1 /* 2 * linux/arch/sh/boards/se/7724/setup.c 3 * 4 * Copyright (C) 2009 Renesas Solutions Corp. 5 * 6 * Kuninori Morimoto <morimoto.kuninori@renesas.com> 7 * 8 * This file is subject to the terms and conditions of the GNU General Public 9 * License. See the file "COPYING" in the main directory of this archive 10 * for more details. 11 */ 12 13 #include <linux/init.h> 14 #include <linux/device.h> 15 #include <linux/interrupt.h> 16 #include <linux/platform_device.h> 17 #include <linux/mtd/physmap.h> 18 #include <linux/delay.h> 19 #include <linux/smc91x.h> 20 #include <linux/gpio.h> 21 #include <linux/input.h> 22 #include <video/sh_mobile_lcdc.h> 23 #include <media/sh_mobile_ceu.h> 24 #include <asm/io.h> 25 #include <asm/heartbeat.h> 26 #include <asm/sh_keysc.h> 27 #include <cpu/sh7724.h> 28 #include <mach-se/mach/se7724.h> 29 30 /* 31 * SWx 1234 5678 32 * ------------------------------------ 33 * SW31 : 1001 1100 : default 34 * SW32 : 0111 1111 : use on board flash 35 * 36 * SW41 : abxx xxxx -> a = 0 : Analog monitor 37 * 1 : Digital monitor 38 * b = 0 : VGA 39 * 1 : SVGA 40 */ 41 42 /* Heartbeat */ 43 static struct heartbeat_data heartbeat_data = { 44 .regsize = 16, 45 }; 46 47 static struct resource heartbeat_resources[] = { 48 [0] = { 49 .start = PA_LED, 50 .end = PA_LED, 51 .flags = IORESOURCE_MEM, 52 }, 53 }; 54 55 static struct platform_device heartbeat_device = { 56 .name = "heartbeat", 57 .id = -1, 58 .dev = { 59 .platform_data = &heartbeat_data, 60 }, 61 .num_resources = ARRAY_SIZE(heartbeat_resources), 62 .resource = heartbeat_resources, 63 }; 64 65 /* LAN91C111 */ 66 static struct smc91x_platdata smc91x_info = { 67 .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, 68 }; 69 70 static struct resource smc91x_eth_resources[] = { 71 [0] = { 72 .name = "SMC91C111" , 73 .start = 0x1a300300, 74 .end = 0x1a30030f, 75 .flags = IORESOURCE_MEM, 76 }, 77 [1] = { 78 .start = IRQ0_SMC, 79 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, 80 }, 81 }; 82 83 static struct platform_device smc91x_eth_device = { 84 .name = "smc91x", 85 .num_resources = ARRAY_SIZE(smc91x_eth_resources), 86 .resource = smc91x_eth_resources, 87 .dev = { 88 .platform_data = &smc91x_info, 89 }, 90 }; 91 92 /* MTD */ 93 static struct mtd_partition nor_flash_partitions[] = { 94 { 95 .name = "uboot", 96 .offset = 0, 97 .size = (1 * 1024 * 1024), 98 .mask_flags = MTD_WRITEABLE, /* Read-only */ 99 }, { 100 .name = "kernel", 101 .offset = MTDPART_OFS_APPEND, 102 .size = (2 * 1024 * 1024), 103 }, { 104 .name = "free-area", 105 .offset = MTDPART_OFS_APPEND, 106 .size = MTDPART_SIZ_FULL, 107 }, 108 }; 109 110 static struct physmap_flash_data nor_flash_data = { 111 .width = 2, 112 .parts = nor_flash_partitions, 113 .nr_parts = ARRAY_SIZE(nor_flash_partitions), 114 }; 115 116 static struct resource nor_flash_resources[] = { 117 [0] = { 118 .name = "NOR Flash", 119 .start = 0x00000000, 120 .end = 0x01ffffff, 121 .flags = IORESOURCE_MEM, 122 } 123 }; 124 125 static struct platform_device nor_flash_device = { 126 .name = "physmap-flash", 127 .resource = nor_flash_resources, 128 .num_resources = ARRAY_SIZE(nor_flash_resources), 129 .dev = { 130 .platform_data = &nor_flash_data, 131 }, 132 }; 133 134 /* LCDC */ 135 static struct sh_mobile_lcdc_info lcdc_info = { 136 .clock_source = LCDC_CLK_EXTERNAL, 137 .ch[0] = { 138 .chan = LCDC_CHAN_MAINLCD, 139 .bpp = 16, 140 .clock_divider = 1, 141 .lcd_cfg = { 142 .name = "LB070WV1", 143 .sync = 0, /* hsync and vsync are active low */ 144 }, 145 .lcd_size_cfg = { /* 7.0 inch */ 146 .width = 152, 147 .height = 91, 148 }, 149 .board_cfg = { 150 }, 151 } 152 }; 153 154 static struct resource lcdc_resources[] = { 155 [0] = { 156 .name = "LCDC", 157 .start = 0xfe940000, 158 .end = 0xfe941fff, 159 .flags = IORESOURCE_MEM, 160 }, 161 [1] = { 162 .start = 106, 163 .flags = IORESOURCE_IRQ, 164 }, 165 }; 166 167 static struct platform_device lcdc_device = { 168 .name = "sh_mobile_lcdc_fb", 169 .num_resources = ARRAY_SIZE(lcdc_resources), 170 .resource = lcdc_resources, 171 .dev = { 172 .platform_data = &lcdc_info, 173 }, 174 }; 175 176 /* CEU0 */ 177 static struct sh_mobile_ceu_info sh_mobile_ceu0_info = { 178 .flags = SH_CEU_FLAG_USE_8BIT_BUS, 179 }; 180 181 static struct resource ceu0_resources[] = { 182 [0] = { 183 .name = "CEU0", 184 .start = 0xfe910000, 185 .end = 0xfe91009f, 186 .flags = IORESOURCE_MEM, 187 }, 188 [1] = { 189 .start = 52, 190 .flags = IORESOURCE_IRQ, 191 }, 192 [2] = { 193 /* place holder for contiguous memory */ 194 }, 195 }; 196 197 static struct platform_device ceu0_device = { 198 .name = "sh_mobile_ceu", 199 .id = 0, /* "ceu0" clock */ 200 .num_resources = ARRAY_SIZE(ceu0_resources), 201 .resource = ceu0_resources, 202 .dev = { 203 .platform_data = &sh_mobile_ceu0_info, 204 }, 205 }; 206 207 /* CEU1 */ 208 static struct sh_mobile_ceu_info sh_mobile_ceu1_info = { 209 .flags = SH_CEU_FLAG_USE_8BIT_BUS, 210 }; 211 212 static struct resource ceu1_resources[] = { 213 [0] = { 214 .name = "CEU1", 215 .start = 0xfe914000, 216 .end = 0xfe91409f, 217 .flags = IORESOURCE_MEM, 218 }, 219 [1] = { 220 .start = 63, 221 .flags = IORESOURCE_IRQ, 222 }, 223 [2] = { 224 /* place holder for contiguous memory */ 225 }, 226 }; 227 228 static struct platform_device ceu1_device = { 229 .name = "sh_mobile_ceu", 230 .id = 1, /* "ceu1" clock */ 231 .num_resources = ARRAY_SIZE(ceu1_resources), 232 .resource = ceu1_resources, 233 .dev = { 234 .platform_data = &sh_mobile_ceu1_info, 235 }, 236 }; 237 238 /* KEYSC */ 239 static struct sh_keysc_info keysc_info = { 240 .mode = SH_KEYSC_MODE_1, 241 .scan_timing = 10, 242 .delay = 50, 243 .keycodes = { 244 KEY_1, KEY_2, KEY_3, KEY_4, KEY_5, 245 KEY_6, KEY_7, KEY_8, KEY_9, KEY_A, 246 KEY_B, KEY_C, KEY_D, KEY_E, KEY_F, 247 KEY_G, KEY_H, KEY_I, KEY_K, KEY_L, 248 KEY_M, KEY_N, KEY_O, KEY_P, KEY_Q, 249 KEY_R, KEY_S, KEY_T, KEY_U, KEY_V, 250 }, 251 }; 252 253 static struct resource keysc_resources[] = { 254 [0] = { 255 .start = 0x1a204000, 256 .end = 0x1a20400f, 257 .flags = IORESOURCE_MEM, 258 }, 259 [1] = { 260 .start = IRQ0_KEY, 261 .flags = IORESOURCE_IRQ, 262 }, 263 }; 264 265 static struct platform_device keysc_device = { 266 .name = "sh_keysc", 267 .id = 0, /* "keysc0" clock */ 268 .num_resources = ARRAY_SIZE(keysc_resources), 269 .resource = keysc_resources, 270 .dev = { 271 .platform_data = &keysc_info, 272 }, 273 }; 274 275 static struct platform_device *ms7724se_devices[] __initdata = { 276 &heartbeat_device, 277 &smc91x_eth_device, 278 &lcdc_device, 279 &nor_flash_device, 280 &ceu0_device, 281 &ceu1_device, 282 &keysc_device, 283 }; 284 285 #define SW4140 0xBA201000 286 #define FPGA_OUT 0xBA200400 287 #define PORT_HIZA 0xA4050158 288 289 #define SW41_A 0x0100 290 #define SW41_B 0x0200 291 #define SW41_C 0x0400 292 #define SW41_D 0x0800 293 #define SW41_E 0x1000 294 #define SW41_F 0x2000 295 #define SW41_G 0x4000 296 #define SW41_H 0x8000 297 static int __init devices_setup(void) 298 { 299 u16 sw = ctrl_inw(SW4140); /* select camera, monitor */ 300 301 /* Reset Release */ 302 ctrl_outw(ctrl_inw(FPGA_OUT) & 303 ~((1 << 1) | /* LAN */ 304 (1 << 6) | /* VIDEO DAC */ 305 (1 << 12)), /* USB0 */ 306 FPGA_OUT); 307 308 /* enable IRQ 0,1,2 */ 309 gpio_request(GPIO_FN_INTC_IRQ0, NULL); 310 gpio_request(GPIO_FN_INTC_IRQ1, NULL); 311 gpio_request(GPIO_FN_INTC_IRQ2, NULL); 312 313 /* enable SCIFA3 */ 314 gpio_request(GPIO_FN_SCIF3_I_SCK, NULL); 315 gpio_request(GPIO_FN_SCIF3_I_RXD, NULL); 316 gpio_request(GPIO_FN_SCIF3_I_TXD, NULL); 317 gpio_request(GPIO_FN_SCIF3_I_CTS, NULL); 318 gpio_request(GPIO_FN_SCIF3_I_RTS, NULL); 319 320 /* enable LCDC */ 321 gpio_request(GPIO_FN_LCDD23, NULL); 322 gpio_request(GPIO_FN_LCDD22, NULL); 323 gpio_request(GPIO_FN_LCDD21, NULL); 324 gpio_request(GPIO_FN_LCDD20, NULL); 325 gpio_request(GPIO_FN_LCDD19, NULL); 326 gpio_request(GPIO_FN_LCDD18, NULL); 327 gpio_request(GPIO_FN_LCDD17, NULL); 328 gpio_request(GPIO_FN_LCDD16, NULL); 329 gpio_request(GPIO_FN_LCDD15, NULL); 330 gpio_request(GPIO_FN_LCDD14, NULL); 331 gpio_request(GPIO_FN_LCDD13, NULL); 332 gpio_request(GPIO_FN_LCDD12, NULL); 333 gpio_request(GPIO_FN_LCDD11, NULL); 334 gpio_request(GPIO_FN_LCDD10, NULL); 335 gpio_request(GPIO_FN_LCDD9, NULL); 336 gpio_request(GPIO_FN_LCDD8, NULL); 337 gpio_request(GPIO_FN_LCDD7, NULL); 338 gpio_request(GPIO_FN_LCDD6, NULL); 339 gpio_request(GPIO_FN_LCDD5, NULL); 340 gpio_request(GPIO_FN_LCDD4, NULL); 341 gpio_request(GPIO_FN_LCDD3, NULL); 342 gpio_request(GPIO_FN_LCDD2, NULL); 343 gpio_request(GPIO_FN_LCDD1, NULL); 344 gpio_request(GPIO_FN_LCDD0, NULL); 345 gpio_request(GPIO_FN_LCDDISP, NULL); 346 gpio_request(GPIO_FN_LCDHSYN, NULL); 347 gpio_request(GPIO_FN_LCDDCK, NULL); 348 gpio_request(GPIO_FN_LCDVSYN, NULL); 349 gpio_request(GPIO_FN_LCDDON, NULL); 350 gpio_request(GPIO_FN_LCDVEPWC, NULL); 351 gpio_request(GPIO_FN_LCDVCPWC, NULL); 352 gpio_request(GPIO_FN_LCDRD, NULL); 353 gpio_request(GPIO_FN_LCDLCLK, NULL); 354 ctrl_outw((ctrl_inw(PORT_HIZA) & ~0x0001), PORT_HIZA); 355 356 /* enable CEU0 */ 357 gpio_request(GPIO_FN_VIO0_D15, NULL); 358 gpio_request(GPIO_FN_VIO0_D14, NULL); 359 gpio_request(GPIO_FN_VIO0_D13, NULL); 360 gpio_request(GPIO_FN_VIO0_D12, NULL); 361 gpio_request(GPIO_FN_VIO0_D11, NULL); 362 gpio_request(GPIO_FN_VIO0_D10, NULL); 363 gpio_request(GPIO_FN_VIO0_D9, NULL); 364 gpio_request(GPIO_FN_VIO0_D8, NULL); 365 gpio_request(GPIO_FN_VIO0_D7, NULL); 366 gpio_request(GPIO_FN_VIO0_D6, NULL); 367 gpio_request(GPIO_FN_VIO0_D5, NULL); 368 gpio_request(GPIO_FN_VIO0_D4, NULL); 369 gpio_request(GPIO_FN_VIO0_D3, NULL); 370 gpio_request(GPIO_FN_VIO0_D2, NULL); 371 gpio_request(GPIO_FN_VIO0_D1, NULL); 372 gpio_request(GPIO_FN_VIO0_D0, NULL); 373 gpio_request(GPIO_FN_VIO0_VD, NULL); 374 gpio_request(GPIO_FN_VIO0_CLK, NULL); 375 gpio_request(GPIO_FN_VIO0_FLD, NULL); 376 gpio_request(GPIO_FN_VIO0_HD, NULL); 377 platform_resource_setup_memory(&ceu0_device, "ceu", 4 << 20); 378 379 /* enable CEU1 */ 380 gpio_request(GPIO_FN_VIO1_D7, NULL); 381 gpio_request(GPIO_FN_VIO1_D6, NULL); 382 gpio_request(GPIO_FN_VIO1_D5, NULL); 383 gpio_request(GPIO_FN_VIO1_D4, NULL); 384 gpio_request(GPIO_FN_VIO1_D3, NULL); 385 gpio_request(GPIO_FN_VIO1_D2, NULL); 386 gpio_request(GPIO_FN_VIO1_D1, NULL); 387 gpio_request(GPIO_FN_VIO1_D0, NULL); 388 gpio_request(GPIO_FN_VIO1_FLD, NULL); 389 gpio_request(GPIO_FN_VIO1_HD, NULL); 390 gpio_request(GPIO_FN_VIO1_VD, NULL); 391 gpio_request(GPIO_FN_VIO1_CLK, NULL); 392 platform_resource_setup_memory(&ceu1_device, "ceu", 4 << 20); 393 394 /* KEYSC */ 395 gpio_request(GPIO_FN_KEYOUT5_IN5, NULL); 396 gpio_request(GPIO_FN_KEYOUT4_IN6, NULL); 397 gpio_request(GPIO_FN_KEYIN4, NULL); 398 gpio_request(GPIO_FN_KEYIN3, NULL); 399 gpio_request(GPIO_FN_KEYIN2, NULL); 400 gpio_request(GPIO_FN_KEYIN1, NULL); 401 gpio_request(GPIO_FN_KEYIN0, NULL); 402 gpio_request(GPIO_FN_KEYOUT3, NULL); 403 gpio_request(GPIO_FN_KEYOUT2, NULL); 404 gpio_request(GPIO_FN_KEYOUT1, NULL); 405 gpio_request(GPIO_FN_KEYOUT0, NULL); 406 407 if (sw & SW41_B) { 408 /* SVGA */ 409 lcdc_info.ch[0].lcd_cfg.xres = 800; 410 lcdc_info.ch[0].lcd_cfg.yres = 600; 411 lcdc_info.ch[0].lcd_cfg.left_margin = 142; 412 lcdc_info.ch[0].lcd_cfg.right_margin = 52; 413 lcdc_info.ch[0].lcd_cfg.hsync_len = 96; 414 lcdc_info.ch[0].lcd_cfg.upper_margin = 24; 415 lcdc_info.ch[0].lcd_cfg.lower_margin = 2; 416 lcdc_info.ch[0].lcd_cfg.vsync_len = 2; 417 } else { 418 /* VGA */ 419 lcdc_info.ch[0].lcd_cfg.xres = 640; 420 lcdc_info.ch[0].lcd_cfg.yres = 480; 421 lcdc_info.ch[0].lcd_cfg.left_margin = 105; 422 lcdc_info.ch[0].lcd_cfg.right_margin = 50; 423 lcdc_info.ch[0].lcd_cfg.hsync_len = 96; 424 lcdc_info.ch[0].lcd_cfg.upper_margin = 33; 425 lcdc_info.ch[0].lcd_cfg.lower_margin = 10; 426 lcdc_info.ch[0].lcd_cfg.vsync_len = 2; 427 } 428 429 if (sw & SW41_A) { 430 /* Digital monitor */ 431 lcdc_info.ch[0].interface_type = RGB18; 432 lcdc_info.ch[0].flags = 0; 433 } else { 434 /* Analog monitor */ 435 lcdc_info.ch[0].interface_type = RGB24; 436 lcdc_info.ch[0].flags = LCDC_FLAGS_DWPOL; 437 } 438 439 return platform_add_devices(ms7724se_devices, 440 ARRAY_SIZE(ms7724se_devices)); 441 } 442 device_initcall(devices_setup); 443 444 static struct sh_machine_vector mv_ms7724se __initmv = { 445 .mv_name = "ms7724se", 446 .mv_init_irq = init_se7724_IRQ, 447 .mv_nr_irqs = SE7724_FPGA_IRQ_BASE + SE7724_FPGA_IRQ_NR, 448 }; 449