1 /* 2 * linux/arch/sh/boards/se/7724/setup.c 3 * 4 * Copyright (C) 2009 Renesas Solutions Corp. 5 * 6 * Kuninori Morimoto <morimoto.kuninori@renesas.com> 7 * 8 * This file is subject to the terms and conditions of the GNU General Public 9 * License. See the file "COPYING" in the main directory of this archive 10 * for more details. 11 */ 12 13 #include <linux/init.h> 14 #include <linux/device.h> 15 #include <linux/interrupt.h> 16 #include <linux/platform_device.h> 17 #include <linux/mfd/sh_mobile_sdhi.h> 18 #include <linux/mmc/host.h> 19 #include <linux/mtd/physmap.h> 20 #include <linux/delay.h> 21 #include <linux/smc91x.h> 22 #include <linux/gpio.h> 23 #include <linux/input.h> 24 #include <linux/input/sh_keysc.h> 25 #include <linux/usb/r8a66597.h> 26 #include <video/sh_mobile_lcdc.h> 27 #include <media/sh_mobile_ceu.h> 28 #include <sound/sh_fsi.h> 29 #include <asm/io.h> 30 #include <asm/heartbeat.h> 31 #include <asm/sh_eth.h> 32 #include <asm/clock.h> 33 #include <asm/suspend.h> 34 #include <cpu/sh7724.h> 35 #include <mach-se/mach/se7724.h> 36 37 /* 38 * SWx 1234 5678 39 * ------------------------------------ 40 * SW31 : 1001 1100 : default 41 * SW32 : 0111 1111 : use on board flash 42 * 43 * SW41 : abxx xxxx -> a = 0 : Analog monitor 44 * 1 : Digital monitor 45 * b = 0 : VGA 46 * 1 : 720p 47 */ 48 49 /* 50 * about 720p 51 * 52 * When you use 1280 x 720 lcdc output, 53 * you should change OSC6 lcdc clock from 25.175MHz to 74.25MHz, 54 * and change SW41 to use 720p 55 */ 56 57 /* 58 * about sound 59 * 60 * This setup.c supports FSI slave mode. 61 * Please change J20, J21, J22 pin to 1-2 connection. 62 */ 63 64 /* Heartbeat */ 65 static struct resource heartbeat_resource = { 66 .start = PA_LED, 67 .end = PA_LED, 68 .flags = IORESOURCE_MEM | IORESOURCE_MEM_16BIT, 69 }; 70 71 static struct platform_device heartbeat_device = { 72 .name = "heartbeat", 73 .id = -1, 74 .num_resources = 1, 75 .resource = &heartbeat_resource, 76 }; 77 78 /* LAN91C111 */ 79 static struct smc91x_platdata smc91x_info = { 80 .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, 81 }; 82 83 static struct resource smc91x_eth_resources[] = { 84 [0] = { 85 .name = "SMC91C111" , 86 .start = 0x1a300300, 87 .end = 0x1a30030f, 88 .flags = IORESOURCE_MEM, 89 }, 90 [1] = { 91 .start = IRQ0_SMC, 92 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, 93 }, 94 }; 95 96 static struct platform_device smc91x_eth_device = { 97 .name = "smc91x", 98 .num_resources = ARRAY_SIZE(smc91x_eth_resources), 99 .resource = smc91x_eth_resources, 100 .dev = { 101 .platform_data = &smc91x_info, 102 }, 103 }; 104 105 /* MTD */ 106 static struct mtd_partition nor_flash_partitions[] = { 107 { 108 .name = "uboot", 109 .offset = 0, 110 .size = (1 * 1024 * 1024), 111 .mask_flags = MTD_WRITEABLE, /* Read-only */ 112 }, { 113 .name = "kernel", 114 .offset = MTDPART_OFS_APPEND, 115 .size = (2 * 1024 * 1024), 116 }, { 117 .name = "free-area", 118 .offset = MTDPART_OFS_APPEND, 119 .size = MTDPART_SIZ_FULL, 120 }, 121 }; 122 123 static struct physmap_flash_data nor_flash_data = { 124 .width = 2, 125 .parts = nor_flash_partitions, 126 .nr_parts = ARRAY_SIZE(nor_flash_partitions), 127 }; 128 129 static struct resource nor_flash_resources[] = { 130 [0] = { 131 .name = "NOR Flash", 132 .start = 0x00000000, 133 .end = 0x01ffffff, 134 .flags = IORESOURCE_MEM, 135 } 136 }; 137 138 static struct platform_device nor_flash_device = { 139 .name = "physmap-flash", 140 .resource = nor_flash_resources, 141 .num_resources = ARRAY_SIZE(nor_flash_resources), 142 .dev = { 143 .platform_data = &nor_flash_data, 144 }, 145 }; 146 147 /* LCDC */ 148 const static struct fb_videomode lcdc_720p_modes[] = { 149 { 150 .name = "LB070WV1", 151 .sync = 0, /* hsync and vsync are active low */ 152 .xres = 1280, 153 .yres = 720, 154 .left_margin = 220, 155 .right_margin = 110, 156 .hsync_len = 40, 157 .upper_margin = 20, 158 .lower_margin = 5, 159 .vsync_len = 5, 160 }, 161 }; 162 163 const static struct fb_videomode lcdc_vga_modes[] = { 164 { 165 .name = "LB070WV1", 166 .sync = 0, /* hsync and vsync are active low */ 167 .xres = 640, 168 .yres = 480, 169 .left_margin = 105, 170 .right_margin = 50, 171 .hsync_len = 96, 172 .upper_margin = 33, 173 .lower_margin = 10, 174 .vsync_len = 2, 175 }, 176 }; 177 178 static struct sh_mobile_lcdc_info lcdc_info = { 179 .clock_source = LCDC_CLK_EXTERNAL, 180 .ch[0] = { 181 .chan = LCDC_CHAN_MAINLCD, 182 .bpp = 16, 183 .clock_divider = 1, 184 .lcd_size_cfg = { /* 7.0 inch */ 185 .width = 152, 186 .height = 91, 187 }, 188 .board_cfg = { 189 }, 190 } 191 }; 192 193 static struct resource lcdc_resources[] = { 194 [0] = { 195 .name = "LCDC", 196 .start = 0xfe940000, 197 .end = 0xfe942fff, 198 .flags = IORESOURCE_MEM, 199 }, 200 [1] = { 201 .start = 106, 202 .flags = IORESOURCE_IRQ, 203 }, 204 }; 205 206 static struct platform_device lcdc_device = { 207 .name = "sh_mobile_lcdc_fb", 208 .num_resources = ARRAY_SIZE(lcdc_resources), 209 .resource = lcdc_resources, 210 .dev = { 211 .platform_data = &lcdc_info, 212 }, 213 .archdata = { 214 .hwblk_id = HWBLK_LCDC, 215 }, 216 }; 217 218 /* CEU0 */ 219 static struct sh_mobile_ceu_info sh_mobile_ceu0_info = { 220 .flags = SH_CEU_FLAG_USE_8BIT_BUS, 221 }; 222 223 static struct resource ceu0_resources[] = { 224 [0] = { 225 .name = "CEU0", 226 .start = 0xfe910000, 227 .end = 0xfe91009f, 228 .flags = IORESOURCE_MEM, 229 }, 230 [1] = { 231 .start = 52, 232 .flags = IORESOURCE_IRQ, 233 }, 234 [2] = { 235 /* place holder for contiguous memory */ 236 }, 237 }; 238 239 static struct platform_device ceu0_device = { 240 .name = "sh_mobile_ceu", 241 .id = 0, /* "ceu0" clock */ 242 .num_resources = ARRAY_SIZE(ceu0_resources), 243 .resource = ceu0_resources, 244 .dev = { 245 .platform_data = &sh_mobile_ceu0_info, 246 }, 247 .archdata = { 248 .hwblk_id = HWBLK_CEU0, 249 }, 250 }; 251 252 /* CEU1 */ 253 static struct sh_mobile_ceu_info sh_mobile_ceu1_info = { 254 .flags = SH_CEU_FLAG_USE_8BIT_BUS, 255 }; 256 257 static struct resource ceu1_resources[] = { 258 [0] = { 259 .name = "CEU1", 260 .start = 0xfe914000, 261 .end = 0xfe91409f, 262 .flags = IORESOURCE_MEM, 263 }, 264 [1] = { 265 .start = 63, 266 .flags = IORESOURCE_IRQ, 267 }, 268 [2] = { 269 /* place holder for contiguous memory */ 270 }, 271 }; 272 273 static struct platform_device ceu1_device = { 274 .name = "sh_mobile_ceu", 275 .id = 1, /* "ceu1" clock */ 276 .num_resources = ARRAY_SIZE(ceu1_resources), 277 .resource = ceu1_resources, 278 .dev = { 279 .platform_data = &sh_mobile_ceu1_info, 280 }, 281 .archdata = { 282 .hwblk_id = HWBLK_CEU1, 283 }, 284 }; 285 286 /* FSI */ 287 /* change J20, J21, J22 pin to 1-2 connection to use slave mode */ 288 static struct sh_fsi_platform_info fsi_info = { 289 .porta_flags = SH_FSI_BRS_INV | 290 SH_FSI_OUT_SLAVE_MODE | 291 SH_FSI_IN_SLAVE_MODE | 292 SH_FSI_OFMT(PCM) | 293 SH_FSI_IFMT(PCM), 294 }; 295 296 static struct resource fsi_resources[] = { 297 [0] = { 298 .name = "FSI", 299 .start = 0xFE3C0000, 300 .end = 0xFE3C021d, 301 .flags = IORESOURCE_MEM, 302 }, 303 [1] = { 304 .start = 108, 305 .flags = IORESOURCE_IRQ, 306 }, 307 }; 308 309 static struct platform_device fsi_device = { 310 .name = "sh_fsi", 311 .id = 0, 312 .num_resources = ARRAY_SIZE(fsi_resources), 313 .resource = fsi_resources, 314 .dev = { 315 .platform_data = &fsi_info, 316 }, 317 .archdata = { 318 .hwblk_id = HWBLK_SPU, /* FSI needs SPU hwblk */ 319 }, 320 }; 321 322 static struct platform_device fsi_ak4642_device = { 323 .name = "sh_fsi_a_ak4642", 324 }; 325 326 /* KEYSC in SoC (Needs SW33-2 set to ON) */ 327 static struct sh_keysc_info keysc_info = { 328 .mode = SH_KEYSC_MODE_1, 329 .scan_timing = 3, 330 .delay = 50, 331 .keycodes = { 332 KEY_1, KEY_2, KEY_3, KEY_4, KEY_5, 333 KEY_6, KEY_7, KEY_8, KEY_9, KEY_A, 334 KEY_B, KEY_C, KEY_D, KEY_E, KEY_F, 335 KEY_G, KEY_H, KEY_I, KEY_K, KEY_L, 336 KEY_M, KEY_N, KEY_O, KEY_P, KEY_Q, 337 KEY_R, KEY_S, KEY_T, KEY_U, KEY_V, 338 }, 339 }; 340 341 static struct resource keysc_resources[] = { 342 [0] = { 343 .name = "KEYSC", 344 .start = 0x044b0000, 345 .end = 0x044b000f, 346 .flags = IORESOURCE_MEM, 347 }, 348 [1] = { 349 .start = 79, 350 .flags = IORESOURCE_IRQ, 351 }, 352 }; 353 354 static struct platform_device keysc_device = { 355 .name = "sh_keysc", 356 .id = 0, /* "keysc0" clock */ 357 .num_resources = ARRAY_SIZE(keysc_resources), 358 .resource = keysc_resources, 359 .dev = { 360 .platform_data = &keysc_info, 361 }, 362 .archdata = { 363 .hwblk_id = HWBLK_KEYSC, 364 }, 365 }; 366 367 /* SH Eth */ 368 static struct resource sh_eth_resources[] = { 369 [0] = { 370 .start = SH_ETH_ADDR, 371 .end = SH_ETH_ADDR + 0x1FC, 372 .flags = IORESOURCE_MEM, 373 }, 374 [1] = { 375 .start = 91, 376 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, 377 }, 378 }; 379 380 static struct sh_eth_plat_data sh_eth_plat = { 381 .phy = 0x1f, /* SMSC LAN8187 */ 382 .edmac_endian = EDMAC_LITTLE_ENDIAN, 383 }; 384 385 static struct platform_device sh_eth_device = { 386 .name = "sh-eth", 387 .id = 0, 388 .dev = { 389 .platform_data = &sh_eth_plat, 390 }, 391 .num_resources = ARRAY_SIZE(sh_eth_resources), 392 .resource = sh_eth_resources, 393 .archdata = { 394 .hwblk_id = HWBLK_ETHER, 395 }, 396 }; 397 398 static struct r8a66597_platdata sh7724_usb0_host_data = { 399 .on_chip = 1, 400 }; 401 402 static struct resource sh7724_usb0_host_resources[] = { 403 [0] = { 404 .start = 0xa4d80000, 405 .end = 0xa4d80124 - 1, 406 .flags = IORESOURCE_MEM, 407 }, 408 [1] = { 409 .start = 65, 410 .end = 65, 411 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW, 412 }, 413 }; 414 415 static struct platform_device sh7724_usb0_host_device = { 416 .name = "r8a66597_hcd", 417 .id = 0, 418 .dev = { 419 .dma_mask = NULL, /* not use dma */ 420 .coherent_dma_mask = 0xffffffff, 421 .platform_data = &sh7724_usb0_host_data, 422 }, 423 .num_resources = ARRAY_SIZE(sh7724_usb0_host_resources), 424 .resource = sh7724_usb0_host_resources, 425 .archdata = { 426 .hwblk_id = HWBLK_USB0, 427 }, 428 }; 429 430 static struct r8a66597_platdata sh7724_usb1_gadget_data = { 431 .on_chip = 1, 432 }; 433 434 static struct resource sh7724_usb1_gadget_resources[] = { 435 [0] = { 436 .start = 0xa4d90000, 437 .end = 0xa4d90123, 438 .flags = IORESOURCE_MEM, 439 }, 440 [1] = { 441 .start = 66, 442 .end = 66, 443 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW, 444 }, 445 }; 446 447 static struct platform_device sh7724_usb1_gadget_device = { 448 .name = "r8a66597_udc", 449 .id = 1, /* USB1 */ 450 .dev = { 451 .dma_mask = NULL, /* not use dma */ 452 .coherent_dma_mask = 0xffffffff, 453 .platform_data = &sh7724_usb1_gadget_data, 454 }, 455 .num_resources = ARRAY_SIZE(sh7724_usb1_gadget_resources), 456 .resource = sh7724_usb1_gadget_resources, 457 }; 458 459 static struct resource sdhi0_cn7_resources[] = { 460 [0] = { 461 .name = "SDHI0", 462 .start = 0x04ce0000, 463 .end = 0x04ce01ff, 464 .flags = IORESOURCE_MEM, 465 }, 466 [1] = { 467 .start = 100, 468 .flags = IORESOURCE_IRQ, 469 }, 470 }; 471 472 static struct sh_mobile_sdhi_info sh7724_sdhi0_data = { 473 .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX, 474 .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX, 475 .tmio_caps = MMC_CAP_SDIO_IRQ, 476 }; 477 478 static struct platform_device sdhi0_cn7_device = { 479 .name = "sh_mobile_sdhi", 480 .id = 0, 481 .num_resources = ARRAY_SIZE(sdhi0_cn7_resources), 482 .resource = sdhi0_cn7_resources, 483 .dev = { 484 .platform_data = &sh7724_sdhi0_data, 485 }, 486 .archdata = { 487 .hwblk_id = HWBLK_SDHI0, 488 }, 489 }; 490 491 static struct resource sdhi1_cn8_resources[] = { 492 [0] = { 493 .name = "SDHI1", 494 .start = 0x04cf0000, 495 .end = 0x04cf01ff, 496 .flags = IORESOURCE_MEM, 497 }, 498 [1] = { 499 .start = 23, 500 .flags = IORESOURCE_IRQ, 501 }, 502 }; 503 504 static struct sh_mobile_sdhi_info sh7724_sdhi1_data = { 505 .dma_slave_tx = SHDMA_SLAVE_SDHI1_TX, 506 .dma_slave_rx = SHDMA_SLAVE_SDHI1_RX, 507 .tmio_caps = MMC_CAP_SDIO_IRQ, 508 }; 509 510 static struct platform_device sdhi1_cn8_device = { 511 .name = "sh_mobile_sdhi", 512 .id = 1, 513 .num_resources = ARRAY_SIZE(sdhi1_cn8_resources), 514 .resource = sdhi1_cn8_resources, 515 .dev = { 516 .platform_data = &sh7724_sdhi1_data, 517 }, 518 .archdata = { 519 .hwblk_id = HWBLK_SDHI1, 520 }, 521 }; 522 523 /* IrDA */ 524 static struct resource irda_resources[] = { 525 [0] = { 526 .name = "IrDA", 527 .start = 0xA45D0000, 528 .end = 0xA45D0049, 529 .flags = IORESOURCE_MEM, 530 }, 531 [1] = { 532 .start = 20, 533 .flags = IORESOURCE_IRQ, 534 }, 535 }; 536 537 static struct platform_device irda_device = { 538 .name = "sh_sir", 539 .num_resources = ARRAY_SIZE(irda_resources), 540 .resource = irda_resources, 541 }; 542 543 #include <media/ak881x.h> 544 #include <media/sh_vou.h> 545 546 static struct ak881x_pdata ak881x_pdata = { 547 .flags = AK881X_IF_MODE_SLAVE, 548 }; 549 550 static struct i2c_board_info ak8813 = { 551 /* With open J18 jumper address is 0x21 */ 552 I2C_BOARD_INFO("ak8813", 0x20), 553 .platform_data = &ak881x_pdata, 554 }; 555 556 static struct sh_vou_pdata sh_vou_pdata = { 557 .bus_fmt = SH_VOU_BUS_8BIT, 558 .flags = SH_VOU_HSYNC_LOW | SH_VOU_VSYNC_LOW, 559 .board_info = &ak8813, 560 .i2c_adap = 0, 561 }; 562 563 static struct resource sh_vou_resources[] = { 564 [0] = { 565 .start = 0xfe960000, 566 .end = 0xfe962043, 567 .flags = IORESOURCE_MEM, 568 }, 569 [1] = { 570 .start = 55, 571 .flags = IORESOURCE_IRQ, 572 }, 573 }; 574 575 static struct platform_device vou_device = { 576 .name = "sh-vou", 577 .id = -1, 578 .num_resources = ARRAY_SIZE(sh_vou_resources), 579 .resource = sh_vou_resources, 580 .dev = { 581 .platform_data = &sh_vou_pdata, 582 }, 583 .archdata = { 584 .hwblk_id = HWBLK_VOU, 585 }, 586 }; 587 588 static struct platform_device *ms7724se_devices[] __initdata = { 589 &heartbeat_device, 590 &smc91x_eth_device, 591 &lcdc_device, 592 &nor_flash_device, 593 &ceu0_device, 594 &ceu1_device, 595 &keysc_device, 596 &sh_eth_device, 597 &sh7724_usb0_host_device, 598 &sh7724_usb1_gadget_device, 599 &fsi_device, 600 &fsi_ak4642_device, 601 &sdhi0_cn7_device, 602 &sdhi1_cn8_device, 603 &irda_device, 604 &vou_device, 605 }; 606 607 /* I2C device */ 608 static struct i2c_board_info i2c0_devices[] = { 609 { 610 I2C_BOARD_INFO("ak4642", 0x12), 611 }, 612 }; 613 614 #define EEPROM_OP 0xBA206000 615 #define EEPROM_ADR 0xBA206004 616 #define EEPROM_DATA 0xBA20600C 617 #define EEPROM_STAT 0xBA206010 618 #define EEPROM_STRT 0xBA206014 619 static int __init sh_eth_is_eeprom_ready(void) 620 { 621 int t = 10000; 622 623 while (t--) { 624 if (!__raw_readw(EEPROM_STAT)) 625 return 1; 626 udelay(1); 627 } 628 629 printk(KERN_ERR "ms7724se can not access to eeprom\n"); 630 return 0; 631 } 632 633 static void __init sh_eth_init(void) 634 { 635 int i; 636 u16 mac; 637 638 /* check EEPROM status */ 639 if (!sh_eth_is_eeprom_ready()) 640 return; 641 642 /* read MAC addr from EEPROM */ 643 for (i = 0 ; i < 3 ; i++) { 644 __raw_writew(0x0, EEPROM_OP); /* read */ 645 __raw_writew(i*2, EEPROM_ADR); 646 __raw_writew(0x1, EEPROM_STRT); 647 if (!sh_eth_is_eeprom_ready()) 648 return; 649 650 mac = __raw_readw(EEPROM_DATA); 651 sh_eth_plat.mac_addr[i << 1] = mac & 0xff; 652 sh_eth_plat.mac_addr[(i << 1) + 1] = mac >> 8; 653 } 654 } 655 656 #define SW4140 0xBA201000 657 #define FPGA_OUT 0xBA200400 658 #define PORT_HIZA 0xA4050158 659 #define PORT_MSELCRB 0xA4050182 660 661 #define SW41_A 0x0100 662 #define SW41_B 0x0200 663 #define SW41_C 0x0400 664 #define SW41_D 0x0800 665 #define SW41_E 0x1000 666 #define SW41_F 0x2000 667 #define SW41_G 0x4000 668 #define SW41_H 0x8000 669 670 extern char ms7724se_sdram_enter_start; 671 extern char ms7724se_sdram_enter_end; 672 extern char ms7724se_sdram_leave_start; 673 extern char ms7724se_sdram_leave_end; 674 675 676 static int __init arch_setup(void) 677 { 678 /* enable I2C device */ 679 i2c_register_board_info(0, i2c0_devices, 680 ARRAY_SIZE(i2c0_devices)); 681 return 0; 682 } 683 arch_initcall(arch_setup); 684 685 static int __init devices_setup(void) 686 { 687 u16 sw = __raw_readw(SW4140); /* select camera, monitor */ 688 struct clk *clk; 689 u16 fpga_out; 690 691 /* register board specific self-refresh code */ 692 sh_mobile_register_self_refresh(SUSP_SH_STANDBY | SUSP_SH_SF | 693 SUSP_SH_RSTANDBY, 694 &ms7724se_sdram_enter_start, 695 &ms7724se_sdram_enter_end, 696 &ms7724se_sdram_leave_start, 697 &ms7724se_sdram_leave_end); 698 /* Reset Release */ 699 fpga_out = __raw_readw(FPGA_OUT); 700 /* bit4: NTSC_PDN, bit5: NTSC_RESET */ 701 fpga_out &= ~((1 << 1) | /* LAN */ 702 (1 << 4) | /* AK8813 PDN */ 703 (1 << 5) | /* AK8813 RESET */ 704 (1 << 6) | /* VIDEO DAC */ 705 (1 << 7) | /* AK4643 */ 706 (1 << 8) | /* IrDA */ 707 (1 << 12) | /* USB0 */ 708 (1 << 14)); /* RMII */ 709 __raw_writew(fpga_out | (1 << 4), FPGA_OUT); 710 711 udelay(10); 712 713 /* AK8813 RESET */ 714 __raw_writew(fpga_out | (1 << 5), FPGA_OUT); 715 716 udelay(10); 717 718 __raw_writew(fpga_out, FPGA_OUT); 719 720 /* turn on USB clocks, use external clock */ 721 __raw_writew((__raw_readw(PORT_MSELCRB) & ~0xc000) | 0x8000, PORT_MSELCRB); 722 723 /* Let LED9 show STATUS2 */ 724 gpio_request(GPIO_FN_STATUS2, NULL); 725 726 /* Lit LED10 show STATUS0 */ 727 gpio_request(GPIO_FN_STATUS0, NULL); 728 729 /* Lit LED11 show PDSTATUS */ 730 gpio_request(GPIO_FN_PDSTATUS, NULL); 731 732 /* enable USB0 port */ 733 __raw_writew(0x0600, 0xa40501d4); 734 735 /* enable USB1 port */ 736 __raw_writew(0x0600, 0xa4050192); 737 738 /* enable IRQ 0,1,2 */ 739 gpio_request(GPIO_FN_INTC_IRQ0, NULL); 740 gpio_request(GPIO_FN_INTC_IRQ1, NULL); 741 gpio_request(GPIO_FN_INTC_IRQ2, NULL); 742 743 /* enable SCIFA3 */ 744 gpio_request(GPIO_FN_SCIF3_I_SCK, NULL); 745 gpio_request(GPIO_FN_SCIF3_I_RXD, NULL); 746 gpio_request(GPIO_FN_SCIF3_I_TXD, NULL); 747 gpio_request(GPIO_FN_SCIF3_I_CTS, NULL); 748 gpio_request(GPIO_FN_SCIF3_I_RTS, NULL); 749 750 /* enable LCDC */ 751 gpio_request(GPIO_FN_LCDD23, NULL); 752 gpio_request(GPIO_FN_LCDD22, NULL); 753 gpio_request(GPIO_FN_LCDD21, NULL); 754 gpio_request(GPIO_FN_LCDD20, NULL); 755 gpio_request(GPIO_FN_LCDD19, NULL); 756 gpio_request(GPIO_FN_LCDD18, NULL); 757 gpio_request(GPIO_FN_LCDD17, NULL); 758 gpio_request(GPIO_FN_LCDD16, NULL); 759 gpio_request(GPIO_FN_LCDD15, NULL); 760 gpio_request(GPIO_FN_LCDD14, NULL); 761 gpio_request(GPIO_FN_LCDD13, NULL); 762 gpio_request(GPIO_FN_LCDD12, NULL); 763 gpio_request(GPIO_FN_LCDD11, NULL); 764 gpio_request(GPIO_FN_LCDD10, NULL); 765 gpio_request(GPIO_FN_LCDD9, NULL); 766 gpio_request(GPIO_FN_LCDD8, NULL); 767 gpio_request(GPIO_FN_LCDD7, NULL); 768 gpio_request(GPIO_FN_LCDD6, NULL); 769 gpio_request(GPIO_FN_LCDD5, NULL); 770 gpio_request(GPIO_FN_LCDD4, NULL); 771 gpio_request(GPIO_FN_LCDD3, NULL); 772 gpio_request(GPIO_FN_LCDD2, NULL); 773 gpio_request(GPIO_FN_LCDD1, NULL); 774 gpio_request(GPIO_FN_LCDD0, NULL); 775 gpio_request(GPIO_FN_LCDDISP, NULL); 776 gpio_request(GPIO_FN_LCDHSYN, NULL); 777 gpio_request(GPIO_FN_LCDDCK, NULL); 778 gpio_request(GPIO_FN_LCDVSYN, NULL); 779 gpio_request(GPIO_FN_LCDDON, NULL); 780 gpio_request(GPIO_FN_LCDVEPWC, NULL); 781 gpio_request(GPIO_FN_LCDVCPWC, NULL); 782 gpio_request(GPIO_FN_LCDRD, NULL); 783 gpio_request(GPIO_FN_LCDLCLK, NULL); 784 __raw_writew((__raw_readw(PORT_HIZA) & ~0x0001), PORT_HIZA); 785 786 /* enable CEU0 */ 787 gpio_request(GPIO_FN_VIO0_D15, NULL); 788 gpio_request(GPIO_FN_VIO0_D14, NULL); 789 gpio_request(GPIO_FN_VIO0_D13, NULL); 790 gpio_request(GPIO_FN_VIO0_D12, NULL); 791 gpio_request(GPIO_FN_VIO0_D11, NULL); 792 gpio_request(GPIO_FN_VIO0_D10, NULL); 793 gpio_request(GPIO_FN_VIO0_D9, NULL); 794 gpio_request(GPIO_FN_VIO0_D8, NULL); 795 gpio_request(GPIO_FN_VIO0_D7, NULL); 796 gpio_request(GPIO_FN_VIO0_D6, NULL); 797 gpio_request(GPIO_FN_VIO0_D5, NULL); 798 gpio_request(GPIO_FN_VIO0_D4, NULL); 799 gpio_request(GPIO_FN_VIO0_D3, NULL); 800 gpio_request(GPIO_FN_VIO0_D2, NULL); 801 gpio_request(GPIO_FN_VIO0_D1, NULL); 802 gpio_request(GPIO_FN_VIO0_D0, NULL); 803 gpio_request(GPIO_FN_VIO0_VD, NULL); 804 gpio_request(GPIO_FN_VIO0_CLK, NULL); 805 gpio_request(GPIO_FN_VIO0_FLD, NULL); 806 gpio_request(GPIO_FN_VIO0_HD, NULL); 807 platform_resource_setup_memory(&ceu0_device, "ceu0", 4 << 20); 808 809 /* enable CEU1 */ 810 gpio_request(GPIO_FN_VIO1_D7, NULL); 811 gpio_request(GPIO_FN_VIO1_D6, NULL); 812 gpio_request(GPIO_FN_VIO1_D5, NULL); 813 gpio_request(GPIO_FN_VIO1_D4, NULL); 814 gpio_request(GPIO_FN_VIO1_D3, NULL); 815 gpio_request(GPIO_FN_VIO1_D2, NULL); 816 gpio_request(GPIO_FN_VIO1_D1, NULL); 817 gpio_request(GPIO_FN_VIO1_D0, NULL); 818 gpio_request(GPIO_FN_VIO1_FLD, NULL); 819 gpio_request(GPIO_FN_VIO1_HD, NULL); 820 gpio_request(GPIO_FN_VIO1_VD, NULL); 821 gpio_request(GPIO_FN_VIO1_CLK, NULL); 822 platform_resource_setup_memory(&ceu1_device, "ceu1", 4 << 20); 823 824 /* KEYSC */ 825 gpio_request(GPIO_FN_KEYOUT5_IN5, NULL); 826 gpio_request(GPIO_FN_KEYOUT4_IN6, NULL); 827 gpio_request(GPIO_FN_KEYIN4, NULL); 828 gpio_request(GPIO_FN_KEYIN3, NULL); 829 gpio_request(GPIO_FN_KEYIN2, NULL); 830 gpio_request(GPIO_FN_KEYIN1, NULL); 831 gpio_request(GPIO_FN_KEYIN0, NULL); 832 gpio_request(GPIO_FN_KEYOUT3, NULL); 833 gpio_request(GPIO_FN_KEYOUT2, NULL); 834 gpio_request(GPIO_FN_KEYOUT1, NULL); 835 gpio_request(GPIO_FN_KEYOUT0, NULL); 836 837 /* enable FSI */ 838 gpio_request(GPIO_FN_FSIMCKA, NULL); 839 gpio_request(GPIO_FN_FSIIASD, NULL); 840 gpio_request(GPIO_FN_FSIOASD, NULL); 841 gpio_request(GPIO_FN_FSIIABCK, NULL); 842 gpio_request(GPIO_FN_FSIIALRCK, NULL); 843 gpio_request(GPIO_FN_FSIOABCK, NULL); 844 gpio_request(GPIO_FN_FSIOALRCK, NULL); 845 gpio_request(GPIO_FN_CLKAUDIOAO, NULL); 846 847 /* set SPU2 clock to 83.4 MHz */ 848 clk = clk_get(NULL, "spu_clk"); 849 if (!IS_ERR(clk)) { 850 clk_set_rate(clk, clk_round_rate(clk, 83333333)); 851 clk_put(clk); 852 } 853 854 /* change parent of FSI A */ 855 clk = clk_get(NULL, "fsia_clk"); 856 if (!IS_ERR(clk)) { 857 /* 48kHz dummy clock was used to make sure 1/1 divide */ 858 clk_set_rate(&sh7724_fsimcka_clk, 48000); 859 clk_set_parent(clk, &sh7724_fsimcka_clk); 860 clk_set_rate(clk, 48000); 861 clk_put(clk); 862 } 863 864 /* SDHI0 connected to cn7 */ 865 gpio_request(GPIO_FN_SDHI0CD, NULL); 866 gpio_request(GPIO_FN_SDHI0WP, NULL); 867 gpio_request(GPIO_FN_SDHI0D3, NULL); 868 gpio_request(GPIO_FN_SDHI0D2, NULL); 869 gpio_request(GPIO_FN_SDHI0D1, NULL); 870 gpio_request(GPIO_FN_SDHI0D0, NULL); 871 gpio_request(GPIO_FN_SDHI0CMD, NULL); 872 gpio_request(GPIO_FN_SDHI0CLK, NULL); 873 874 /* SDHI1 connected to cn8 */ 875 gpio_request(GPIO_FN_SDHI1CD, NULL); 876 gpio_request(GPIO_FN_SDHI1WP, NULL); 877 gpio_request(GPIO_FN_SDHI1D3, NULL); 878 gpio_request(GPIO_FN_SDHI1D2, NULL); 879 gpio_request(GPIO_FN_SDHI1D1, NULL); 880 gpio_request(GPIO_FN_SDHI1D0, NULL); 881 gpio_request(GPIO_FN_SDHI1CMD, NULL); 882 gpio_request(GPIO_FN_SDHI1CLK, NULL); 883 884 /* enable IrDA */ 885 gpio_request(GPIO_FN_IRDA_OUT, NULL); 886 gpio_request(GPIO_FN_IRDA_IN, NULL); 887 888 /* 889 * enable SH-Eth 890 * 891 * please remove J33 pin from your board !! 892 * 893 * ms7724 board should not use GPIO_FN_LNKSTA pin 894 * So, This time PTX5 is set to input pin 895 */ 896 gpio_request(GPIO_FN_RMII_RXD0, NULL); 897 gpio_request(GPIO_FN_RMII_RXD1, NULL); 898 gpio_request(GPIO_FN_RMII_TXD0, NULL); 899 gpio_request(GPIO_FN_RMII_TXD1, NULL); 900 gpio_request(GPIO_FN_RMII_REF_CLK, NULL); 901 gpio_request(GPIO_FN_RMII_TX_EN, NULL); 902 gpio_request(GPIO_FN_RMII_RX_ER, NULL); 903 gpio_request(GPIO_FN_RMII_CRS_DV, NULL); 904 gpio_request(GPIO_FN_MDIO, NULL); 905 gpio_request(GPIO_FN_MDC, NULL); 906 gpio_request(GPIO_PTX5, NULL); 907 gpio_direction_input(GPIO_PTX5); 908 sh_eth_init(); 909 910 if (sw & SW41_B) { 911 /* 720p */ 912 lcdc_info.ch[0].lcd_cfg = lcdc_720p_modes; 913 lcdc_info.ch[0].num_cfg = ARRAY_SIZE(lcdc_720p_modes); 914 } else { 915 /* VGA */ 916 lcdc_info.ch[0].lcd_cfg = lcdc_vga_modes; 917 lcdc_info.ch[0].num_cfg = ARRAY_SIZE(lcdc_vga_modes); 918 } 919 920 if (sw & SW41_A) { 921 /* Digital monitor */ 922 lcdc_info.ch[0].interface_type = RGB18; 923 lcdc_info.ch[0].flags = 0; 924 } else { 925 /* Analog monitor */ 926 lcdc_info.ch[0].interface_type = RGB24; 927 lcdc_info.ch[0].flags = LCDC_FLAGS_DWPOL; 928 } 929 930 /* VOU */ 931 gpio_request(GPIO_FN_DV_D15, NULL); 932 gpio_request(GPIO_FN_DV_D14, NULL); 933 gpio_request(GPIO_FN_DV_D13, NULL); 934 gpio_request(GPIO_FN_DV_D12, NULL); 935 gpio_request(GPIO_FN_DV_D11, NULL); 936 gpio_request(GPIO_FN_DV_D10, NULL); 937 gpio_request(GPIO_FN_DV_D9, NULL); 938 gpio_request(GPIO_FN_DV_D8, NULL); 939 gpio_request(GPIO_FN_DV_CLKI, NULL); 940 gpio_request(GPIO_FN_DV_CLK, NULL); 941 gpio_request(GPIO_FN_DV_VSYNC, NULL); 942 gpio_request(GPIO_FN_DV_HSYNC, NULL); 943 944 return platform_add_devices(ms7724se_devices, 945 ARRAY_SIZE(ms7724se_devices)); 946 } 947 device_initcall(devices_setup); 948 949 static struct sh_machine_vector mv_ms7724se __initmv = { 950 .mv_name = "ms7724se", 951 .mv_init_irq = init_se7724_IRQ, 952 .mv_nr_irqs = SE7724_FPGA_IRQ_BASE + SE7724_FPGA_IRQ_NR, 953 }; 954