1 /* 2 * linux/arch/sh/boards/se/7724/irq.c 3 * 4 * Copyright (C) 2009 Renesas Solutions Corp. 5 * 6 * Kuninori Morimoto <morimoto.kuninori@renesas.com> 7 * 8 * Based on linux/arch/sh/boards/se/7722/irq.c 9 * Copyright (C) 2007 Nobuhiro Iwamatsu 10 * 11 * Hitachi UL SolutionEngine 7724 Support. 12 * 13 * This file is subject to the terms and conditions of the GNU General Public 14 * License. See the file "COPYING" in the main directory of this archive 15 * for more details. 16 */ 17 #include <linux/init.h> 18 #include <linux/irq.h> 19 #include <linux/interrupt.h> 20 #include <asm/irq.h> 21 #include <asm/io.h> 22 #include <mach-se/mach/se7724.h> 23 24 struct fpga_irq { 25 unsigned long sraddr; 26 unsigned long mraddr; 27 unsigned short mask; 28 unsigned int base; 29 }; 30 31 static unsigned int fpga2irq(unsigned int irq) 32 { 33 if (irq >= IRQ0_BASE && 34 irq <= IRQ0_END) 35 return IRQ0_IRQ; 36 else if (irq >= IRQ1_BASE && 37 irq <= IRQ1_END) 38 return IRQ1_IRQ; 39 else 40 return IRQ2_IRQ; 41 } 42 43 static struct fpga_irq get_fpga_irq(unsigned int irq) 44 { 45 struct fpga_irq set; 46 47 switch (irq) { 48 case IRQ0_IRQ: 49 set.sraddr = IRQ0_SR; 50 set.mraddr = IRQ0_MR; 51 set.mask = IRQ0_MASK; 52 set.base = IRQ0_BASE; 53 break; 54 case IRQ1_IRQ: 55 set.sraddr = IRQ1_SR; 56 set.mraddr = IRQ1_MR; 57 set.mask = IRQ1_MASK; 58 set.base = IRQ1_BASE; 59 break; 60 default: 61 set.sraddr = IRQ2_SR; 62 set.mraddr = IRQ2_MR; 63 set.mask = IRQ2_MASK; 64 set.base = IRQ2_BASE; 65 break; 66 } 67 68 return set; 69 } 70 71 static void disable_se7724_irq(unsigned int irq) 72 { 73 struct fpga_irq set = get_fpga_irq(fpga2irq(irq)); 74 unsigned int bit = irq - set.base; 75 ctrl_outw(ctrl_inw(set.mraddr) | 0x0001 << bit, set.mraddr); 76 } 77 78 static void enable_se7724_irq(unsigned int irq) 79 { 80 struct fpga_irq set = get_fpga_irq(fpga2irq(irq)); 81 unsigned int bit = irq - set.base; 82 ctrl_outw(ctrl_inw(set.mraddr) & ~(0x0001 << bit), set.mraddr); 83 } 84 85 static struct irq_chip se7724_irq_chip __read_mostly = { 86 .name = "SE7724-FPGA", 87 .mask = disable_se7724_irq, 88 .unmask = enable_se7724_irq, 89 .mask_ack = disable_se7724_irq, 90 }; 91 92 static void se7724_irq_demux(unsigned int irq, struct irq_desc *desc) 93 { 94 struct fpga_irq set = get_fpga_irq(irq); 95 unsigned short intv = ctrl_inw(set.sraddr); 96 struct irq_desc *ext_desc; 97 unsigned int ext_irq = set.base; 98 99 intv &= set.mask; 100 101 while (intv) { 102 if (intv & 0x0001) { 103 ext_desc = irq_desc + ext_irq; 104 handle_level_irq(ext_irq, ext_desc); 105 } 106 intv >>= 1; 107 ext_irq++; 108 } 109 } 110 111 /* 112 * Initialize IRQ setting 113 */ 114 void __init init_se7724_IRQ(void) 115 { 116 int i; 117 118 ctrl_outw(0xffff, IRQ0_MR); /* mask all */ 119 ctrl_outw(0xffff, IRQ1_MR); /* mask all */ 120 ctrl_outw(0xffff, IRQ2_MR); /* mask all */ 121 ctrl_outw(0x0000, IRQ0_SR); /* clear irq */ 122 ctrl_outw(0x0000, IRQ1_SR); /* clear irq */ 123 ctrl_outw(0x0000, IRQ2_SR); /* clear irq */ 124 ctrl_outw(0x002a, IRQ_MODE); /* set irq type */ 125 126 for (i = 0; i < SE7724_FPGA_IRQ_NR; i++) 127 set_irq_chip_and_handler_name(SE7724_FPGA_IRQ_BASE + i, 128 &se7724_irq_chip, 129 handle_level_irq, "level"); 130 131 set_irq_chained_handler(IRQ0_IRQ, se7724_irq_demux); 132 set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW); 133 134 set_irq_chained_handler(IRQ1_IRQ, se7724_irq_demux); 135 set_irq_type(IRQ1_IRQ, IRQ_TYPE_LEVEL_LOW); 136 137 set_irq_chained_handler(IRQ2_IRQ, se7724_irq_demux); 138 set_irq_type(IRQ2_IRQ, IRQ_TYPE_LEVEL_LOW); 139 } 140