1 /* 2 * linux/arch/sh/boards/se/770x/setup.c 3 * 4 * Copyright (C) 2000 Kazumoto Kojima 5 * 6 * Hitachi SolutionEngine Support. 7 * 8 */ 9 #include <linux/init.h> 10 #include <linux/platform_device.h> 11 #include <mach-se/mach/se.h> 12 #include <mach-se/mach/mrshpc.h> 13 #include <asm/machvec.h> 14 #include <asm/io.h> 15 #include <asm/smc37c93x.h> 16 #include <asm/heartbeat.h> 17 18 /* 19 * Configure the Super I/O chip 20 */ 21 static void __init smsc_config(int index, int data) 22 { 23 outb_p(index, INDEX_PORT); 24 outb_p(data, DATA_PORT); 25 } 26 27 /* XXX: Another candidate for a more generic cchip machine vector */ 28 static void __init smsc_setup(char **cmdline_p) 29 { 30 outb_p(CONFIG_ENTER, CONFIG_PORT); 31 outb_p(CONFIG_ENTER, CONFIG_PORT); 32 33 /* FDC */ 34 smsc_config(CURRENT_LDN_INDEX, LDN_FDC); 35 smsc_config(ACTIVATE_INDEX, 0x01); 36 smsc_config(IRQ_SELECT_INDEX, 6); /* IRQ6 */ 37 38 /* AUXIO (GPIO): to use IDE1 */ 39 smsc_config(CURRENT_LDN_INDEX, LDN_AUXIO); 40 smsc_config(GPIO46_INDEX, 0x00); /* nIOROP */ 41 smsc_config(GPIO47_INDEX, 0x00); /* nIOWOP */ 42 43 /* COM1 */ 44 smsc_config(CURRENT_LDN_INDEX, LDN_COM1); 45 smsc_config(ACTIVATE_INDEX, 0x01); 46 smsc_config(IO_BASE_HI_INDEX, 0x03); 47 smsc_config(IO_BASE_LO_INDEX, 0xf8); 48 smsc_config(IRQ_SELECT_INDEX, 4); /* IRQ4 */ 49 50 /* COM2 */ 51 smsc_config(CURRENT_LDN_INDEX, LDN_COM2); 52 smsc_config(ACTIVATE_INDEX, 0x01); 53 smsc_config(IO_BASE_HI_INDEX, 0x02); 54 smsc_config(IO_BASE_LO_INDEX, 0xf8); 55 smsc_config(IRQ_SELECT_INDEX, 3); /* IRQ3 */ 56 57 /* RTC */ 58 smsc_config(CURRENT_LDN_INDEX, LDN_RTC); 59 smsc_config(ACTIVATE_INDEX, 0x01); 60 smsc_config(IRQ_SELECT_INDEX, 8); /* IRQ8 */ 61 62 /* XXX: PARPORT, KBD, and MOUSE will come here... */ 63 outb_p(CONFIG_EXIT, CONFIG_PORT); 64 } 65 66 67 static struct resource cf_ide_resources[] = { 68 [0] = { 69 .start = PA_MRSHPC_IO + 0x1f0, 70 .end = PA_MRSHPC_IO + 0x1f0 + 8, 71 .flags = IORESOURCE_MEM, 72 }, 73 [1] = { 74 .start = PA_MRSHPC_IO + 0x1f0 + 0x206, 75 .end = PA_MRSHPC_IO + 0x1f0 + 8 + 0x206 + 8, 76 .flags = IORESOURCE_MEM, 77 }, 78 [2] = { 79 .start = IRQ_CFCARD, 80 .flags = IORESOURCE_IRQ, 81 }, 82 }; 83 84 static struct platform_device cf_ide_device = { 85 .name = "pata_platform", 86 .id = -1, 87 .num_resources = ARRAY_SIZE(cf_ide_resources), 88 .resource = cf_ide_resources, 89 }; 90 91 static unsigned char heartbeat_bit_pos[] = { 8, 9, 10, 11, 12, 13, 14, 15 }; 92 93 static struct heartbeat_data heartbeat_data = { 94 .bit_pos = heartbeat_bit_pos, 95 .nr_bits = ARRAY_SIZE(heartbeat_bit_pos), 96 .regsize = 16, 97 }; 98 99 static struct resource heartbeat_resources[] = { 100 [0] = { 101 .start = PA_LED, 102 .end = PA_LED, 103 .flags = IORESOURCE_MEM, 104 }, 105 }; 106 107 static struct platform_device heartbeat_device = { 108 .name = "heartbeat", 109 .id = -1, 110 .dev = { 111 .platform_data = &heartbeat_data, 112 }, 113 .num_resources = ARRAY_SIZE(heartbeat_resources), 114 .resource = heartbeat_resources, 115 }; 116 117 #if defined(CONFIG_CPU_SUBTYPE_SH7710) ||\ 118 defined(CONFIG_CPU_SUBTYPE_SH7712) 119 /* SH771X Ethernet driver */ 120 static struct resource sh_eth0_resources[] = { 121 [0] = { 122 .start = SH_ETH0_BASE, 123 .end = SH_ETH0_BASE + 0x1B8, 124 .flags = IORESOURCE_MEM, 125 }, 126 [1] = { 127 .start = SH_ETH0_IRQ, 128 .end = SH_ETH0_IRQ, 129 .flags = IORESOURCE_IRQ, 130 }, 131 }; 132 133 static struct platform_device sh_eth0_device = { 134 .name = "sh-eth", 135 .id = 0, 136 .dev = { 137 .platform_data = PHY_ID, 138 }, 139 .num_resources = ARRAY_SIZE(sh_eth0_resources), 140 .resource = sh_eth0_resources, 141 }; 142 143 static struct resource sh_eth1_resources[] = { 144 [0] = { 145 .start = SH_ETH1_BASE, 146 .end = SH_ETH1_BASE + 0x1B8, 147 .flags = IORESOURCE_MEM, 148 }, 149 [1] = { 150 .start = SH_ETH1_IRQ, 151 .end = SH_ETH1_IRQ, 152 .flags = IORESOURCE_IRQ, 153 }, 154 }; 155 156 static struct platform_device sh_eth1_device = { 157 .name = "sh-eth", 158 .id = 1, 159 .dev = { 160 .platform_data = PHY_ID, 161 }, 162 .num_resources = ARRAY_SIZE(sh_eth1_resources), 163 .resource = sh_eth1_resources, 164 }; 165 #endif 166 167 static struct platform_device *se_devices[] __initdata = { 168 &heartbeat_device, 169 &cf_ide_device, 170 #if defined(CONFIG_CPU_SUBTYPE_SH7710) ||\ 171 defined(CONFIG_CPU_SUBTYPE_SH7712) 172 &sh_eth0_device, 173 &sh_eth1_device, 174 #endif 175 }; 176 177 static int __init se_devices_setup(void) 178 { 179 mrshpc_setup_windows(); 180 return platform_add_devices(se_devices, ARRAY_SIZE(se_devices)); 181 } 182 device_initcall(se_devices_setup); 183 184 /* 185 * The Machine Vector 186 */ 187 static struct sh_machine_vector mv_se __initmv = { 188 .mv_name = "SolutionEngine", 189 .mv_setup = smsc_setup, 190 #if defined(CONFIG_CPU_SH4) 191 .mv_nr_irqs = 48, 192 #elif defined(CONFIG_CPU_SUBTYPE_SH7708) 193 .mv_nr_irqs = 32, 194 #elif defined(CONFIG_CPU_SUBTYPE_SH7709) 195 .mv_nr_irqs = 61, 196 #elif defined(CONFIG_CPU_SUBTYPE_SH7705) 197 .mv_nr_irqs = 86, 198 #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) 199 .mv_nr_irqs = 104, 200 #endif 201 202 .mv_inb = se_inb, 203 .mv_inw = se_inw, 204 .mv_inl = se_inl, 205 .mv_outb = se_outb, 206 .mv_outw = se_outw, 207 .mv_outl = se_outl, 208 209 .mv_inb_p = se_inb_p, 210 .mv_inw_p = se_inw, 211 .mv_inl_p = se_inl, 212 .mv_outb_p = se_outb_p, 213 .mv_outw_p = se_outw, 214 .mv_outl_p = se_outl, 215 216 .mv_insb = se_insb, 217 .mv_insw = se_insw, 218 .mv_insl = se_insl, 219 .mv_outsb = se_outsb, 220 .mv_outsw = se_outsw, 221 .mv_outsl = se_outsl, 222 223 .mv_init_irq = init_se_IRQ, 224 }; 225