1 /* 2 * linux/arch/sh/boards/se/770x/setup.c 3 * 4 * Copyright (C) 2000 Kazumoto Kojima 5 * 6 * Hitachi SolutionEngine Support. 7 * 8 */ 9 #include <linux/init.h> 10 #include <linux/platform_device.h> 11 #include <asm/machvec.h> 12 #include <mach-se/mach/se.h> 13 #include <asm/io.h> 14 #include <asm/smc37c93x.h> 15 #include <asm/heartbeat.h> 16 17 /* 18 * Configure the Super I/O chip 19 */ 20 static void __init smsc_config(int index, int data) 21 { 22 outb_p(index, INDEX_PORT); 23 outb_p(data, DATA_PORT); 24 } 25 26 /* XXX: Another candidate for a more generic cchip machine vector */ 27 static void __init smsc_setup(char **cmdline_p) 28 { 29 outb_p(CONFIG_ENTER, CONFIG_PORT); 30 outb_p(CONFIG_ENTER, CONFIG_PORT); 31 32 /* FDC */ 33 smsc_config(CURRENT_LDN_INDEX, LDN_FDC); 34 smsc_config(ACTIVATE_INDEX, 0x01); 35 smsc_config(IRQ_SELECT_INDEX, 6); /* IRQ6 */ 36 37 /* AUXIO (GPIO): to use IDE1 */ 38 smsc_config(CURRENT_LDN_INDEX, LDN_AUXIO); 39 smsc_config(GPIO46_INDEX, 0x00); /* nIOROP */ 40 smsc_config(GPIO47_INDEX, 0x00); /* nIOWOP */ 41 42 /* COM1 */ 43 smsc_config(CURRENT_LDN_INDEX, LDN_COM1); 44 smsc_config(ACTIVATE_INDEX, 0x01); 45 smsc_config(IO_BASE_HI_INDEX, 0x03); 46 smsc_config(IO_BASE_LO_INDEX, 0xf8); 47 smsc_config(IRQ_SELECT_INDEX, 4); /* IRQ4 */ 48 49 /* COM2 */ 50 smsc_config(CURRENT_LDN_INDEX, LDN_COM2); 51 smsc_config(ACTIVATE_INDEX, 0x01); 52 smsc_config(IO_BASE_HI_INDEX, 0x02); 53 smsc_config(IO_BASE_LO_INDEX, 0xf8); 54 smsc_config(IRQ_SELECT_INDEX, 3); /* IRQ3 */ 55 56 /* RTC */ 57 smsc_config(CURRENT_LDN_INDEX, LDN_RTC); 58 smsc_config(ACTIVATE_INDEX, 0x01); 59 smsc_config(IRQ_SELECT_INDEX, 8); /* IRQ8 */ 60 61 /* XXX: PARPORT, KBD, and MOUSE will come here... */ 62 outb_p(CONFIG_EXIT, CONFIG_PORT); 63 } 64 65 66 static struct resource cf_ide_resources[] = { 67 [0] = { 68 .start = PA_MRSHPC_IO + 0x1f0, 69 .end = PA_MRSHPC_IO + 0x1f0 + 8, 70 .flags = IORESOURCE_MEM, 71 }, 72 [1] = { 73 .start = PA_MRSHPC_IO + 0x1f0 + 0x206, 74 .end = PA_MRSHPC_IO + 0x1f0 + 8 + 0x206 + 8, 75 .flags = IORESOURCE_MEM, 76 }, 77 [2] = { 78 .start = IRQ_CFCARD, 79 .flags = IORESOURCE_IRQ, 80 }, 81 }; 82 83 static struct platform_device cf_ide_device = { 84 .name = "pata_platform", 85 .id = -1, 86 .num_resources = ARRAY_SIZE(cf_ide_resources), 87 .resource = cf_ide_resources, 88 }; 89 90 static unsigned char heartbeat_bit_pos[] = { 8, 9, 10, 11, 12, 13, 14, 15 }; 91 92 static struct heartbeat_data heartbeat_data = { 93 .bit_pos = heartbeat_bit_pos, 94 .nr_bits = ARRAY_SIZE(heartbeat_bit_pos), 95 .regsize = 16, 96 }; 97 98 static struct resource heartbeat_resources[] = { 99 [0] = { 100 .start = PA_LED, 101 .end = PA_LED, 102 .flags = IORESOURCE_MEM, 103 }, 104 }; 105 106 static struct platform_device heartbeat_device = { 107 .name = "heartbeat", 108 .id = -1, 109 .dev = { 110 .platform_data = &heartbeat_data, 111 }, 112 .num_resources = ARRAY_SIZE(heartbeat_resources), 113 .resource = heartbeat_resources, 114 }; 115 116 #if defined(CONFIG_CPU_SUBTYPE_SH7710) ||\ 117 defined(CONFIG_CPU_SUBTYPE_SH7712) 118 /* SH771X Ethernet driver */ 119 static struct resource sh_eth0_resources[] = { 120 [0] = { 121 .start = SH_ETH0_BASE, 122 .end = SH_ETH0_BASE + 0x1B8, 123 .flags = IORESOURCE_MEM, 124 }, 125 [1] = { 126 .start = SH_ETH0_IRQ, 127 .end = SH_ETH0_IRQ, 128 .flags = IORESOURCE_IRQ, 129 }, 130 }; 131 132 static struct platform_device sh_eth0_device = { 133 .name = "sh-eth", 134 .id = 0, 135 .dev = { 136 .platform_data = PHY_ID, 137 }, 138 .num_resources = ARRAY_SIZE(sh_eth0_resources), 139 .resource = sh_eth0_resources, 140 }; 141 142 static struct resource sh_eth1_resources[] = { 143 [0] = { 144 .start = SH_ETH1_BASE, 145 .end = SH_ETH1_BASE + 0x1B8, 146 .flags = IORESOURCE_MEM, 147 }, 148 [1] = { 149 .start = SH_ETH1_IRQ, 150 .end = SH_ETH1_IRQ, 151 .flags = IORESOURCE_IRQ, 152 }, 153 }; 154 155 static struct platform_device sh_eth1_device = { 156 .name = "sh-eth", 157 .id = 1, 158 .dev = { 159 .platform_data = PHY_ID, 160 }, 161 .num_resources = ARRAY_SIZE(sh_eth1_resources), 162 .resource = sh_eth1_resources, 163 }; 164 #endif 165 166 static struct platform_device *se_devices[] __initdata = { 167 &heartbeat_device, 168 &cf_ide_device, 169 #if defined(CONFIG_CPU_SUBTYPE_SH7710) ||\ 170 defined(CONFIG_CPU_SUBTYPE_SH7712) 171 &sh_eth0_device, 172 &sh_eth1_device, 173 #endif 174 }; 175 176 static int __init se_devices_setup(void) 177 { 178 return platform_add_devices(se_devices, ARRAY_SIZE(se_devices)); 179 } 180 device_initcall(se_devices_setup); 181 182 /* 183 * The Machine Vector 184 */ 185 static struct sh_machine_vector mv_se __initmv = { 186 .mv_name = "SolutionEngine", 187 .mv_setup = smsc_setup, 188 #if defined(CONFIG_CPU_SH4) 189 .mv_nr_irqs = 48, 190 #elif defined(CONFIG_CPU_SUBTYPE_SH7708) 191 .mv_nr_irqs = 32, 192 #elif defined(CONFIG_CPU_SUBTYPE_SH7709) 193 .mv_nr_irqs = 61, 194 #elif defined(CONFIG_CPU_SUBTYPE_SH7705) 195 .mv_nr_irqs = 86, 196 #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) 197 .mv_nr_irqs = 104, 198 #endif 199 200 .mv_inb = se_inb, 201 .mv_inw = se_inw, 202 .mv_inl = se_inl, 203 .mv_outb = se_outb, 204 .mv_outw = se_outw, 205 .mv_outl = se_outl, 206 207 .mv_inb_p = se_inb_p, 208 .mv_inw_p = se_inw, 209 .mv_inl_p = se_inl, 210 .mv_outb_p = se_outb_p, 211 .mv_outw_p = se_outw, 212 .mv_outl_p = se_outl, 213 214 .mv_insb = se_insb, 215 .mv_insw = se_insw, 216 .mv_insl = se_insl, 217 .mv_outsb = se_outsb, 218 .mv_outsw = se_outsw, 219 .mv_outsl = se_outsl, 220 221 .mv_init_irq = init_se_IRQ, 222 }; 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