1b2441318SGreg Kroah-Hartman // SPDX-License-Identifier: GPL-2.0
2da2014a2SPaul Mundt /*
3da2014a2SPaul Mundt * linux/arch/sh/boards/se/7206/irq.c
4da2014a2SPaul Mundt *
5da2014a2SPaul Mundt * Copyright (C) 2005,2006 Yoshinori Sato
6da2014a2SPaul Mundt *
7da2014a2SPaul Mundt * Hitachi SolutionEngine Support.
8da2014a2SPaul Mundt *
9da2014a2SPaul Mundt */
10da2014a2SPaul Mundt #include <linux/init.h>
11da2014a2SPaul Mundt #include <linux/irq.h>
12da2014a2SPaul Mundt #include <linux/io.h>
13da2014a2SPaul Mundt #include <linux/interrupt.h>
14939a24a6SPaul Mundt #include <mach-se/mach/se7206.h>
15da2014a2SPaul Mundt
16da2014a2SPaul Mundt #define INTSTS0 0x31800000
17da2014a2SPaul Mundt #define INTSTS1 0x31800002
18da2014a2SPaul Mundt #define INTMSK0 0x31800004
19da2014a2SPaul Mundt #define INTMSK1 0x31800006
20da2014a2SPaul Mundt #define INTSEL 0x31800008
21da2014a2SPaul Mundt
22da2014a2SPaul Mundt #define IRQ0_IRQ 64
23da2014a2SPaul Mundt #define IRQ1_IRQ 65
24da2014a2SPaul Mundt #define IRQ3_IRQ 67
25da2014a2SPaul Mundt
26da2014a2SPaul Mundt #define INTC_IPR01 0xfffe0818
27da2014a2SPaul Mundt #define INTC_ICR1 0xfffe0802
28da2014a2SPaul Mundt
disable_se7206_irq(struct irq_data * data)2915ff2c67SPaul Mundt static void disable_se7206_irq(struct irq_data *data)
30da2014a2SPaul Mundt {
3115ff2c67SPaul Mundt unsigned int irq = data->irq;
32da2014a2SPaul Mundt unsigned short val;
33da2014a2SPaul Mundt unsigned short mask = 0xffff ^ (0x0f << 4 * (3 - (IRQ0_IRQ - irq)));
34da2014a2SPaul Mundt unsigned short msk0,msk1;
35da2014a2SPaul Mundt
36da2014a2SPaul Mundt /* Set the priority in IPR to 0 */
379d56dd3bSPaul Mundt val = __raw_readw(INTC_IPR01);
38da2014a2SPaul Mundt val &= mask;
399d56dd3bSPaul Mundt __raw_writew(val, INTC_IPR01);
40da2014a2SPaul Mundt /* FPGA mask set */
419d56dd3bSPaul Mundt msk0 = __raw_readw(INTMSK0);
429d56dd3bSPaul Mundt msk1 = __raw_readw(INTMSK1);
43da2014a2SPaul Mundt
44da2014a2SPaul Mundt switch (irq) {
45da2014a2SPaul Mundt case IRQ0_IRQ:
46da2014a2SPaul Mundt msk0 |= 0x0010;
47da2014a2SPaul Mundt break;
48da2014a2SPaul Mundt case IRQ1_IRQ:
49da2014a2SPaul Mundt msk0 |= 0x000f;
50da2014a2SPaul Mundt break;
51da2014a2SPaul Mundt case IRQ3_IRQ:
52da2014a2SPaul Mundt msk0 |= 0x0f00;
53da2014a2SPaul Mundt msk1 |= 0x00ff;
54da2014a2SPaul Mundt break;
55da2014a2SPaul Mundt }
569d56dd3bSPaul Mundt __raw_writew(msk0, INTMSK0);
579d56dd3bSPaul Mundt __raw_writew(msk1, INTMSK1);
58da2014a2SPaul Mundt }
59da2014a2SPaul Mundt
enable_se7206_irq(struct irq_data * data)6015ff2c67SPaul Mundt static void enable_se7206_irq(struct irq_data *data)
61da2014a2SPaul Mundt {
6215ff2c67SPaul Mundt unsigned int irq = data->irq;
63da2014a2SPaul Mundt unsigned short val;
64da2014a2SPaul Mundt unsigned short value = (0x0001 << 4 * (3 - (IRQ0_IRQ - irq)));
65da2014a2SPaul Mundt unsigned short msk0,msk1;
66da2014a2SPaul Mundt
67da2014a2SPaul Mundt /* Set priority in IPR back to original value */
689d56dd3bSPaul Mundt val = __raw_readw(INTC_IPR01);
69da2014a2SPaul Mundt val |= value;
709d56dd3bSPaul Mundt __raw_writew(val, INTC_IPR01);
71da2014a2SPaul Mundt
72da2014a2SPaul Mundt /* FPGA mask reset */
739d56dd3bSPaul Mundt msk0 = __raw_readw(INTMSK0);
749d56dd3bSPaul Mundt msk1 = __raw_readw(INTMSK1);
75da2014a2SPaul Mundt
76da2014a2SPaul Mundt switch (irq) {
77da2014a2SPaul Mundt case IRQ0_IRQ:
78da2014a2SPaul Mundt msk0 &= ~0x0010;
79da2014a2SPaul Mundt break;
80da2014a2SPaul Mundt case IRQ1_IRQ:
81da2014a2SPaul Mundt msk0 &= ~0x000f;
82da2014a2SPaul Mundt break;
83da2014a2SPaul Mundt case IRQ3_IRQ:
84da2014a2SPaul Mundt msk0 &= ~0x0f00;
85da2014a2SPaul Mundt msk1 &= ~0x00ff;
86da2014a2SPaul Mundt break;
87da2014a2SPaul Mundt }
889d56dd3bSPaul Mundt __raw_writew(msk0, INTMSK0);
899d56dd3bSPaul Mundt __raw_writew(msk1, INTMSK1);
90da2014a2SPaul Mundt }
91da2014a2SPaul Mundt
eoi_se7206_irq(struct irq_data * data)9215ff2c67SPaul Mundt static void eoi_se7206_irq(struct irq_data *data)
93da2014a2SPaul Mundt {
94da2014a2SPaul Mundt unsigned short sts0,sts1;
9515ff2c67SPaul Mundt unsigned int irq = data->irq;
96da2014a2SPaul Mundt
97a821b279SThomas Gleixner if (!irqd_irq_disabled(data) && !irqd_irq_inprogress(data))
9815ff2c67SPaul Mundt enable_se7206_irq(data);
99da2014a2SPaul Mundt /* FPGA isr clear */
1009d56dd3bSPaul Mundt sts0 = __raw_readw(INTSTS0);
1019d56dd3bSPaul Mundt sts1 = __raw_readw(INTSTS1);
102da2014a2SPaul Mundt
103da2014a2SPaul Mundt switch (irq) {
104da2014a2SPaul Mundt case IRQ0_IRQ:
105da2014a2SPaul Mundt sts0 &= ~0x0010;
106da2014a2SPaul Mundt break;
107da2014a2SPaul Mundt case IRQ1_IRQ:
108da2014a2SPaul Mundt sts0 &= ~0x000f;
109da2014a2SPaul Mundt break;
110da2014a2SPaul Mundt case IRQ3_IRQ:
111da2014a2SPaul Mundt sts0 &= ~0x0f00;
112da2014a2SPaul Mundt sts1 &= ~0x00ff;
113da2014a2SPaul Mundt break;
114da2014a2SPaul Mundt }
1159d56dd3bSPaul Mundt __raw_writew(sts0, INTSTS0);
1169d56dd3bSPaul Mundt __raw_writew(sts1, INTSTS1);
117da2014a2SPaul Mundt }
118da2014a2SPaul Mundt
119da2014a2SPaul Mundt static struct irq_chip se7206_irq_chip __read_mostly = {
120da2014a2SPaul Mundt .name = "SE7206-FPGA",
12115ff2c67SPaul Mundt .irq_mask = disable_se7206_irq,
12215ff2c67SPaul Mundt .irq_unmask = enable_se7206_irq,
12315ff2c67SPaul Mundt .irq_eoi = eoi_se7206_irq,
124da2014a2SPaul Mundt };
125da2014a2SPaul Mundt
make_se7206_irq(unsigned int irq)126da2014a2SPaul Mundt static void make_se7206_irq(unsigned int irq)
127da2014a2SPaul Mundt {
128da2014a2SPaul Mundt disable_irq_nosync(irq);
129fcb8918fSThomas Gleixner irq_set_chip_and_handler_name(irq, &se7206_irq_chip,
130da2014a2SPaul Mundt handle_level_irq, "level");
13115ff2c67SPaul Mundt disable_se7206_irq(irq_get_irq_data(irq));
132da2014a2SPaul Mundt }
133da2014a2SPaul Mundt
134da2014a2SPaul Mundt /*
135da2014a2SPaul Mundt * Initialize IRQ setting
136da2014a2SPaul Mundt */
init_se7206_IRQ(void)137da2014a2SPaul Mundt void __init init_se7206_IRQ(void)
138da2014a2SPaul Mundt {
139da2014a2SPaul Mundt make_se7206_irq(IRQ0_IRQ); /* SMC91C111 */
140da2014a2SPaul Mundt make_se7206_irq(IRQ1_IRQ); /* ATA */
141da2014a2SPaul Mundt make_se7206_irq(IRQ3_IRQ); /* SLOT / PCM */
142e96ce8ebSPaul Mundt
14327434f0aSPaul Mundt __raw_writew(__raw_readw(INTC_ICR1) | 0x000b, INTC_ICR1); /* ICR1 */
144da2014a2SPaul Mundt
145da2014a2SPaul Mundt /* FPGA System register setup*/
1469d56dd3bSPaul Mundt __raw_writew(0x0000,INTSTS0); /* Clear INTSTS0 */
1479d56dd3bSPaul Mundt __raw_writew(0x0000,INTSTS1); /* Clear INTSTS1 */
148e96ce8ebSPaul Mundt
149da2014a2SPaul Mundt /* IRQ0=LAN, IRQ1=ATA, IRQ3=SLT,PCM */
1509d56dd3bSPaul Mundt __raw_writew(0x0001,INTSEL);
151da2014a2SPaul Mundt }
152