xref: /openbmc/linux/arch/sh/boards/mach-migor/setup.c (revision df2634f43f5106947f3735a0b61a6527a4b278cd)
1 /*
2  * Renesas System Solutions Asia Pte. Ltd - Migo-R
3  *
4  * Copyright (C) 2008 Magnus Damm
5  *
6  * This file is subject to the terms and conditions of the GNU General Public
7  * License.  See the file "COPYING" in the main directory of this archive
8  * for more details.
9  */
10 #include <linux/init.h>
11 #include <linux/platform_device.h>
12 #include <linux/interrupt.h>
13 #include <linux/input.h>
14 #include <linux/input/sh_keysc.h>
15 #include <linux/mfd/sh_mobile_sdhi.h>
16 #include <linux/mmc/host.h>
17 #include <linux/mtd/physmap.h>
18 #include <linux/mtd/nand.h>
19 #include <linux/i2c.h>
20 #include <linux/smc91x.h>
21 #include <linux/delay.h>
22 #include <linux/clk.h>
23 #include <linux/gpio.h>
24 #include <video/sh_mobile_lcdc.h>
25 #include <media/sh_mobile_ceu.h>
26 #include <media/ov772x.h>
27 #include <media/tw9910.h>
28 #include <asm/clock.h>
29 #include <asm/machvec.h>
30 #include <asm/io.h>
31 #include <asm/suspend.h>
32 #include <mach/migor.h>
33 #include <cpu/sh7722.h>
34 
35 /* Address     IRQ  Size  Bus  Description
36  * 0x00000000       64MB  16   NOR Flash (SP29PL256N)
37  * 0x0c000000       64MB  64   SDRAM (2xK4M563233G)
38  * 0x10000000  IRQ0       16   Ethernet (SMC91C111)
39  * 0x14000000  IRQ4       16   USB 2.0 Host Controller (M66596)
40  * 0x18000000       8GB    8   NAND Flash (K9K8G08U0A)
41  */
42 
43 static struct smc91x_platdata smc91x_info = {
44 	.flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
45 };
46 
47 static struct resource smc91x_eth_resources[] = {
48 	[0] = {
49 		.name   = "SMC91C111" ,
50 		.start  = 0x10000300,
51 		.end    = 0x1000030f,
52 		.flags  = IORESOURCE_MEM,
53 	},
54 	[1] = {
55 		.start  = 32, /* IRQ0 */
56 		.flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
57 	},
58 };
59 
60 static struct platform_device smc91x_eth_device = {
61 	.name           = "smc91x",
62 	.num_resources  = ARRAY_SIZE(smc91x_eth_resources),
63 	.resource       = smc91x_eth_resources,
64 	.dev	= {
65 		.platform_data	= &smc91x_info,
66 	},
67 };
68 
69 static struct sh_keysc_info sh_keysc_info = {
70 	.mode = SH_KEYSC_MODE_2, /* KEYOUT0->4, KEYIN1->5 */
71 	.scan_timing = 3,
72 	.delay = 5,
73 	.keycodes = {
74 		0, KEY_UP, KEY_DOWN, KEY_LEFT, KEY_RIGHT, KEY_ENTER,
75 		0, KEY_F, KEY_C, KEY_D,	KEY_H, KEY_1,
76 		0, KEY_2, KEY_3, KEY_4,	KEY_5, KEY_6,
77 		0, KEY_7, KEY_8, KEY_9, KEY_S, KEY_0,
78 		0, KEY_P, KEY_STOP, KEY_REWIND, KEY_PLAY, KEY_FASTFORWARD,
79 	},
80 };
81 
82 static struct resource sh_keysc_resources[] = {
83 	[0] = {
84 		.start  = 0x044b0000,
85 		.end    = 0x044b000f,
86 		.flags  = IORESOURCE_MEM,
87 	},
88 	[1] = {
89 		.start  = 79,
90 		.flags  = IORESOURCE_IRQ,
91 	},
92 };
93 
94 static struct platform_device sh_keysc_device = {
95 	.name           = "sh_keysc",
96 	.id             = 0, /* "keysc0" clock */
97 	.num_resources  = ARRAY_SIZE(sh_keysc_resources),
98 	.resource       = sh_keysc_resources,
99 	.dev	= {
100 		.platform_data	= &sh_keysc_info,
101 	},
102 	.archdata = {
103 		.hwblk_id = HWBLK_KEYSC,
104 	},
105 };
106 
107 static struct mtd_partition migor_nor_flash_partitions[] =
108 {
109 	{
110 		.name = "uboot",
111 		.offset = 0,
112 		.size = (1 * 1024 * 1024),
113 		.mask_flags = MTD_WRITEABLE,	/* Read-only */
114 	},
115 	{
116 		.name = "rootfs",
117 		.offset = MTDPART_OFS_APPEND,
118 		.size = (15 * 1024 * 1024),
119 	},
120 	{
121 		.name = "other",
122 		.offset = MTDPART_OFS_APPEND,
123 		.size = MTDPART_SIZ_FULL,
124 	},
125 };
126 
127 static struct physmap_flash_data migor_nor_flash_data = {
128 	.width		= 2,
129 	.parts		= migor_nor_flash_partitions,
130 	.nr_parts	= ARRAY_SIZE(migor_nor_flash_partitions),
131 };
132 
133 static struct resource migor_nor_flash_resources[] = {
134 	[0] = {
135 		.name		= "NOR Flash",
136 		.start		= 0x00000000,
137 		.end		= 0x03ffffff,
138 		.flags		= IORESOURCE_MEM,
139 	}
140 };
141 
142 static struct platform_device migor_nor_flash_device = {
143 	.name		= "physmap-flash",
144 	.resource	= migor_nor_flash_resources,
145 	.num_resources	= ARRAY_SIZE(migor_nor_flash_resources),
146 	.dev		= {
147 		.platform_data = &migor_nor_flash_data,
148 	},
149 };
150 
151 static struct mtd_partition migor_nand_flash_partitions[] = {
152 	{
153 		.name		= "nanddata1",
154 		.offset		= 0x0,
155 		.size		= 512 * 1024 * 1024,
156 	},
157 	{
158 		.name		= "nanddata2",
159 		.offset		= MTDPART_OFS_APPEND,
160 		.size		= 512 * 1024 * 1024,
161 	},
162 };
163 
164 static void migor_nand_flash_cmd_ctl(struct mtd_info *mtd, int cmd,
165 				     unsigned int ctrl)
166 {
167 	struct nand_chip *chip = mtd->priv;
168 
169 	if (cmd == NAND_CMD_NONE)
170 		return;
171 
172 	if (ctrl & NAND_CLE)
173 		writeb(cmd, chip->IO_ADDR_W + 0x00400000);
174 	else if (ctrl & NAND_ALE)
175 		writeb(cmd, chip->IO_ADDR_W + 0x00800000);
176 	else
177 		writeb(cmd, chip->IO_ADDR_W);
178 }
179 
180 static int migor_nand_flash_ready(struct mtd_info *mtd)
181 {
182 	return gpio_get_value(GPIO_PTA1); /* NAND_RBn */
183 }
184 
185 static struct platform_nand_data migor_nand_flash_data = {
186 	.chip = {
187 		.nr_chips = 1,
188 		.partitions = migor_nand_flash_partitions,
189 		.nr_partitions = ARRAY_SIZE(migor_nand_flash_partitions),
190 		.chip_delay = 20,
191 		.part_probe_types = (const char *[]) { "cmdlinepart", NULL },
192 	},
193 	.ctrl = {
194 		.dev_ready = migor_nand_flash_ready,
195 		.cmd_ctrl = migor_nand_flash_cmd_ctl,
196 	},
197 };
198 
199 static struct resource migor_nand_flash_resources[] = {
200 	[0] = {
201 		.name		= "NAND Flash",
202 		.start		= 0x18000000,
203 		.end		= 0x18ffffff,
204 		.flags		= IORESOURCE_MEM,
205 	},
206 };
207 
208 static struct platform_device migor_nand_flash_device = {
209 	.name		= "gen_nand",
210 	.resource	= migor_nand_flash_resources,
211 	.num_resources	= ARRAY_SIZE(migor_nand_flash_resources),
212 	.dev		= {
213 		.platform_data = &migor_nand_flash_data,
214 	}
215 };
216 
217 const static struct fb_videomode migor_lcd_modes[] = {
218 	{
219 #if defined(CONFIG_SH_MIGOR_RTA_WVGA)
220 		.name = "LB070WV1",
221 		.xres = 800,
222 		.yres = 480,
223 		.left_margin = 64,
224 		.right_margin = 16,
225 		.hsync_len = 120,
226 		.sync = 0,
227 #elif defined(CONFIG_SH_MIGOR_QVGA)
228 		.name = "PH240320T",
229 		.xres = 320,
230 		.yres = 240,
231 		.left_margin = 0,
232 		.right_margin = 16,
233 		.hsync_len = 8,
234 		.sync = FB_SYNC_HOR_HIGH_ACT,
235 #endif
236 		.upper_margin = 1,
237 		.lower_margin = 17,
238 		.vsync_len = 2,
239 	},
240 };
241 
242 static struct sh_mobile_lcdc_info sh_mobile_lcdc_info = {
243 #if defined(CONFIG_SH_MIGOR_RTA_WVGA)
244 	.clock_source = LCDC_CLK_BUS,
245 	.ch[0] = {
246 		.chan = LCDC_CHAN_MAINLCD,
247 		.bpp = 16,
248 		.interface_type = RGB16,
249 		.clock_divider = 2,
250 		.lcd_cfg = migor_lcd_modes,
251 		.num_cfg = ARRAY_SIZE(migor_lcd_modes),
252 		.lcd_size_cfg = { /* 7.0 inch */
253 			.width = 152,
254 			.height = 91,
255 		},
256 	}
257 #elif defined(CONFIG_SH_MIGOR_QVGA)
258 	.clock_source = LCDC_CLK_PERIPHERAL,
259 	.ch[0] = {
260 		.chan = LCDC_CHAN_MAINLCD,
261 		.bpp = 16,
262 		.interface_type = SYS16A,
263 		.clock_divider = 10,
264 		.lcd_cfg = migor_lcd_modes,
265 		.num_cfg = ARRAY_SIZE(migor_lcd_modes),
266 		.lcd_size_cfg = { /* 2.4 inch */
267 			.width = 49,
268 			.height = 37,
269 		},
270 		.board_cfg = {
271 			.setup_sys = migor_lcd_qvga_setup,
272 		},
273 		.sys_bus_cfg = {
274 			.ldmt2r = 0x06000a09,
275 			.ldmt3r = 0x180e3418,
276 			/* set 1s delay to encourage fsync() */
277 			.deferred_io_msec = 1000,
278 		},
279 	}
280 #endif
281 };
282 
283 static struct resource migor_lcdc_resources[] = {
284 	[0] = {
285 		.name	= "LCDC",
286 		.start	= 0xfe940000, /* P4-only space */
287 		.end	= 0xfe942fff,
288 		.flags	= IORESOURCE_MEM,
289 	},
290 	[1] = {
291 		.start	= 28,
292 		.flags	= IORESOURCE_IRQ,
293 	},
294 };
295 
296 static struct platform_device migor_lcdc_device = {
297 	.name		= "sh_mobile_lcdc_fb",
298 	.num_resources	= ARRAY_SIZE(migor_lcdc_resources),
299 	.resource	= migor_lcdc_resources,
300 	.dev	= {
301 		.platform_data	= &sh_mobile_lcdc_info,
302 	},
303 	.archdata = {
304 		.hwblk_id = HWBLK_LCDC,
305 	},
306 };
307 
308 static struct clk *camera_clk;
309 static DEFINE_MUTEX(camera_lock);
310 
311 static void camera_power_on(int is_tw)
312 {
313 	mutex_lock(&camera_lock);
314 
315 	/* Use 10 MHz VIO_CKO instead of 24 MHz to work
316 	 * around signal quality issues on Panel Board V2.1.
317 	 */
318 	camera_clk = clk_get(NULL, "video_clk");
319 	clk_set_rate(camera_clk, 10000000);
320 	clk_enable(camera_clk);	/* start VIO_CKO */
321 
322 	/* use VIO_RST to take camera out of reset */
323 	mdelay(10);
324 	if (is_tw) {
325 		gpio_set_value(GPIO_PTT2, 0);
326 		gpio_set_value(GPIO_PTT0, 0);
327 	} else {
328 		gpio_set_value(GPIO_PTT0, 1);
329 	}
330 	gpio_set_value(GPIO_PTT3, 0);
331 	mdelay(10);
332 	gpio_set_value(GPIO_PTT3, 1);
333 	mdelay(10); /* wait to let chip come out of reset */
334 }
335 
336 static void camera_power_off(void)
337 {
338 	clk_disable(camera_clk); /* stop VIO_CKO */
339 	clk_put(camera_clk);
340 
341 	gpio_set_value(GPIO_PTT3, 0);
342 	mutex_unlock(&camera_lock);
343 }
344 
345 static int ov7725_power(struct device *dev, int mode)
346 {
347 	if (mode)
348 		camera_power_on(0);
349 	else
350 		camera_power_off();
351 
352 	return 0;
353 }
354 
355 static int tw9910_power(struct device *dev, int mode)
356 {
357 	if (mode)
358 		camera_power_on(1);
359 	else
360 		camera_power_off();
361 
362 	return 0;
363 }
364 
365 static struct sh_mobile_ceu_info sh_mobile_ceu_info = {
366 	.flags = SH_CEU_FLAG_USE_8BIT_BUS,
367 };
368 
369 static struct resource migor_ceu_resources[] = {
370 	[0] = {
371 		.name	= "CEU",
372 		.start	= 0xfe910000,
373 		.end	= 0xfe91009f,
374 		.flags	= IORESOURCE_MEM,
375 	},
376 	[1] = {
377 		.start  = 52,
378 		.flags  = IORESOURCE_IRQ,
379 	},
380 	[2] = {
381 		/* place holder for contiguous memory */
382 	},
383 };
384 
385 static struct platform_device migor_ceu_device = {
386 	.name		= "sh_mobile_ceu",
387 	.id             = 0, /* "ceu0" clock */
388 	.num_resources	= ARRAY_SIZE(migor_ceu_resources),
389 	.resource	= migor_ceu_resources,
390 	.dev	= {
391 		.platform_data	= &sh_mobile_ceu_info,
392 	},
393 	.archdata = {
394 		.hwblk_id = HWBLK_CEU,
395 	},
396 };
397 
398 static struct resource sdhi_cn9_resources[] = {
399 	[0] = {
400 		.name	= "SDHI",
401 		.start	= 0x04ce0000,
402 		.end	= 0x04ce01ff,
403 		.flags	= IORESOURCE_MEM,
404 	},
405 	[1] = {
406 		.start	= 100,
407 		.flags  = IORESOURCE_IRQ,
408 	},
409 };
410 
411 static struct sh_mobile_sdhi_info sh7724_sdhi_data = {
412 	.dma_slave_tx	= SHDMA_SLAVE_SDHI0_TX,
413 	.dma_slave_rx	= SHDMA_SLAVE_SDHI0_RX,
414 	.tmio_caps      = MMC_CAP_SDIO_IRQ,
415 };
416 
417 static struct platform_device sdhi_cn9_device = {
418 	.name		= "sh_mobile_sdhi",
419 	.num_resources	= ARRAY_SIZE(sdhi_cn9_resources),
420 	.resource	= sdhi_cn9_resources,
421 	.dev = {
422 		.platform_data	= &sh7724_sdhi_data,
423 	},
424 	.archdata = {
425 		.hwblk_id = HWBLK_SDHI,
426 	},
427 };
428 
429 static struct i2c_board_info migor_i2c_devices[] = {
430 	{
431 		I2C_BOARD_INFO("rs5c372b", 0x32),
432 	},
433 	{
434 		I2C_BOARD_INFO("migor_ts", 0x51),
435 		.irq = 38, /* IRQ6 */
436 	},
437 	{
438 		I2C_BOARD_INFO("wm8978", 0x1a),
439 	},
440 };
441 
442 static struct i2c_board_info migor_i2c_camera[] = {
443 	{
444 		I2C_BOARD_INFO("ov772x", 0x21),
445 	},
446 	{
447 		I2C_BOARD_INFO("tw9910", 0x45),
448 	},
449 };
450 
451 static struct ov772x_camera_info ov7725_info = {
452 	.flags		= OV772X_FLAG_8BIT,
453 };
454 
455 static struct soc_camera_link ov7725_link = {
456 	.power		= ov7725_power,
457 	.board_info	= &migor_i2c_camera[0],
458 	.i2c_adapter_id	= 0,
459 	.priv		= &ov7725_info,
460 };
461 
462 static struct tw9910_video_info tw9910_info = {
463 	.buswidth	= SOCAM_DATAWIDTH_8,
464 	.mpout		= TW9910_MPO_FIELD,
465 };
466 
467 static struct soc_camera_link tw9910_link = {
468 	.power		= tw9910_power,
469 	.board_info	= &migor_i2c_camera[1],
470 	.i2c_adapter_id	= 0,
471 	.priv		= &tw9910_info,
472 };
473 
474 static struct platform_device migor_camera[] = {
475 	{
476 		.name	= "soc-camera-pdrv",
477 		.id	= 0,
478 		.dev	= {
479 			.platform_data = &ov7725_link,
480 		},
481 	}, {
482 		.name	= "soc-camera-pdrv",
483 		.id	= 1,
484 		.dev	= {
485 			.platform_data = &tw9910_link,
486 		},
487 	},
488 };
489 
490 static struct platform_device *migor_devices[] __initdata = {
491 	&smc91x_eth_device,
492 	&sh_keysc_device,
493 	&migor_lcdc_device,
494 	&migor_ceu_device,
495 	&migor_nor_flash_device,
496 	&migor_nand_flash_device,
497 	&sdhi_cn9_device,
498 	&migor_camera[0],
499 	&migor_camera[1],
500 };
501 
502 extern char migor_sdram_enter_start;
503 extern char migor_sdram_enter_end;
504 extern char migor_sdram_leave_start;
505 extern char migor_sdram_leave_end;
506 
507 static int __init migor_devices_setup(void)
508 {
509 	/* register board specific self-refresh code */
510 	sh_mobile_register_self_refresh(SUSP_SH_STANDBY | SUSP_SH_SF,
511 					&migor_sdram_enter_start,
512 					&migor_sdram_enter_end,
513 					&migor_sdram_leave_start,
514 					&migor_sdram_leave_end);
515 	/* Let D11 LED show STATUS0 */
516 	gpio_request(GPIO_FN_STATUS0, NULL);
517 
518 	/* Lit D12 LED show PDSTATUS */
519 	gpio_request(GPIO_FN_PDSTATUS, NULL);
520 
521 	/* SMC91C111 - Enable IRQ0, Setup CS4 for 16-bit fast access */
522 	gpio_request(GPIO_FN_IRQ0, NULL);
523 	__raw_writel(0x00003400, BSC_CS4BCR);
524 	__raw_writel(0x00110080, BSC_CS4WCR);
525 
526 	/* KEYSC */
527 	gpio_request(GPIO_FN_KEYOUT0, NULL);
528 	gpio_request(GPIO_FN_KEYOUT1, NULL);
529 	gpio_request(GPIO_FN_KEYOUT2, NULL);
530 	gpio_request(GPIO_FN_KEYOUT3, NULL);
531 	gpio_request(GPIO_FN_KEYOUT4_IN6, NULL);
532 	gpio_request(GPIO_FN_KEYIN1, NULL);
533 	gpio_request(GPIO_FN_KEYIN2, NULL);
534 	gpio_request(GPIO_FN_KEYIN3, NULL);
535 	gpio_request(GPIO_FN_KEYIN4, NULL);
536 	gpio_request(GPIO_FN_KEYOUT5_IN5, NULL);
537 
538 	/* NAND Flash */
539 	gpio_request(GPIO_FN_CS6A_CE2B, NULL);
540 	__raw_writel((__raw_readl(BSC_CS6ABCR) & ~0x0600) | 0x0200, BSC_CS6ABCR);
541 	gpio_request(GPIO_PTA1, NULL);
542 	gpio_direction_input(GPIO_PTA1);
543 
544 	/* SDHI */
545 	gpio_request(GPIO_FN_SDHICD, NULL);
546 	gpio_request(GPIO_FN_SDHIWP, NULL);
547 	gpio_request(GPIO_FN_SDHID3, NULL);
548 	gpio_request(GPIO_FN_SDHID2, NULL);
549 	gpio_request(GPIO_FN_SDHID1, NULL);
550 	gpio_request(GPIO_FN_SDHID0, NULL);
551 	gpio_request(GPIO_FN_SDHICMD, NULL);
552 	gpio_request(GPIO_FN_SDHICLK, NULL);
553 
554 	/* Touch Panel */
555 	gpio_request(GPIO_FN_IRQ6, NULL);
556 
557 	/* LCD Panel */
558 #ifdef CONFIG_SH_MIGOR_QVGA /* LCDC - QVGA - Enable SYS Interface signals */
559 	gpio_request(GPIO_FN_LCDD17, NULL);
560 	gpio_request(GPIO_FN_LCDD16, NULL);
561 	gpio_request(GPIO_FN_LCDD15, NULL);
562 	gpio_request(GPIO_FN_LCDD14, NULL);
563 	gpio_request(GPIO_FN_LCDD13, NULL);
564 	gpio_request(GPIO_FN_LCDD12, NULL);
565 	gpio_request(GPIO_FN_LCDD11, NULL);
566 	gpio_request(GPIO_FN_LCDD10, NULL);
567 	gpio_request(GPIO_FN_LCDD8, NULL);
568 	gpio_request(GPIO_FN_LCDD7, NULL);
569 	gpio_request(GPIO_FN_LCDD6, NULL);
570 	gpio_request(GPIO_FN_LCDD5, NULL);
571 	gpio_request(GPIO_FN_LCDD4, NULL);
572 	gpio_request(GPIO_FN_LCDD3, NULL);
573 	gpio_request(GPIO_FN_LCDD2, NULL);
574 	gpio_request(GPIO_FN_LCDD1, NULL);
575 	gpio_request(GPIO_FN_LCDRS, NULL);
576 	gpio_request(GPIO_FN_LCDCS, NULL);
577 	gpio_request(GPIO_FN_LCDRD, NULL);
578 	gpio_request(GPIO_FN_LCDWR, NULL);
579 	gpio_request(GPIO_PTH2, NULL); /* LCD_DON */
580 	gpio_direction_output(GPIO_PTH2, 1);
581 #endif
582 #ifdef CONFIG_SH_MIGOR_RTA_WVGA /* LCDC - WVGA - Enable RGB Interface signals */
583 	gpio_request(GPIO_FN_LCDD15, NULL);
584 	gpio_request(GPIO_FN_LCDD14, NULL);
585 	gpio_request(GPIO_FN_LCDD13, NULL);
586 	gpio_request(GPIO_FN_LCDD12, NULL);
587 	gpio_request(GPIO_FN_LCDD11, NULL);
588 	gpio_request(GPIO_FN_LCDD10, NULL);
589 	gpio_request(GPIO_FN_LCDD9, NULL);
590 	gpio_request(GPIO_FN_LCDD8, NULL);
591 	gpio_request(GPIO_FN_LCDD7, NULL);
592 	gpio_request(GPIO_FN_LCDD6, NULL);
593 	gpio_request(GPIO_FN_LCDD5, NULL);
594 	gpio_request(GPIO_FN_LCDD4, NULL);
595 	gpio_request(GPIO_FN_LCDD3, NULL);
596 	gpio_request(GPIO_FN_LCDD2, NULL);
597 	gpio_request(GPIO_FN_LCDD1, NULL);
598 	gpio_request(GPIO_FN_LCDD0, NULL);
599 	gpio_request(GPIO_FN_LCDLCLK, NULL);
600 	gpio_request(GPIO_FN_LCDDCK, NULL);
601 	gpio_request(GPIO_FN_LCDVEPWC, NULL);
602 	gpio_request(GPIO_FN_LCDVCPWC, NULL);
603 	gpio_request(GPIO_FN_LCDVSYN, NULL);
604 	gpio_request(GPIO_FN_LCDHSYN, NULL);
605 	gpio_request(GPIO_FN_LCDDISP, NULL);
606 	gpio_request(GPIO_FN_LCDDON, NULL);
607 #endif
608 
609 	/* CEU */
610 	gpio_request(GPIO_FN_VIO_CLK2, NULL);
611 	gpio_request(GPIO_FN_VIO_VD2, NULL);
612 	gpio_request(GPIO_FN_VIO_HD2, NULL);
613 	gpio_request(GPIO_FN_VIO_FLD, NULL);
614 	gpio_request(GPIO_FN_VIO_CKO, NULL);
615 	gpio_request(GPIO_FN_VIO_D15, NULL);
616 	gpio_request(GPIO_FN_VIO_D14, NULL);
617 	gpio_request(GPIO_FN_VIO_D13, NULL);
618 	gpio_request(GPIO_FN_VIO_D12, NULL);
619 	gpio_request(GPIO_FN_VIO_D11, NULL);
620 	gpio_request(GPIO_FN_VIO_D10, NULL);
621 	gpio_request(GPIO_FN_VIO_D9, NULL);
622 	gpio_request(GPIO_FN_VIO_D8, NULL);
623 
624 	gpio_request(GPIO_PTT3, NULL); /* VIO_RST */
625 	gpio_direction_output(GPIO_PTT3, 0);
626 	gpio_request(GPIO_PTT2, NULL); /* TV_IN_EN */
627 	gpio_direction_output(GPIO_PTT2, 1);
628 	gpio_request(GPIO_PTT0, NULL); /* CAM_EN */
629 #ifdef CONFIG_SH_MIGOR_RTA_WVGA
630 	gpio_direction_output(GPIO_PTT0, 0);
631 #else
632 	gpio_direction_output(GPIO_PTT0, 1);
633 #endif
634 	__raw_writew(__raw_readw(PORT_MSELCRB) | 0x2000, PORT_MSELCRB); /* D15->D8 */
635 
636 	platform_resource_setup_memory(&migor_ceu_device, "ceu", 4 << 20);
637 
638 	/* SIU: Port B */
639 	gpio_request(GPIO_FN_SIUBOLR, NULL);
640 	gpio_request(GPIO_FN_SIUBOBT, NULL);
641 	gpio_request(GPIO_FN_SIUBISLD, NULL);
642 	gpio_request(GPIO_FN_SIUBOSLD, NULL);
643 	gpio_request(GPIO_FN_SIUMCKB, NULL);
644 
645 	/*
646 	 * The original driver sets SIUB OLR/OBT, ILR/IBT, and SIUA OLR/OBT to
647 	 * output. Need only SIUB, set to output for master mode (table 34.2)
648 	 */
649 	__raw_writew(__raw_readw(PORT_MSELCRA) | 1, PORT_MSELCRA);
650 
651 	i2c_register_board_info(0, migor_i2c_devices,
652 				ARRAY_SIZE(migor_i2c_devices));
653 
654 	return platform_add_devices(migor_devices, ARRAY_SIZE(migor_devices));
655 }
656 arch_initcall(migor_devices_setup);
657 
658 /* Return the board specific boot mode pin configuration */
659 static int migor_mode_pins(void)
660 {
661 	/* MD0=1, MD1=1, MD2=0: Clock Mode 3
662 	 * MD3=0: 16-bit Area0 Bus Width
663 	 * MD5=1: Little Endian
664 	 * TSTMD=1, MD8=0: Test Mode Disabled
665 	 */
666 	return MODE_PIN0 | MODE_PIN1 | MODE_PIN5;
667 }
668 
669 /*
670  * The Machine Vector
671  */
672 static struct sh_machine_vector mv_migor __initmv = {
673 	.mv_name		= "Migo-R",
674 	.mv_mode_pins		= migor_mode_pins,
675 };
676