1 /* 2 * Renesas System Solutions Asia Pte. Ltd - Migo-R 3 * 4 * Copyright (C) 2008 Magnus Damm 5 * 6 * This file is subject to the terms and conditions of the GNU General Public 7 * License. See the file "COPYING" in the main directory of this archive 8 * for more details. 9 */ 10 #include <linux/init.h> 11 #include <linux/platform_device.h> 12 #include <linux/interrupt.h> 13 #include <linux/input.h> 14 #include <linux/input/sh_keysc.h> 15 #include <linux/mfd/sh_mobile_sdhi.h> 16 #include <linux/mtd/physmap.h> 17 #include <linux/mtd/nand.h> 18 #include <linux/i2c.h> 19 #include <linux/smc91x.h> 20 #include <linux/delay.h> 21 #include <linux/clk.h> 22 #include <linux/gpio.h> 23 #include <video/sh_mobile_lcdc.h> 24 #include <media/sh_mobile_ceu.h> 25 #include <media/ov772x.h> 26 #include <media/tw9910.h> 27 #include <asm/clock.h> 28 #include <asm/machvec.h> 29 #include <asm/io.h> 30 #include <asm/suspend.h> 31 #include <mach/migor.h> 32 #include <cpu/sh7722.h> 33 34 /* Address IRQ Size Bus Description 35 * 0x00000000 64MB 16 NOR Flash (SP29PL256N) 36 * 0x0c000000 64MB 64 SDRAM (2xK4M563233G) 37 * 0x10000000 IRQ0 16 Ethernet (SMC91C111) 38 * 0x14000000 IRQ4 16 USB 2.0 Host Controller (M66596) 39 * 0x18000000 8GB 8 NAND Flash (K9K8G08U0A) 40 */ 41 42 static struct smc91x_platdata smc91x_info = { 43 .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, 44 }; 45 46 static struct resource smc91x_eth_resources[] = { 47 [0] = { 48 .name = "SMC91C111" , 49 .start = 0x10000300, 50 .end = 0x1000030f, 51 .flags = IORESOURCE_MEM, 52 }, 53 [1] = { 54 .start = 32, /* IRQ0 */ 55 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, 56 }, 57 }; 58 59 static struct platform_device smc91x_eth_device = { 60 .name = "smc91x", 61 .num_resources = ARRAY_SIZE(smc91x_eth_resources), 62 .resource = smc91x_eth_resources, 63 .dev = { 64 .platform_data = &smc91x_info, 65 }, 66 }; 67 68 static struct sh_keysc_info sh_keysc_info = { 69 .mode = SH_KEYSC_MODE_2, /* KEYOUT0->4, KEYIN1->5 */ 70 .scan_timing = 3, 71 .delay = 5, 72 .keycodes = { 73 0, KEY_UP, KEY_DOWN, KEY_LEFT, KEY_RIGHT, KEY_ENTER, 74 0, KEY_F, KEY_C, KEY_D, KEY_H, KEY_1, 75 0, KEY_2, KEY_3, KEY_4, KEY_5, KEY_6, 76 0, KEY_7, KEY_8, KEY_9, KEY_S, KEY_0, 77 0, KEY_P, KEY_STOP, KEY_REWIND, KEY_PLAY, KEY_FASTFORWARD, 78 }, 79 }; 80 81 static struct resource sh_keysc_resources[] = { 82 [0] = { 83 .start = 0x044b0000, 84 .end = 0x044b000f, 85 .flags = IORESOURCE_MEM, 86 }, 87 [1] = { 88 .start = 79, 89 .flags = IORESOURCE_IRQ, 90 }, 91 }; 92 93 static struct platform_device sh_keysc_device = { 94 .name = "sh_keysc", 95 .id = 0, /* "keysc0" clock */ 96 .num_resources = ARRAY_SIZE(sh_keysc_resources), 97 .resource = sh_keysc_resources, 98 .dev = { 99 .platform_data = &sh_keysc_info, 100 }, 101 .archdata = { 102 .hwblk_id = HWBLK_KEYSC, 103 }, 104 }; 105 106 static struct mtd_partition migor_nor_flash_partitions[] = 107 { 108 { 109 .name = "uboot", 110 .offset = 0, 111 .size = (1 * 1024 * 1024), 112 .mask_flags = MTD_WRITEABLE, /* Read-only */ 113 }, 114 { 115 .name = "rootfs", 116 .offset = MTDPART_OFS_APPEND, 117 .size = (15 * 1024 * 1024), 118 }, 119 { 120 .name = "other", 121 .offset = MTDPART_OFS_APPEND, 122 .size = MTDPART_SIZ_FULL, 123 }, 124 }; 125 126 static struct physmap_flash_data migor_nor_flash_data = { 127 .width = 2, 128 .parts = migor_nor_flash_partitions, 129 .nr_parts = ARRAY_SIZE(migor_nor_flash_partitions), 130 }; 131 132 static struct resource migor_nor_flash_resources[] = { 133 [0] = { 134 .name = "NOR Flash", 135 .start = 0x00000000, 136 .end = 0x03ffffff, 137 .flags = IORESOURCE_MEM, 138 } 139 }; 140 141 static struct platform_device migor_nor_flash_device = { 142 .name = "physmap-flash", 143 .resource = migor_nor_flash_resources, 144 .num_resources = ARRAY_SIZE(migor_nor_flash_resources), 145 .dev = { 146 .platform_data = &migor_nor_flash_data, 147 }, 148 }; 149 150 static struct mtd_partition migor_nand_flash_partitions[] = { 151 { 152 .name = "nanddata1", 153 .offset = 0x0, 154 .size = 512 * 1024 * 1024, 155 }, 156 { 157 .name = "nanddata2", 158 .offset = MTDPART_OFS_APPEND, 159 .size = 512 * 1024 * 1024, 160 }, 161 }; 162 163 static void migor_nand_flash_cmd_ctl(struct mtd_info *mtd, int cmd, 164 unsigned int ctrl) 165 { 166 struct nand_chip *chip = mtd->priv; 167 168 if (cmd == NAND_CMD_NONE) 169 return; 170 171 if (ctrl & NAND_CLE) 172 writeb(cmd, chip->IO_ADDR_W + 0x00400000); 173 else if (ctrl & NAND_ALE) 174 writeb(cmd, chip->IO_ADDR_W + 0x00800000); 175 else 176 writeb(cmd, chip->IO_ADDR_W); 177 } 178 179 static int migor_nand_flash_ready(struct mtd_info *mtd) 180 { 181 return gpio_get_value(GPIO_PTA1); /* NAND_RBn */ 182 } 183 184 static struct platform_nand_data migor_nand_flash_data = { 185 .chip = { 186 .nr_chips = 1, 187 .partitions = migor_nand_flash_partitions, 188 .nr_partitions = ARRAY_SIZE(migor_nand_flash_partitions), 189 .chip_delay = 20, 190 .part_probe_types = (const char *[]) { "cmdlinepart", NULL }, 191 }, 192 .ctrl = { 193 .dev_ready = migor_nand_flash_ready, 194 .cmd_ctrl = migor_nand_flash_cmd_ctl, 195 }, 196 }; 197 198 static struct resource migor_nand_flash_resources[] = { 199 [0] = { 200 .name = "NAND Flash", 201 .start = 0x18000000, 202 .end = 0x18ffffff, 203 .flags = IORESOURCE_MEM, 204 }, 205 }; 206 207 static struct platform_device migor_nand_flash_device = { 208 .name = "gen_nand", 209 .resource = migor_nand_flash_resources, 210 .num_resources = ARRAY_SIZE(migor_nand_flash_resources), 211 .dev = { 212 .platform_data = &migor_nand_flash_data, 213 } 214 }; 215 216 const static struct fb_videomode migor_lcd_modes[] = { 217 { 218 #if defined(CONFIG_SH_MIGOR_RTA_WVGA) 219 .name = "LB070WV1", 220 .xres = 800, 221 .yres = 480, 222 .left_margin = 64, 223 .right_margin = 16, 224 .hsync_len = 120, 225 .sync = 0, 226 #elif defined(CONFIG_SH_MIGOR_QVGA) 227 .name = "PH240320T", 228 .xres = 320, 229 .yres = 240, 230 .left_margin = 0, 231 .right_margin = 16, 232 .hsync_len = 8, 233 .sync = FB_SYNC_HOR_HIGH_ACT, 234 #endif 235 .upper_margin = 1, 236 .lower_margin = 17, 237 .vsync_len = 2, 238 }, 239 }; 240 241 static struct sh_mobile_lcdc_info sh_mobile_lcdc_info = { 242 #if defined(CONFIG_SH_MIGOR_RTA_WVGA) 243 .clock_source = LCDC_CLK_BUS, 244 .ch[0] = { 245 .chan = LCDC_CHAN_MAINLCD, 246 .bpp = 16, 247 .interface_type = RGB16, 248 .clock_divider = 2, 249 .lcd_cfg = migor_lcd_modes, 250 .num_cfg = ARRAY_SIZE(migor_lcd_modes), 251 .lcd_size_cfg = { /* 7.0 inch */ 252 .width = 152, 253 .height = 91, 254 }, 255 } 256 #elif defined(CONFIG_SH_MIGOR_QVGA) 257 .clock_source = LCDC_CLK_PERIPHERAL, 258 .ch[0] = { 259 .chan = LCDC_CHAN_MAINLCD, 260 .bpp = 16, 261 .interface_type = SYS16A, 262 .clock_divider = 10, 263 .lcd_cfg = migor_lcd_modes, 264 .num_cfg = ARRAY_SIZE(migor_lcd_modes), 265 .lcd_size_cfg = { /* 2.4 inch */ 266 .width = 49, 267 .height = 37, 268 }, 269 .board_cfg = { 270 .setup_sys = migor_lcd_qvga_setup, 271 }, 272 .sys_bus_cfg = { 273 .ldmt2r = 0x06000a09, 274 .ldmt3r = 0x180e3418, 275 /* set 1s delay to encourage fsync() */ 276 .deferred_io_msec = 1000, 277 }, 278 } 279 #endif 280 }; 281 282 static struct resource migor_lcdc_resources[] = { 283 [0] = { 284 .name = "LCDC", 285 .start = 0xfe940000, /* P4-only space */ 286 .end = 0xfe942fff, 287 .flags = IORESOURCE_MEM, 288 }, 289 [1] = { 290 .start = 28, 291 .flags = IORESOURCE_IRQ, 292 }, 293 }; 294 295 static struct platform_device migor_lcdc_device = { 296 .name = "sh_mobile_lcdc_fb", 297 .num_resources = ARRAY_SIZE(migor_lcdc_resources), 298 .resource = migor_lcdc_resources, 299 .dev = { 300 .platform_data = &sh_mobile_lcdc_info, 301 }, 302 .archdata = { 303 .hwblk_id = HWBLK_LCDC, 304 }, 305 }; 306 307 static struct clk *camera_clk; 308 static DEFINE_MUTEX(camera_lock); 309 310 static void camera_power_on(int is_tw) 311 { 312 mutex_lock(&camera_lock); 313 314 /* Use 10 MHz VIO_CKO instead of 24 MHz to work 315 * around signal quality issues on Panel Board V2.1. 316 */ 317 camera_clk = clk_get(NULL, "video_clk"); 318 clk_set_rate(camera_clk, 10000000); 319 clk_enable(camera_clk); /* start VIO_CKO */ 320 321 /* use VIO_RST to take camera out of reset */ 322 mdelay(10); 323 if (is_tw) { 324 gpio_set_value(GPIO_PTT2, 0); 325 gpio_set_value(GPIO_PTT0, 0); 326 } else { 327 gpio_set_value(GPIO_PTT0, 1); 328 } 329 gpio_set_value(GPIO_PTT3, 0); 330 mdelay(10); 331 gpio_set_value(GPIO_PTT3, 1); 332 mdelay(10); /* wait to let chip come out of reset */ 333 } 334 335 static void camera_power_off(void) 336 { 337 clk_disable(camera_clk); /* stop VIO_CKO */ 338 clk_put(camera_clk); 339 340 gpio_set_value(GPIO_PTT3, 0); 341 mutex_unlock(&camera_lock); 342 } 343 344 static int ov7725_power(struct device *dev, int mode) 345 { 346 if (mode) 347 camera_power_on(0); 348 else 349 camera_power_off(); 350 351 return 0; 352 } 353 354 static int tw9910_power(struct device *dev, int mode) 355 { 356 if (mode) 357 camera_power_on(1); 358 else 359 camera_power_off(); 360 361 return 0; 362 } 363 364 static struct sh_mobile_ceu_info sh_mobile_ceu_info = { 365 .flags = SH_CEU_FLAG_USE_8BIT_BUS, 366 }; 367 368 static struct resource migor_ceu_resources[] = { 369 [0] = { 370 .name = "CEU", 371 .start = 0xfe910000, 372 .end = 0xfe91009f, 373 .flags = IORESOURCE_MEM, 374 }, 375 [1] = { 376 .start = 52, 377 .flags = IORESOURCE_IRQ, 378 }, 379 [2] = { 380 /* place holder for contiguous memory */ 381 }, 382 }; 383 384 static struct platform_device migor_ceu_device = { 385 .name = "sh_mobile_ceu", 386 .id = 0, /* "ceu0" clock */ 387 .num_resources = ARRAY_SIZE(migor_ceu_resources), 388 .resource = migor_ceu_resources, 389 .dev = { 390 .platform_data = &sh_mobile_ceu_info, 391 }, 392 .archdata = { 393 .hwblk_id = HWBLK_CEU, 394 }, 395 }; 396 397 static struct resource sdhi_cn9_resources[] = { 398 [0] = { 399 .name = "SDHI", 400 .start = 0x04ce0000, 401 .end = 0x04ce01ff, 402 .flags = IORESOURCE_MEM, 403 }, 404 [1] = { 405 .start = 100, 406 .flags = IORESOURCE_IRQ, 407 }, 408 }; 409 410 static struct sh_mobile_sdhi_info sh7724_sdhi_data = { 411 .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX, 412 .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX, 413 }; 414 415 static struct platform_device sdhi_cn9_device = { 416 .name = "sh_mobile_sdhi", 417 .num_resources = ARRAY_SIZE(sdhi_cn9_resources), 418 .resource = sdhi_cn9_resources, 419 .dev = { 420 .platform_data = &sh7724_sdhi_data, 421 }, 422 .archdata = { 423 .hwblk_id = HWBLK_SDHI, 424 }, 425 }; 426 427 static struct i2c_board_info migor_i2c_devices[] = { 428 { 429 I2C_BOARD_INFO("rs5c372b", 0x32), 430 }, 431 { 432 I2C_BOARD_INFO("migor_ts", 0x51), 433 .irq = 38, /* IRQ6 */ 434 }, 435 { 436 I2C_BOARD_INFO("wm8978", 0x1a), 437 }, 438 }; 439 440 static struct i2c_board_info migor_i2c_camera[] = { 441 { 442 I2C_BOARD_INFO("ov772x", 0x21), 443 }, 444 { 445 I2C_BOARD_INFO("tw9910", 0x45), 446 }, 447 }; 448 449 static struct ov772x_camera_info ov7725_info = { 450 .flags = OV772X_FLAG_8BIT, 451 }; 452 453 static struct soc_camera_link ov7725_link = { 454 .power = ov7725_power, 455 .board_info = &migor_i2c_camera[0], 456 .i2c_adapter_id = 0, 457 .priv = &ov7725_info, 458 }; 459 460 static struct tw9910_video_info tw9910_info = { 461 .buswidth = SOCAM_DATAWIDTH_8, 462 .mpout = TW9910_MPO_FIELD, 463 }; 464 465 static struct soc_camera_link tw9910_link = { 466 .power = tw9910_power, 467 .board_info = &migor_i2c_camera[1], 468 .i2c_adapter_id = 0, 469 .priv = &tw9910_info, 470 }; 471 472 static struct platform_device migor_camera[] = { 473 { 474 .name = "soc-camera-pdrv", 475 .id = 0, 476 .dev = { 477 .platform_data = &ov7725_link, 478 }, 479 }, { 480 .name = "soc-camera-pdrv", 481 .id = 1, 482 .dev = { 483 .platform_data = &tw9910_link, 484 }, 485 }, 486 }; 487 488 static struct platform_device *migor_devices[] __initdata = { 489 &smc91x_eth_device, 490 &sh_keysc_device, 491 &migor_lcdc_device, 492 &migor_ceu_device, 493 &migor_nor_flash_device, 494 &migor_nand_flash_device, 495 &sdhi_cn9_device, 496 &migor_camera[0], 497 &migor_camera[1], 498 }; 499 500 extern char migor_sdram_enter_start; 501 extern char migor_sdram_enter_end; 502 extern char migor_sdram_leave_start; 503 extern char migor_sdram_leave_end; 504 505 static int __init migor_devices_setup(void) 506 { 507 /* register board specific self-refresh code */ 508 sh_mobile_register_self_refresh(SUSP_SH_STANDBY | SUSP_SH_SF, 509 &migor_sdram_enter_start, 510 &migor_sdram_enter_end, 511 &migor_sdram_leave_start, 512 &migor_sdram_leave_end); 513 /* Let D11 LED show STATUS0 */ 514 gpio_request(GPIO_FN_STATUS0, NULL); 515 516 /* Lit D12 LED show PDSTATUS */ 517 gpio_request(GPIO_FN_PDSTATUS, NULL); 518 519 /* SMC91C111 - Enable IRQ0, Setup CS4 for 16-bit fast access */ 520 gpio_request(GPIO_FN_IRQ0, NULL); 521 __raw_writel(0x00003400, BSC_CS4BCR); 522 __raw_writel(0x00110080, BSC_CS4WCR); 523 524 /* KEYSC */ 525 gpio_request(GPIO_FN_KEYOUT0, NULL); 526 gpio_request(GPIO_FN_KEYOUT1, NULL); 527 gpio_request(GPIO_FN_KEYOUT2, NULL); 528 gpio_request(GPIO_FN_KEYOUT3, NULL); 529 gpio_request(GPIO_FN_KEYOUT4_IN6, NULL); 530 gpio_request(GPIO_FN_KEYIN1, NULL); 531 gpio_request(GPIO_FN_KEYIN2, NULL); 532 gpio_request(GPIO_FN_KEYIN3, NULL); 533 gpio_request(GPIO_FN_KEYIN4, NULL); 534 gpio_request(GPIO_FN_KEYOUT5_IN5, NULL); 535 536 /* NAND Flash */ 537 gpio_request(GPIO_FN_CS6A_CE2B, NULL); 538 __raw_writel((__raw_readl(BSC_CS6ABCR) & ~0x0600) | 0x0200, BSC_CS6ABCR); 539 gpio_request(GPIO_PTA1, NULL); 540 gpio_direction_input(GPIO_PTA1); 541 542 /* SDHI */ 543 gpio_request(GPIO_FN_SDHICD, NULL); 544 gpio_request(GPIO_FN_SDHIWP, NULL); 545 gpio_request(GPIO_FN_SDHID3, NULL); 546 gpio_request(GPIO_FN_SDHID2, NULL); 547 gpio_request(GPIO_FN_SDHID1, NULL); 548 gpio_request(GPIO_FN_SDHID0, NULL); 549 gpio_request(GPIO_FN_SDHICMD, NULL); 550 gpio_request(GPIO_FN_SDHICLK, NULL); 551 552 /* Touch Panel */ 553 gpio_request(GPIO_FN_IRQ6, NULL); 554 555 /* LCD Panel */ 556 #ifdef CONFIG_SH_MIGOR_QVGA /* LCDC - QVGA - Enable SYS Interface signals */ 557 gpio_request(GPIO_FN_LCDD17, NULL); 558 gpio_request(GPIO_FN_LCDD16, NULL); 559 gpio_request(GPIO_FN_LCDD15, NULL); 560 gpio_request(GPIO_FN_LCDD14, NULL); 561 gpio_request(GPIO_FN_LCDD13, NULL); 562 gpio_request(GPIO_FN_LCDD12, NULL); 563 gpio_request(GPIO_FN_LCDD11, NULL); 564 gpio_request(GPIO_FN_LCDD10, NULL); 565 gpio_request(GPIO_FN_LCDD8, NULL); 566 gpio_request(GPIO_FN_LCDD7, NULL); 567 gpio_request(GPIO_FN_LCDD6, NULL); 568 gpio_request(GPIO_FN_LCDD5, NULL); 569 gpio_request(GPIO_FN_LCDD4, NULL); 570 gpio_request(GPIO_FN_LCDD3, NULL); 571 gpio_request(GPIO_FN_LCDD2, NULL); 572 gpio_request(GPIO_FN_LCDD1, NULL); 573 gpio_request(GPIO_FN_LCDRS, NULL); 574 gpio_request(GPIO_FN_LCDCS, NULL); 575 gpio_request(GPIO_FN_LCDRD, NULL); 576 gpio_request(GPIO_FN_LCDWR, NULL); 577 gpio_request(GPIO_PTH2, NULL); /* LCD_DON */ 578 gpio_direction_output(GPIO_PTH2, 1); 579 #endif 580 #ifdef CONFIG_SH_MIGOR_RTA_WVGA /* LCDC - WVGA - Enable RGB Interface signals */ 581 gpio_request(GPIO_FN_LCDD15, NULL); 582 gpio_request(GPIO_FN_LCDD14, NULL); 583 gpio_request(GPIO_FN_LCDD13, NULL); 584 gpio_request(GPIO_FN_LCDD12, NULL); 585 gpio_request(GPIO_FN_LCDD11, NULL); 586 gpio_request(GPIO_FN_LCDD10, NULL); 587 gpio_request(GPIO_FN_LCDD9, NULL); 588 gpio_request(GPIO_FN_LCDD8, NULL); 589 gpio_request(GPIO_FN_LCDD7, NULL); 590 gpio_request(GPIO_FN_LCDD6, NULL); 591 gpio_request(GPIO_FN_LCDD5, NULL); 592 gpio_request(GPIO_FN_LCDD4, NULL); 593 gpio_request(GPIO_FN_LCDD3, NULL); 594 gpio_request(GPIO_FN_LCDD2, NULL); 595 gpio_request(GPIO_FN_LCDD1, NULL); 596 gpio_request(GPIO_FN_LCDD0, NULL); 597 gpio_request(GPIO_FN_LCDLCLK, NULL); 598 gpio_request(GPIO_FN_LCDDCK, NULL); 599 gpio_request(GPIO_FN_LCDVEPWC, NULL); 600 gpio_request(GPIO_FN_LCDVCPWC, NULL); 601 gpio_request(GPIO_FN_LCDVSYN, NULL); 602 gpio_request(GPIO_FN_LCDHSYN, NULL); 603 gpio_request(GPIO_FN_LCDDISP, NULL); 604 gpio_request(GPIO_FN_LCDDON, NULL); 605 #endif 606 607 /* CEU */ 608 gpio_request(GPIO_FN_VIO_CLK2, NULL); 609 gpio_request(GPIO_FN_VIO_VD2, NULL); 610 gpio_request(GPIO_FN_VIO_HD2, NULL); 611 gpio_request(GPIO_FN_VIO_FLD, NULL); 612 gpio_request(GPIO_FN_VIO_CKO, NULL); 613 gpio_request(GPIO_FN_VIO_D15, NULL); 614 gpio_request(GPIO_FN_VIO_D14, NULL); 615 gpio_request(GPIO_FN_VIO_D13, NULL); 616 gpio_request(GPIO_FN_VIO_D12, NULL); 617 gpio_request(GPIO_FN_VIO_D11, NULL); 618 gpio_request(GPIO_FN_VIO_D10, NULL); 619 gpio_request(GPIO_FN_VIO_D9, NULL); 620 gpio_request(GPIO_FN_VIO_D8, NULL); 621 622 gpio_request(GPIO_PTT3, NULL); /* VIO_RST */ 623 gpio_direction_output(GPIO_PTT3, 0); 624 gpio_request(GPIO_PTT2, NULL); /* TV_IN_EN */ 625 gpio_direction_output(GPIO_PTT2, 1); 626 gpio_request(GPIO_PTT0, NULL); /* CAM_EN */ 627 #ifdef CONFIG_SH_MIGOR_RTA_WVGA 628 gpio_direction_output(GPIO_PTT0, 0); 629 #else 630 gpio_direction_output(GPIO_PTT0, 1); 631 #endif 632 __raw_writew(__raw_readw(PORT_MSELCRB) | 0x2000, PORT_MSELCRB); /* D15->D8 */ 633 634 platform_resource_setup_memory(&migor_ceu_device, "ceu", 4 << 20); 635 636 /* SIU: Port B */ 637 gpio_request(GPIO_FN_SIUBOLR, NULL); 638 gpio_request(GPIO_FN_SIUBOBT, NULL); 639 gpio_request(GPIO_FN_SIUBISLD, NULL); 640 gpio_request(GPIO_FN_SIUBOSLD, NULL); 641 gpio_request(GPIO_FN_SIUMCKB, NULL); 642 643 /* 644 * The original driver sets SIUB OLR/OBT, ILR/IBT, and SIUA OLR/OBT to 645 * output. Need only SIUB, set to output for master mode (table 34.2) 646 */ 647 __raw_writew(__raw_readw(PORT_MSELCRA) | 1, PORT_MSELCRA); 648 649 i2c_register_board_info(0, migor_i2c_devices, 650 ARRAY_SIZE(migor_i2c_devices)); 651 652 return platform_add_devices(migor_devices, ARRAY_SIZE(migor_devices)); 653 } 654 arch_initcall(migor_devices_setup); 655 656 /* Return the board specific boot mode pin configuration */ 657 static int migor_mode_pins(void) 658 { 659 /* MD0=1, MD1=1, MD2=0: Clock Mode 3 660 * MD3=0: 16-bit Area0 Bus Width 661 * MD5=1: Little Endian 662 * TSTMD=1, MD8=0: Test Mode Disabled 663 */ 664 return MODE_PIN0 | MODE_PIN1 | MODE_PIN5; 665 } 666 667 /* 668 * The Machine Vector 669 */ 670 static struct sh_machine_vector mv_migor __initmv = { 671 .mv_name = "Migo-R", 672 .mv_mode_pins = migor_mode_pins, 673 }; 674