1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Renesas System Solutions Asia Pte. Ltd - Migo-R 4 * 5 * Copyright (C) 2008 Magnus Damm 6 */ 7 #include <linux/clkdev.h> 8 #include <linux/init.h> 9 #include <linux/platform_device.h> 10 #include <linux/interrupt.h> 11 #include <linux/input.h> 12 #include <linux/input/sh_keysc.h> 13 #include <linux/memblock.h> 14 #include <linux/mmc/host.h> 15 #include <linux/mtd/physmap.h> 16 #include <linux/mfd/tmio.h> 17 #include <linux/mtd/rawnand.h> 18 #include <linux/i2c.h> 19 #include <linux/regulator/fixed.h> 20 #include <linux/regulator/machine.h> 21 #include <linux/smc91x.h> 22 #include <linux/delay.h> 23 #include <linux/clk.h> 24 #include <linux/gpio.h> 25 #include <linux/gpio/machine.h> 26 #include <linux/videodev2.h> 27 #include <linux/sh_intc.h> 28 #include <video/sh_mobile_lcdc.h> 29 #include <media/drv-intf/renesas-ceu.h> 30 #include <media/i2c/ov772x.h> 31 #include <media/i2c/tw9910.h> 32 #include <asm/clock.h> 33 #include <asm/machvec.h> 34 #include <asm/io.h> 35 #include <asm/suspend.h> 36 #include <mach/migor.h> 37 #include <cpu/sh7722.h> 38 39 /* Address IRQ Size Bus Description 40 * 0x00000000 64MB 16 NOR Flash (SP29PL256N) 41 * 0x0c000000 64MB 64 SDRAM (2xK4M563233G) 42 * 0x10000000 IRQ0 16 Ethernet (SMC91C111) 43 * 0x14000000 IRQ4 16 USB 2.0 Host Controller (M66596) 44 * 0x18000000 8GB 8 NAND Flash (K9K8G08U0A) 45 */ 46 47 #define CEU_BUFFER_MEMORY_SIZE (4 << 20) 48 static phys_addr_t ceu_dma_membase; 49 50 static struct smc91x_platdata smc91x_info = { 51 .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, 52 }; 53 54 static struct resource smc91x_eth_resources[] = { 55 [0] = { 56 .name = "SMC91C111" , 57 .start = 0x10000300, 58 .end = 0x1000030f, 59 .flags = IORESOURCE_MEM, 60 }, 61 [1] = { 62 .start = evt2irq(0x600), /* IRQ0 */ 63 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, 64 }, 65 }; 66 67 static struct platform_device smc91x_eth_device = { 68 .name = "smc91x", 69 .num_resources = ARRAY_SIZE(smc91x_eth_resources), 70 .resource = smc91x_eth_resources, 71 .dev = { 72 .platform_data = &smc91x_info, 73 }, 74 }; 75 76 static struct sh_keysc_info sh_keysc_info = { 77 .mode = SH_KEYSC_MODE_2, /* KEYOUT0->4, KEYIN1->5 */ 78 .scan_timing = 3, 79 .delay = 5, 80 .keycodes = { 81 0, KEY_UP, KEY_DOWN, KEY_LEFT, KEY_RIGHT, KEY_ENTER, 82 0, KEY_F, KEY_C, KEY_D, KEY_H, KEY_1, 83 0, KEY_2, KEY_3, KEY_4, KEY_5, KEY_6, 84 0, KEY_7, KEY_8, KEY_9, KEY_S, KEY_0, 85 0, KEY_P, KEY_STOP, KEY_REWIND, KEY_PLAY, KEY_FASTFORWARD, 86 }, 87 }; 88 89 static struct resource sh_keysc_resources[] = { 90 [0] = { 91 .start = 0x044b0000, 92 .end = 0x044b000f, 93 .flags = IORESOURCE_MEM, 94 }, 95 [1] = { 96 .start = evt2irq(0xbe0), 97 .flags = IORESOURCE_IRQ, 98 }, 99 }; 100 101 static struct platform_device sh_keysc_device = { 102 .name = "sh_keysc", 103 .id = 0, /* "keysc0" clock */ 104 .num_resources = ARRAY_SIZE(sh_keysc_resources), 105 .resource = sh_keysc_resources, 106 .dev = { 107 .platform_data = &sh_keysc_info, 108 }, 109 }; 110 111 static struct mtd_partition migor_nor_flash_partitions[] = 112 { 113 { 114 .name = "uboot", 115 .offset = 0, 116 .size = (1 * 1024 * 1024), 117 .mask_flags = MTD_WRITEABLE, /* Read-only */ 118 }, 119 { 120 .name = "rootfs", 121 .offset = MTDPART_OFS_APPEND, 122 .size = (15 * 1024 * 1024), 123 }, 124 { 125 .name = "other", 126 .offset = MTDPART_OFS_APPEND, 127 .size = MTDPART_SIZ_FULL, 128 }, 129 }; 130 131 static struct physmap_flash_data migor_nor_flash_data = { 132 .width = 2, 133 .parts = migor_nor_flash_partitions, 134 .nr_parts = ARRAY_SIZE(migor_nor_flash_partitions), 135 }; 136 137 static struct resource migor_nor_flash_resources[] = { 138 [0] = { 139 .name = "NOR Flash", 140 .start = 0x00000000, 141 .end = 0x03ffffff, 142 .flags = IORESOURCE_MEM, 143 } 144 }; 145 146 static struct platform_device migor_nor_flash_device = { 147 .name = "physmap-flash", 148 .resource = migor_nor_flash_resources, 149 .num_resources = ARRAY_SIZE(migor_nor_flash_resources), 150 .dev = { 151 .platform_data = &migor_nor_flash_data, 152 }, 153 }; 154 155 static struct mtd_partition migor_nand_flash_partitions[] = { 156 { 157 .name = "nanddata1", 158 .offset = 0x0, 159 .size = 512 * 1024 * 1024, 160 }, 161 { 162 .name = "nanddata2", 163 .offset = MTDPART_OFS_APPEND, 164 .size = 512 * 1024 * 1024, 165 }, 166 }; 167 168 static void migor_nand_flash_cmd_ctl(struct mtd_info *mtd, int cmd, 169 unsigned int ctrl) 170 { 171 struct nand_chip *chip = mtd_to_nand(mtd); 172 173 if (cmd == NAND_CMD_NONE) 174 return; 175 176 if (ctrl & NAND_CLE) 177 writeb(cmd, chip->IO_ADDR_W + 0x00400000); 178 else if (ctrl & NAND_ALE) 179 writeb(cmd, chip->IO_ADDR_W + 0x00800000); 180 else 181 writeb(cmd, chip->IO_ADDR_W); 182 } 183 184 static int migor_nand_flash_ready(struct mtd_info *mtd) 185 { 186 return gpio_get_value(GPIO_PTA1); /* NAND_RBn */ 187 } 188 189 static struct platform_nand_data migor_nand_flash_data = { 190 .chip = { 191 .nr_chips = 1, 192 .partitions = migor_nand_flash_partitions, 193 .nr_partitions = ARRAY_SIZE(migor_nand_flash_partitions), 194 .chip_delay = 20, 195 }, 196 .ctrl = { 197 .dev_ready = migor_nand_flash_ready, 198 .cmd_ctrl = migor_nand_flash_cmd_ctl, 199 }, 200 }; 201 202 static struct resource migor_nand_flash_resources[] = { 203 [0] = { 204 .name = "NAND Flash", 205 .start = 0x18000000, 206 .end = 0x18ffffff, 207 .flags = IORESOURCE_MEM, 208 }, 209 }; 210 211 static struct platform_device migor_nand_flash_device = { 212 .name = "gen_nand", 213 .resource = migor_nand_flash_resources, 214 .num_resources = ARRAY_SIZE(migor_nand_flash_resources), 215 .dev = { 216 .platform_data = &migor_nand_flash_data, 217 } 218 }; 219 220 static const struct fb_videomode migor_lcd_modes[] = { 221 { 222 #if defined(CONFIG_SH_MIGOR_RTA_WVGA) 223 .name = "LB070WV1", 224 .xres = 800, 225 .yres = 480, 226 .left_margin = 64, 227 .right_margin = 16, 228 .hsync_len = 120, 229 .sync = 0, 230 #elif defined(CONFIG_SH_MIGOR_QVGA) 231 .name = "PH240320T", 232 .xres = 320, 233 .yres = 240, 234 .left_margin = 0, 235 .right_margin = 16, 236 .hsync_len = 8, 237 .sync = FB_SYNC_HOR_HIGH_ACT, 238 #endif 239 .upper_margin = 1, 240 .lower_margin = 17, 241 .vsync_len = 2, 242 }, 243 }; 244 245 static struct sh_mobile_lcdc_info sh_mobile_lcdc_info = { 246 #if defined(CONFIG_SH_MIGOR_RTA_WVGA) 247 .clock_source = LCDC_CLK_BUS, 248 .ch[0] = { 249 .chan = LCDC_CHAN_MAINLCD, 250 .fourcc = V4L2_PIX_FMT_RGB565, 251 .interface_type = RGB16, 252 .clock_divider = 2, 253 .lcd_modes = migor_lcd_modes, 254 .num_modes = ARRAY_SIZE(migor_lcd_modes), 255 .panel_cfg = { /* 7.0 inch */ 256 .width = 152, 257 .height = 91, 258 }, 259 } 260 #elif defined(CONFIG_SH_MIGOR_QVGA) 261 .clock_source = LCDC_CLK_PERIPHERAL, 262 .ch[0] = { 263 .chan = LCDC_CHAN_MAINLCD, 264 .fourcc = V4L2_PIX_FMT_RGB565, 265 .interface_type = SYS16A, 266 .clock_divider = 10, 267 .lcd_modes = migor_lcd_modes, 268 .num_modes = ARRAY_SIZE(migor_lcd_modes), 269 .panel_cfg = { 270 .width = 49, /* 2.4 inch */ 271 .height = 37, 272 .setup_sys = migor_lcd_qvga_setup, 273 }, 274 .sys_bus_cfg = { 275 .ldmt2r = 0x06000a09, 276 .ldmt3r = 0x180e3418, 277 /* set 1s delay to encourage fsync() */ 278 .deferred_io_msec = 1000, 279 }, 280 } 281 #endif 282 }; 283 284 static struct resource migor_lcdc_resources[] = { 285 [0] = { 286 .name = "LCDC", 287 .start = 0xfe940000, /* P4-only space */ 288 .end = 0xfe942fff, 289 .flags = IORESOURCE_MEM, 290 }, 291 [1] = { 292 .start = evt2irq(0x580), 293 .flags = IORESOURCE_IRQ, 294 }, 295 }; 296 297 static struct platform_device migor_lcdc_device = { 298 .name = "sh_mobile_lcdc_fb", 299 .num_resources = ARRAY_SIZE(migor_lcdc_resources), 300 .resource = migor_lcdc_resources, 301 .dev = { 302 .platform_data = &sh_mobile_lcdc_info, 303 }, 304 }; 305 306 static struct ceu_platform_data ceu_pdata = { 307 .num_subdevs = 2, 308 .subdevs = { 309 { /* [0] = ov772x */ 310 .flags = 0, 311 .bus_width = 8, 312 .bus_shift = 0, 313 .i2c_adapter_id = 0, 314 .i2c_address = 0x21, 315 }, 316 { /* [1] = tw9910 */ 317 .flags = 0, 318 .bus_width = 8, 319 .bus_shift = 0, 320 .i2c_adapter_id = 0, 321 .i2c_address = 0x45, 322 }, 323 }, 324 }; 325 326 static struct resource migor_ceu_resources[] = { 327 [0] = { 328 .name = "CEU", 329 .start = 0xfe910000, 330 .end = 0xfe91009f, 331 .flags = IORESOURCE_MEM, 332 }, 333 [1] = { 334 .start = evt2irq(0x880), 335 .flags = IORESOURCE_IRQ, 336 }, 337 }; 338 339 static struct platform_device migor_ceu_device = { 340 .name = "renesas-ceu", 341 .id = 0, /* ceu.0 */ 342 .num_resources = ARRAY_SIZE(migor_ceu_resources), 343 .resource = migor_ceu_resources, 344 .dev = { 345 .platform_data = &ceu_pdata, 346 }, 347 }; 348 349 /* Powerdown/reset gpios for CEU image sensors */ 350 static struct gpiod_lookup_table ov7725_gpios = { 351 .dev_id = "0-0021", 352 .table = { 353 GPIO_LOOKUP("sh7722_pfc", GPIO_PTT0, "powerdown", 354 GPIO_ACTIVE_HIGH), 355 GPIO_LOOKUP("sh7722_pfc", GPIO_PTT3, "reset", GPIO_ACTIVE_LOW), 356 }, 357 }; 358 359 static struct gpiod_lookup_table tw9910_gpios = { 360 .dev_id = "0-0045", 361 .table = { 362 GPIO_LOOKUP("sh7722_pfc", GPIO_PTT2, "pdn", GPIO_ACTIVE_LOW), 363 GPIO_LOOKUP("sh7722_pfc", GPIO_PTT3, "rstb", GPIO_ACTIVE_LOW), 364 }, 365 }; 366 367 /* Fixed 3.3V regulator to be used by SDHI0 */ 368 static struct regulator_consumer_supply fixed3v3_power_consumers[] = 369 { 370 REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"), 371 REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"), 372 }; 373 374 static struct resource sdhi_cn9_resources[] = { 375 [0] = { 376 .name = "SDHI", 377 .start = 0x04ce0000, 378 .end = 0x04ce00ff, 379 .flags = IORESOURCE_MEM, 380 }, 381 [1] = { 382 .start = evt2irq(0xe80), 383 .flags = IORESOURCE_IRQ, 384 }, 385 }; 386 387 static struct tmio_mmc_data sh7724_sdhi_data = { 388 .chan_priv_tx = (void *)SHDMA_SLAVE_SDHI0_TX, 389 .chan_priv_rx = (void *)SHDMA_SLAVE_SDHI0_RX, 390 .capabilities = MMC_CAP_SDIO_IRQ, 391 }; 392 393 static struct platform_device sdhi_cn9_device = { 394 .name = "sh_mobile_sdhi", 395 .num_resources = ARRAY_SIZE(sdhi_cn9_resources), 396 .resource = sdhi_cn9_resources, 397 .dev = { 398 .platform_data = &sh7724_sdhi_data, 399 }, 400 }; 401 402 static struct ov772x_camera_info ov7725_info = { 403 .flags = 0, 404 }; 405 406 static struct tw9910_video_info tw9910_info = { 407 .buswidth = 8, 408 .mpout = TW9910_MPO_FIELD, 409 }; 410 411 static struct i2c_board_info migor_i2c_devices[] = { 412 { 413 I2C_BOARD_INFO("rs5c372b", 0x32), 414 }, 415 { 416 I2C_BOARD_INFO("migor_ts", 0x51), 417 .irq = evt2irq(0x6c0), /* IRQ6 */ 418 }, 419 { 420 I2C_BOARD_INFO("wm8978", 0x1a), 421 }, 422 { 423 I2C_BOARD_INFO("ov772x", 0x21), 424 .platform_data = &ov7725_info, 425 }, 426 { 427 I2C_BOARD_INFO("tw9910", 0x45), 428 .platform_data = &tw9910_info, 429 }, 430 }; 431 432 static struct platform_device *migor_devices[] __initdata = { 433 &smc91x_eth_device, 434 &sh_keysc_device, 435 &migor_lcdc_device, 436 &migor_nor_flash_device, 437 &migor_nand_flash_device, 438 &sdhi_cn9_device, 439 }; 440 441 extern char migor_sdram_enter_start; 442 extern char migor_sdram_enter_end; 443 extern char migor_sdram_leave_start; 444 extern char migor_sdram_leave_end; 445 446 static int __init migor_devices_setup(void) 447 { 448 struct clk *video_clk; 449 450 /* register board specific self-refresh code */ 451 sh_mobile_register_self_refresh(SUSP_SH_STANDBY | SUSP_SH_SF, 452 &migor_sdram_enter_start, 453 &migor_sdram_enter_end, 454 &migor_sdram_leave_start, 455 &migor_sdram_leave_end); 456 457 regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers, 458 ARRAY_SIZE(fixed3v3_power_consumers), 3300000); 459 460 /* Let D11 LED show STATUS0 */ 461 gpio_request(GPIO_FN_STATUS0, NULL); 462 463 /* Lit D12 LED show PDSTATUS */ 464 gpio_request(GPIO_FN_PDSTATUS, NULL); 465 466 /* SMC91C111 - Enable IRQ0, Setup CS4 for 16-bit fast access */ 467 gpio_request(GPIO_FN_IRQ0, NULL); 468 __raw_writel(0x00003400, BSC_CS4BCR); 469 __raw_writel(0x00110080, BSC_CS4WCR); 470 471 /* KEYSC */ 472 gpio_request(GPIO_FN_KEYOUT0, NULL); 473 gpio_request(GPIO_FN_KEYOUT1, NULL); 474 gpio_request(GPIO_FN_KEYOUT2, NULL); 475 gpio_request(GPIO_FN_KEYOUT3, NULL); 476 gpio_request(GPIO_FN_KEYOUT4_IN6, NULL); 477 gpio_request(GPIO_FN_KEYIN1, NULL); 478 gpio_request(GPIO_FN_KEYIN2, NULL); 479 gpio_request(GPIO_FN_KEYIN3, NULL); 480 gpio_request(GPIO_FN_KEYIN4, NULL); 481 gpio_request(GPIO_FN_KEYOUT5_IN5, NULL); 482 483 /* NAND Flash */ 484 gpio_request(GPIO_FN_CS6A_CE2B, NULL); 485 __raw_writel((__raw_readl(BSC_CS6ABCR) & ~0x0600) | 0x0200, BSC_CS6ABCR); 486 gpio_request(GPIO_PTA1, NULL); 487 gpio_direction_input(GPIO_PTA1); 488 489 /* SDHI */ 490 gpio_request(GPIO_FN_SDHICD, NULL); 491 gpio_request(GPIO_FN_SDHIWP, NULL); 492 gpio_request(GPIO_FN_SDHID3, NULL); 493 gpio_request(GPIO_FN_SDHID2, NULL); 494 gpio_request(GPIO_FN_SDHID1, NULL); 495 gpio_request(GPIO_FN_SDHID0, NULL); 496 gpio_request(GPIO_FN_SDHICMD, NULL); 497 gpio_request(GPIO_FN_SDHICLK, NULL); 498 499 /* Touch Panel */ 500 gpio_request(GPIO_FN_IRQ6, NULL); 501 502 /* LCD Panel */ 503 #ifdef CONFIG_SH_MIGOR_QVGA /* LCDC - QVGA - Enable SYS Interface signals */ 504 gpio_request(GPIO_FN_LCDD17, NULL); 505 gpio_request(GPIO_FN_LCDD16, NULL); 506 gpio_request(GPIO_FN_LCDD15, NULL); 507 gpio_request(GPIO_FN_LCDD14, NULL); 508 gpio_request(GPIO_FN_LCDD13, NULL); 509 gpio_request(GPIO_FN_LCDD12, NULL); 510 gpio_request(GPIO_FN_LCDD11, NULL); 511 gpio_request(GPIO_FN_LCDD10, NULL); 512 gpio_request(GPIO_FN_LCDD8, NULL); 513 gpio_request(GPIO_FN_LCDD7, NULL); 514 gpio_request(GPIO_FN_LCDD6, NULL); 515 gpio_request(GPIO_FN_LCDD5, NULL); 516 gpio_request(GPIO_FN_LCDD4, NULL); 517 gpio_request(GPIO_FN_LCDD3, NULL); 518 gpio_request(GPIO_FN_LCDD2, NULL); 519 gpio_request(GPIO_FN_LCDD1, NULL); 520 gpio_request(GPIO_FN_LCDRS, NULL); 521 gpio_request(GPIO_FN_LCDCS, NULL); 522 gpio_request(GPIO_FN_LCDRD, NULL); 523 gpio_request(GPIO_FN_LCDWR, NULL); 524 gpio_request(GPIO_PTH2, NULL); /* LCD_DON */ 525 gpio_direction_output(GPIO_PTH2, 1); 526 #endif 527 #ifdef CONFIG_SH_MIGOR_RTA_WVGA /* LCDC - WVGA - Enable RGB Interface signals */ 528 gpio_request(GPIO_FN_LCDD15, NULL); 529 gpio_request(GPIO_FN_LCDD14, NULL); 530 gpio_request(GPIO_FN_LCDD13, NULL); 531 gpio_request(GPIO_FN_LCDD12, NULL); 532 gpio_request(GPIO_FN_LCDD11, NULL); 533 gpio_request(GPIO_FN_LCDD10, NULL); 534 gpio_request(GPIO_FN_LCDD9, NULL); 535 gpio_request(GPIO_FN_LCDD8, NULL); 536 gpio_request(GPIO_FN_LCDD7, NULL); 537 gpio_request(GPIO_FN_LCDD6, NULL); 538 gpio_request(GPIO_FN_LCDD5, NULL); 539 gpio_request(GPIO_FN_LCDD4, NULL); 540 gpio_request(GPIO_FN_LCDD3, NULL); 541 gpio_request(GPIO_FN_LCDD2, NULL); 542 gpio_request(GPIO_FN_LCDD1, NULL); 543 gpio_request(GPIO_FN_LCDD0, NULL); 544 gpio_request(GPIO_FN_LCDLCLK, NULL); 545 gpio_request(GPIO_FN_LCDDCK, NULL); 546 gpio_request(GPIO_FN_LCDVEPWC, NULL); 547 gpio_request(GPIO_FN_LCDVCPWC, NULL); 548 gpio_request(GPIO_FN_LCDVSYN, NULL); 549 gpio_request(GPIO_FN_LCDHSYN, NULL); 550 gpio_request(GPIO_FN_LCDDISP, NULL); 551 gpio_request(GPIO_FN_LCDDON, NULL); 552 #endif 553 554 /* CEU */ 555 gpio_request(GPIO_FN_VIO_CLK2, NULL); 556 gpio_request(GPIO_FN_VIO_VD2, NULL); 557 gpio_request(GPIO_FN_VIO_HD2, NULL); 558 gpio_request(GPIO_FN_VIO_FLD, NULL); 559 gpio_request(GPIO_FN_VIO_CKO, NULL); 560 gpio_request(GPIO_FN_VIO_D15, NULL); 561 gpio_request(GPIO_FN_VIO_D14, NULL); 562 gpio_request(GPIO_FN_VIO_D13, NULL); 563 gpio_request(GPIO_FN_VIO_D12, NULL); 564 gpio_request(GPIO_FN_VIO_D11, NULL); 565 gpio_request(GPIO_FN_VIO_D10, NULL); 566 gpio_request(GPIO_FN_VIO_D9, NULL); 567 gpio_request(GPIO_FN_VIO_D8, NULL); 568 569 __raw_writew(__raw_readw(PORT_MSELCRB) | 0x2000, PORT_MSELCRB); /* D15->D8 */ 570 571 /* SIU: Port B */ 572 gpio_request(GPIO_FN_SIUBOLR, NULL); 573 gpio_request(GPIO_FN_SIUBOBT, NULL); 574 gpio_request(GPIO_FN_SIUBISLD, NULL); 575 gpio_request(GPIO_FN_SIUBOSLD, NULL); 576 gpio_request(GPIO_FN_SIUMCKB, NULL); 577 578 /* 579 * The original driver sets SIUB OLR/OBT, ILR/IBT, and SIUA OLR/OBT to 580 * output. Need only SIUB, set to output for master mode (table 34.2) 581 */ 582 __raw_writew(__raw_readw(PORT_MSELCRA) | 1, PORT_MSELCRA); 583 584 /* 585 * Use 10 MHz VIO_CKO instead of 24 MHz to work around signal quality 586 * issues on Panel Board V2.1. 587 */ 588 video_clk = clk_get(NULL, "video_clk"); 589 if (!IS_ERR(video_clk)) { 590 clk_set_rate(video_clk, clk_round_rate(video_clk, 10000000)); 591 clk_put(video_clk); 592 } 593 594 /* Add a clock alias for ov7725 xclk source. */ 595 clk_add_alias(NULL, "0-0021", "video_clk", NULL); 596 597 /* Register GPIOs for video sources. */ 598 gpiod_add_lookup_table(&ov7725_gpios); 599 gpiod_add_lookup_table(&tw9910_gpios); 600 601 i2c_register_board_info(0, migor_i2c_devices, 602 ARRAY_SIZE(migor_i2c_devices)); 603 604 /* Initialize CEU platform device separately to map memory first */ 605 device_initialize(&migor_ceu_device.dev); 606 arch_setup_pdev_archdata(&migor_ceu_device); 607 dma_declare_coherent_memory(&migor_ceu_device.dev, 608 ceu_dma_membase, ceu_dma_membase, 609 ceu_dma_membase + CEU_BUFFER_MEMORY_SIZE - 1, 610 DMA_MEMORY_EXCLUSIVE); 611 612 platform_device_add(&migor_ceu_device); 613 614 return platform_add_devices(migor_devices, ARRAY_SIZE(migor_devices)); 615 } 616 arch_initcall(migor_devices_setup); 617 618 /* Return the board specific boot mode pin configuration */ 619 static int migor_mode_pins(void) 620 { 621 /* MD0=1, MD1=1, MD2=0: Clock Mode 3 622 * MD3=0: 16-bit Area0 Bus Width 623 * MD5=1: Little Endian 624 * TSTMD=1, MD8=0: Test Mode Disabled 625 */ 626 return MODE_PIN0 | MODE_PIN1 | MODE_PIN5; 627 } 628 629 /* Reserve a portion of memory for CEU buffers */ 630 static void __init migor_mv_mem_reserve(void) 631 { 632 phys_addr_t phys; 633 phys_addr_t size = CEU_BUFFER_MEMORY_SIZE; 634 635 phys = memblock_alloc_base(size, PAGE_SIZE, MEMBLOCK_ALLOC_ANYWHERE); 636 memblock_free(phys, size); 637 memblock_remove(phys, size); 638 639 ceu_dma_membase = phys; 640 } 641 642 /* 643 * The Machine Vector 644 */ 645 static struct sh_machine_vector mv_migor __initmv = { 646 .mv_name = "Migo-R", 647 .mv_mode_pins = migor_mode_pins, 648 .mv_mem_reserve = migor_mv_mem_reserve, 649 }; 650