1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * arch/sh/boards/superh/microdev/setup.c
4  *
5  * Copyright (C) 2003 Sean McGoogan (Sean.McGoogan@superh.com)
6  * Copyright (C) 2003, 2004 SuperH, Inc.
7  * Copyright (C) 2004, 2005 Paul Mundt
8  *
9  * SuperH SH4-202 MicroDev board support.
10  */
11 #include <linux/init.h>
12 #include <linux/platform_device.h>
13 #include <linux/ioport.h>
14 #include <video/s1d13xxxfb.h>
15 #include <mach/microdev.h>
16 #include <asm/io.h>
17 #include <asm/machvec.h>
18 #include <asm/sizes.h>
19 
20 static struct resource smc91x_resources[] = {
21 	[0] = {
22 		.start		= 0x300,
23 		.end		= 0x300 + SZ_4K - 1,
24 		.flags		= IORESOURCE_MEM,
25 	},
26 	[1] = {
27 		.start		= MICRODEV_LINUX_IRQ_ETHERNET,
28 		.end		= MICRODEV_LINUX_IRQ_ETHERNET,
29 		.flags		= IORESOURCE_IRQ,
30 	},
31 };
32 
33 static struct platform_device smc91x_device = {
34 	.name		= "smc91x",
35 	.id		= -1,
36 	.num_resources	= ARRAY_SIZE(smc91x_resources),
37 	.resource	= smc91x_resources,
38 };
39 
40 static struct s1d13xxxfb_regval s1d13806_initregs[] = {
41 	{ S1DREG_MISC,			0x00 },
42 	{ S1DREG_COM_DISP_MODE,		0x00 },
43 	{ S1DREG_GPIO_CNF0,		0x00 },
44 	{ S1DREG_GPIO_CNF1,		0x00 },
45 	{ S1DREG_GPIO_CTL0,		0x00 },
46 	{ S1DREG_GPIO_CTL1,		0x00 },
47 	{ S1DREG_CLK_CNF,		0x02 },
48 	{ S1DREG_LCD_CLK_CNF,		0x01 },
49 	{ S1DREG_CRT_CLK_CNF,		0x03 },
50 	{ S1DREG_MPLUG_CLK_CNF,		0x03 },
51 	{ S1DREG_CPU2MEM_WST_SEL,	0x02 },
52 	{ S1DREG_SDRAM_REF_RATE,	0x03 },
53 	{ S1DREG_SDRAM_TC0,		0x00 },
54 	{ S1DREG_SDRAM_TC1,		0x01 },
55 	{ S1DREG_MEM_CNF,		0x80 },
56 	{ S1DREG_PANEL_TYPE,		0x25 },
57 	{ S1DREG_MOD_RATE,		0x00 },
58 	{ S1DREG_LCD_DISP_HWIDTH,	0x63 },
59 	{ S1DREG_LCD_NDISP_HPER,	0x1e },
60 	{ S1DREG_TFT_FPLINE_START,	0x06 },
61 	{ S1DREG_TFT_FPLINE_PWIDTH,	0x03 },
62 	{ S1DREG_LCD_DISP_VHEIGHT0,	0x57 },
63 	{ S1DREG_LCD_DISP_VHEIGHT1,	0x02 },
64 	{ S1DREG_LCD_NDISP_VPER,	0x00 },
65 	{ S1DREG_TFT_FPFRAME_START,	0x0a },
66 	{ S1DREG_TFT_FPFRAME_PWIDTH,	0x81 },
67 	{ S1DREG_LCD_DISP_MODE,		0x03 },
68 	{ S1DREG_LCD_MISC,		0x00 },
69 	{ S1DREG_LCD_DISP_START0,	0x00 },
70 	{ S1DREG_LCD_DISP_START1,	0x00 },
71 	{ S1DREG_LCD_DISP_START2,	0x00 },
72 	{ S1DREG_LCD_MEM_OFF0,		0x90 },
73 	{ S1DREG_LCD_MEM_OFF1,		0x01 },
74 	{ S1DREG_LCD_PIX_PAN,		0x00 },
75 	{ S1DREG_LCD_DISP_FIFO_HTC,	0x00 },
76 	{ S1DREG_LCD_DISP_FIFO_LTC,	0x00 },
77 	{ S1DREG_CRT_DISP_HWIDTH,	0x63 },
78 	{ S1DREG_CRT_NDISP_HPER,	0x1f },
79 	{ S1DREG_CRT_HRTC_START,	0x04 },
80 	{ S1DREG_CRT_HRTC_PWIDTH,	0x8f },
81 	{ S1DREG_CRT_DISP_VHEIGHT0,	0x57 },
82 	{ S1DREG_CRT_DISP_VHEIGHT1,	0x02 },
83 	{ S1DREG_CRT_NDISP_VPER,	0x1b },
84 	{ S1DREG_CRT_VRTC_START,	0x00 },
85 	{ S1DREG_CRT_VRTC_PWIDTH,	0x83 },
86 	{ S1DREG_TV_OUT_CTL,		0x10 },
87 	{ S1DREG_CRT_DISP_MODE,		0x05 },
88 	{ S1DREG_CRT_DISP_START0,	0x00 },
89 	{ S1DREG_CRT_DISP_START1,	0x00 },
90 	{ S1DREG_CRT_DISP_START2,	0x00 },
91 	{ S1DREG_CRT_MEM_OFF0,		0x20 },
92 	{ S1DREG_CRT_MEM_OFF1,		0x03 },
93 	{ S1DREG_CRT_PIX_PAN,		0x00 },
94 	{ S1DREG_CRT_DISP_FIFO_HTC,	0x00 },
95 	{ S1DREG_CRT_DISP_FIFO_LTC,	0x00 },
96 	{ S1DREG_LCD_CUR_CTL,		0x00 },
97 	{ S1DREG_LCD_CUR_START,		0x01 },
98 	{ S1DREG_LCD_CUR_XPOS0,		0x00 },
99 	{ S1DREG_LCD_CUR_XPOS1,		0x00 },
100 	{ S1DREG_LCD_CUR_YPOS0,		0x00 },
101 	{ S1DREG_LCD_CUR_YPOS1,		0x00 },
102 	{ S1DREG_LCD_CUR_BCTL0,		0x00 },
103 	{ S1DREG_LCD_CUR_GCTL0,		0x00 },
104 	{ S1DREG_LCD_CUR_RCTL0,		0x00 },
105 	{ S1DREG_LCD_CUR_BCTL1,		0x1f },
106 	{ S1DREG_LCD_CUR_GCTL1,		0x3f },
107 	{ S1DREG_LCD_CUR_RCTL1,		0x1f },
108 	{ S1DREG_LCD_CUR_FIFO_HTC,	0x00 },
109 	{ S1DREG_CRT_CUR_CTL,		0x00 },
110 	{ S1DREG_CRT_CUR_START,		0x01 },
111 	{ S1DREG_CRT_CUR_XPOS0,		0x00 },
112 	{ S1DREG_CRT_CUR_XPOS1,		0x00 },
113 	{ S1DREG_CRT_CUR_YPOS0,		0x00 },
114 	{ S1DREG_CRT_CUR_YPOS1,		0x00 },
115 	{ S1DREG_CRT_CUR_BCTL0,		0x00 },
116 	{ S1DREG_CRT_CUR_GCTL0,		0x00 },
117 	{ S1DREG_CRT_CUR_RCTL0,		0x00 },
118 	{ S1DREG_CRT_CUR_BCTL1,		0x1f },
119 	{ S1DREG_CRT_CUR_GCTL1,		0x3f },
120 	{ S1DREG_CRT_CUR_RCTL1,		0x1f },
121 	{ S1DREG_CRT_CUR_FIFO_HTC,	0x00 },
122 	{ S1DREG_BBLT_CTL0,		0x00 },
123 	{ S1DREG_BBLT_CTL1,		0x00 },
124 	{ S1DREG_BBLT_CC_EXP,		0x00 },
125 	{ S1DREG_BBLT_OP,		0x00 },
126 	{ S1DREG_BBLT_SRC_START0,	0x00 },
127 	{ S1DREG_BBLT_SRC_START1,	0x00 },
128 	{ S1DREG_BBLT_SRC_START2,	0x00 },
129 	{ S1DREG_BBLT_DST_START0,	0x00 },
130 	{ S1DREG_BBLT_DST_START1,	0x00 },
131 	{ S1DREG_BBLT_DST_START2,	0x00 },
132 	{ S1DREG_BBLT_MEM_OFF0,		0x00 },
133 	{ S1DREG_BBLT_MEM_OFF1,		0x00 },
134 	{ S1DREG_BBLT_WIDTH0,		0x00 },
135 	{ S1DREG_BBLT_WIDTH1,		0x00 },
136 	{ S1DREG_BBLT_HEIGHT0,		0x00 },
137 	{ S1DREG_BBLT_HEIGHT1,		0x00 },
138 	{ S1DREG_BBLT_BGC0,		0x00 },
139 	{ S1DREG_BBLT_BGC1,		0x00 },
140 	{ S1DREG_BBLT_FGC0,		0x00 },
141 	{ S1DREG_BBLT_FGC1,		0x00 },
142 	{ S1DREG_LKUP_MODE,		0x00 },
143 	{ S1DREG_LKUP_ADDR,		0x00 },
144 	{ S1DREG_PS_CNF,		0x10 },
145 	{ S1DREG_PS_STATUS,		0x00 },
146 	{ S1DREG_CPU2MEM_WDOGT,		0x00 },
147 	{ S1DREG_COM_DISP_MODE,		0x02 },
148 };
149 
150 static struct s1d13xxxfb_pdata s1d13806_platform_data = {
151 	.initregs	= s1d13806_initregs,
152 	.initregssize	= ARRAY_SIZE(s1d13806_initregs),
153 };
154 
155 static struct resource s1d13806_resources[] = {
156 	[0] = {
157 		.start		= 0x07200000,
158 		.end		= 0x07200000 + SZ_2M - 1,
159 		.flags		= IORESOURCE_MEM,
160 	},
161 	[1] = {
162 		.start		= 0x07000000,
163 		.end		= 0x07000000 + SZ_2M - 1,
164 		.flags		= IORESOURCE_MEM,
165 	},
166 };
167 
168 static struct platform_device s1d13806_device = {
169 	.name		= "s1d13806fb",
170 	.id		= -1,
171 	.num_resources	= ARRAY_SIZE(s1d13806_resources),
172 	.resource	= s1d13806_resources,
173 
174 	.dev = {
175 		.platform_data	= &s1d13806_platform_data,
176 	},
177 };
178 
179 static struct platform_device *microdev_devices[] __initdata = {
180 	&smc91x_device,
181 	&s1d13806_device,
182 };
183 
184 static int __init microdev_devices_setup(void)
185 {
186 	return platform_add_devices(microdev_devices, ARRAY_SIZE(microdev_devices));
187 }
188 device_initcall(microdev_devices_setup);
189 
190 /*
191  * The Machine Vector
192  */
193 static struct sh_machine_vector mv_sh4202_microdev __initmv = {
194 	.mv_name		= "SH4-202 MicroDev",
195 	.mv_ioport_map		= microdev_ioport_map,
196 	.mv_init_irq		= init_microdev_irq,
197 };
198