1 /* 2 * Renesas - AP-325RXA 3 * (Compatible with Algo System ., LTD. - AP-320A) 4 * 5 * Copyright (C) 2008 Renesas Solutions Corp. 6 * Author : Yusuke Goda <goda.yuske@renesas.com> 7 * 8 * This file is subject to the terms and conditions of the GNU General Public 9 * License. See the file "COPYING" in the main directory of this archive 10 * for more details. 11 */ 12 13 #include <linux/init.h> 14 #include <linux/device.h> 15 #include <linux/interrupt.h> 16 #include <linux/platform_device.h> 17 #include <linux/mtd/physmap.h> 18 #include <linux/mtd/sh_flctl.h> 19 #include <linux/delay.h> 20 #include <linux/i2c.h> 21 #include <linux/smsc911x.h> 22 #include <linux/gpio.h> 23 #include <media/ov772x.h> 24 #include <media/soc_camera.h> 25 #include <media/soc_camera_platform.h> 26 #include <media/sh_mobile_ceu.h> 27 #include <video/sh_mobile_lcdc.h> 28 #include <asm/io.h> 29 #include <asm/clock.h> 30 #include <asm/suspend.h> 31 #include <cpu/sh7723.h> 32 33 static struct smsc911x_platform_config smsc911x_config = { 34 .phy_interface = PHY_INTERFACE_MODE_MII, 35 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, 36 .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN, 37 .flags = SMSC911X_USE_32BIT, 38 }; 39 40 static struct resource smsc9118_resources[] = { 41 [0] = { 42 .start = 0xb6080000, 43 .end = 0xb60fffff, 44 .flags = IORESOURCE_MEM, 45 }, 46 [1] = { 47 .start = 35, 48 .end = 35, 49 .flags = IORESOURCE_IRQ, 50 } 51 }; 52 53 static struct platform_device smsc9118_device = { 54 .name = "smsc911x", 55 .id = -1, 56 .num_resources = ARRAY_SIZE(smsc9118_resources), 57 .resource = smsc9118_resources, 58 .dev = { 59 .platform_data = &smsc911x_config, 60 }, 61 }; 62 63 /* 64 * AP320 and AP325RXA has CPLD data in NOR Flash(0xA80000-0xABFFFF). 65 * If this area erased, this board can not boot. 66 */ 67 static struct mtd_partition ap325rxa_nor_flash_partitions[] = { 68 { 69 .name = "uboot", 70 .offset = 0, 71 .size = (1 * 1024 * 1024), 72 .mask_flags = MTD_WRITEABLE, /* Read-only */ 73 }, { 74 .name = "kernel", 75 .offset = MTDPART_OFS_APPEND, 76 .size = (2 * 1024 * 1024), 77 }, { 78 .name = "free-area0", 79 .offset = MTDPART_OFS_APPEND, 80 .size = ((7 * 1024 * 1024) + (512 * 1024)), 81 }, { 82 .name = "CPLD-Data", 83 .offset = MTDPART_OFS_APPEND, 84 .mask_flags = MTD_WRITEABLE, /* Read-only */ 85 .size = (1024 * 128 * 2), 86 }, { 87 .name = "free-area1", 88 .offset = MTDPART_OFS_APPEND, 89 .size = MTDPART_SIZ_FULL, 90 }, 91 }; 92 93 static struct physmap_flash_data ap325rxa_nor_flash_data = { 94 .width = 2, 95 .parts = ap325rxa_nor_flash_partitions, 96 .nr_parts = ARRAY_SIZE(ap325rxa_nor_flash_partitions), 97 }; 98 99 static struct resource ap325rxa_nor_flash_resources[] = { 100 [0] = { 101 .name = "NOR Flash", 102 .start = 0x00000000, 103 .end = 0x00ffffff, 104 .flags = IORESOURCE_MEM, 105 } 106 }; 107 108 static struct platform_device ap325rxa_nor_flash_device = { 109 .name = "physmap-flash", 110 .resource = ap325rxa_nor_flash_resources, 111 .num_resources = ARRAY_SIZE(ap325rxa_nor_flash_resources), 112 .dev = { 113 .platform_data = &ap325rxa_nor_flash_data, 114 }, 115 }; 116 117 static struct mtd_partition nand_partition_info[] = { 118 { 119 .name = "nand_data", 120 .offset = 0, 121 .size = MTDPART_SIZ_FULL, 122 }, 123 }; 124 125 static struct resource nand_flash_resources[] = { 126 [0] = { 127 .start = 0xa4530000, 128 .end = 0xa45300ff, 129 .flags = IORESOURCE_MEM, 130 } 131 }; 132 133 static struct sh_flctl_platform_data nand_flash_data = { 134 .parts = nand_partition_info, 135 .nr_parts = ARRAY_SIZE(nand_partition_info), 136 .flcmncr_val = FCKSEL_E | TYPESEL_SET | NANWF_E, 137 .has_hwecc = 1, 138 }; 139 140 static struct platform_device nand_flash_device = { 141 .name = "sh_flctl", 142 .resource = nand_flash_resources, 143 .num_resources = ARRAY_SIZE(nand_flash_resources), 144 .dev = { 145 .platform_data = &nand_flash_data, 146 }, 147 }; 148 149 #define FPGA_LCDREG 0xB4100180 150 #define FPGA_BKLREG 0xB4100212 151 #define FPGA_LCDREG_VAL 0x0018 152 #define PORT_MSELCRB 0xA4050182 153 #define PORT_HIZCRC 0xA405015C 154 #define PORT_DRVCRA 0xA405018A 155 #define PORT_DRVCRB 0xA405018C 156 157 static void ap320_wvga_power_on(void *board_data, struct fb_info *info) 158 { 159 msleep(100); 160 161 /* ASD AP-320/325 LCD ON */ 162 __raw_writew(FPGA_LCDREG_VAL, FPGA_LCDREG); 163 164 /* backlight */ 165 gpio_set_value(GPIO_PTS3, 0); 166 __raw_writew(0x100, FPGA_BKLREG); 167 } 168 169 static void ap320_wvga_power_off(void *board_data) 170 { 171 /* backlight */ 172 __raw_writew(0, FPGA_BKLREG); 173 gpio_set_value(GPIO_PTS3, 1); 174 175 /* ASD AP-320/325 LCD OFF */ 176 __raw_writew(0, FPGA_LCDREG); 177 } 178 179 const static struct fb_videomode ap325rxa_lcdc_modes[] = { 180 { 181 .name = "LB070WV1", 182 .xres = 800, 183 .yres = 480, 184 .left_margin = 32, 185 .right_margin = 160, 186 .hsync_len = 8, 187 .upper_margin = 63, 188 .lower_margin = 80, 189 .vsync_len = 1, 190 .sync = 0, /* hsync and vsync are active low */ 191 }, 192 }; 193 194 static struct sh_mobile_lcdc_info lcdc_info = { 195 .clock_source = LCDC_CLK_EXTERNAL, 196 .ch[0] = { 197 .chan = LCDC_CHAN_MAINLCD, 198 .bpp = 16, 199 .interface_type = RGB18, 200 .clock_divider = 1, 201 .lcd_cfg = ap325rxa_lcdc_modes, 202 .num_cfg = ARRAY_SIZE(ap325rxa_lcdc_modes), 203 .lcd_size_cfg = { /* 7.0 inch */ 204 .width = 152, 205 .height = 91, 206 }, 207 .board_cfg = { 208 .display_on = ap320_wvga_power_on, 209 .display_off = ap320_wvga_power_off, 210 }, 211 } 212 }; 213 214 static struct resource lcdc_resources[] = { 215 [0] = { 216 .name = "LCDC", 217 .start = 0xfe940000, /* P4-only space */ 218 .end = 0xfe942fff, 219 .flags = IORESOURCE_MEM, 220 }, 221 [1] = { 222 .start = 28, 223 .flags = IORESOURCE_IRQ, 224 }, 225 }; 226 227 static struct platform_device lcdc_device = { 228 .name = "sh_mobile_lcdc_fb", 229 .num_resources = ARRAY_SIZE(lcdc_resources), 230 .resource = lcdc_resources, 231 .dev = { 232 .platform_data = &lcdc_info, 233 }, 234 .archdata = { 235 .hwblk_id = HWBLK_LCDC, 236 }, 237 }; 238 239 static void camera_power(int val) 240 { 241 gpio_set_value(GPIO_PTZ5, val); /* RST_CAM/RSTB */ 242 mdelay(10); 243 } 244 245 #ifdef CONFIG_I2C 246 /* support for the old ncm03j camera */ 247 static unsigned char camera_ncm03j_magic[] = 248 { 249 0x87, 0x00, 0x88, 0x08, 0x89, 0x01, 0x8A, 0xE8, 250 0x1D, 0x00, 0x1E, 0x8A, 0x21, 0x00, 0x33, 0x36, 251 0x36, 0x60, 0x37, 0x08, 0x3B, 0x31, 0x44, 0x0F, 252 0x46, 0xF0, 0x4B, 0x28, 0x4C, 0x21, 0x4D, 0x55, 253 0x4E, 0x1B, 0x4F, 0xC7, 0x50, 0xFC, 0x51, 0x12, 254 0x58, 0x02, 0x66, 0xC0, 0x67, 0x46, 0x6B, 0xA0, 255 0x6C, 0x34, 0x7E, 0x25, 0x7F, 0x25, 0x8D, 0x0F, 256 0x92, 0x40, 0x93, 0x04, 0x94, 0x26, 0x95, 0x0A, 257 0x99, 0x03, 0x9A, 0xF0, 0x9B, 0x14, 0x9D, 0x7A, 258 0xC5, 0x02, 0xD6, 0x07, 0x59, 0x00, 0x5A, 0x1A, 259 0x5B, 0x2A, 0x5C, 0x37, 0x5D, 0x42, 0x5E, 0x56, 260 0xC8, 0x00, 0xC9, 0x1A, 0xCA, 0x2A, 0xCB, 0x37, 261 0xCC, 0x42, 0xCD, 0x56, 0xCE, 0x00, 0xCF, 0x1A, 262 0xD0, 0x2A, 0xD1, 0x37, 0xD2, 0x42, 0xD3, 0x56, 263 0x5F, 0x68, 0x60, 0x87, 0x61, 0xA3, 0x62, 0xBC, 264 0x63, 0xD4, 0x64, 0xEA, 0xD6, 0x0F, 265 }; 266 267 static int camera_probe(void) 268 { 269 struct i2c_adapter *a = i2c_get_adapter(0); 270 struct i2c_msg msg; 271 int ret; 272 273 if (!a) 274 return -ENODEV; 275 276 camera_power(1); 277 msg.addr = 0x6e; 278 msg.buf = camera_ncm03j_magic; 279 msg.len = 2; 280 msg.flags = 0; 281 ret = i2c_transfer(a, &msg, 1); 282 camera_power(0); 283 284 return ret; 285 } 286 287 static int camera_set_capture(struct soc_camera_platform_info *info, 288 int enable) 289 { 290 struct i2c_adapter *a = i2c_get_adapter(0); 291 struct i2c_msg msg; 292 int ret = 0; 293 int i; 294 295 camera_power(0); 296 if (!enable) 297 return 0; /* no disable for now */ 298 299 camera_power(1); 300 for (i = 0; i < ARRAY_SIZE(camera_ncm03j_magic); i += 2) { 301 u_int8_t buf[8]; 302 303 msg.addr = 0x6e; 304 msg.buf = buf; 305 msg.len = 2; 306 msg.flags = 0; 307 308 buf[0] = camera_ncm03j_magic[i]; 309 buf[1] = camera_ncm03j_magic[i + 1]; 310 311 ret = (ret < 0) ? ret : i2c_transfer(a, &msg, 1); 312 } 313 314 return ret; 315 } 316 317 static int ap325rxa_camera_add(struct soc_camera_link *icl, struct device *dev); 318 static void ap325rxa_camera_del(struct soc_camera_link *icl); 319 320 static struct soc_camera_platform_info camera_info = { 321 .format_name = "UYVY", 322 .format_depth = 16, 323 .format = { 324 .code = V4L2_MBUS_FMT_UYVY8_2X8, 325 .colorspace = V4L2_COLORSPACE_SMPTE170M, 326 .field = V4L2_FIELD_NONE, 327 .width = 640, 328 .height = 480, 329 }, 330 .bus_param = SOCAM_PCLK_SAMPLE_RISING | SOCAM_HSYNC_ACTIVE_HIGH | 331 SOCAM_VSYNC_ACTIVE_HIGH | SOCAM_MASTER | SOCAM_DATAWIDTH_8 | 332 SOCAM_DATA_ACTIVE_HIGH, 333 .set_capture = camera_set_capture, 334 }; 335 336 static struct soc_camera_link camera_link = { 337 .bus_id = 0, 338 .add_device = ap325rxa_camera_add, 339 .del_device = ap325rxa_camera_del, 340 .module_name = "soc_camera_platform", 341 .priv = &camera_info, 342 }; 343 344 static void dummy_release(struct device *dev) 345 { 346 } 347 348 static struct platform_device camera_device = { 349 .name = "soc_camera_platform", 350 .dev = { 351 .platform_data = &camera_info, 352 .release = dummy_release, 353 }, 354 }; 355 356 static int ap325rxa_camera_add(struct soc_camera_link *icl, 357 struct device *dev) 358 { 359 if (icl != &camera_link || camera_probe() <= 0) 360 return -ENODEV; 361 362 camera_info.dev = dev; 363 364 return platform_device_register(&camera_device); 365 } 366 367 static void ap325rxa_camera_del(struct soc_camera_link *icl) 368 { 369 if (icl != &camera_link) 370 return; 371 372 platform_device_unregister(&camera_device); 373 memset(&camera_device.dev.kobj, 0, 374 sizeof(camera_device.dev.kobj)); 375 } 376 #endif /* CONFIG_I2C */ 377 378 static int ov7725_power(struct device *dev, int mode) 379 { 380 camera_power(0); 381 if (mode) 382 camera_power(1); 383 384 return 0; 385 } 386 387 static struct sh_mobile_ceu_info sh_mobile_ceu_info = { 388 .flags = SH_CEU_FLAG_USE_8BIT_BUS, 389 }; 390 391 static struct resource ceu_resources[] = { 392 [0] = { 393 .name = "CEU", 394 .start = 0xfe910000, 395 .end = 0xfe91009f, 396 .flags = IORESOURCE_MEM, 397 }, 398 [1] = { 399 .start = 52, 400 .flags = IORESOURCE_IRQ, 401 }, 402 [2] = { 403 /* place holder for contiguous memory */ 404 }, 405 }; 406 407 static struct platform_device ceu_device = { 408 .name = "sh_mobile_ceu", 409 .id = 0, /* "ceu0" clock */ 410 .num_resources = ARRAY_SIZE(ceu_resources), 411 .resource = ceu_resources, 412 .dev = { 413 .platform_data = &sh_mobile_ceu_info, 414 }, 415 .archdata = { 416 .hwblk_id = HWBLK_CEU, 417 }, 418 }; 419 420 static struct resource sdhi0_cn3_resources[] = { 421 [0] = { 422 .name = "SDHI0", 423 .start = 0x04ce0000, 424 .end = 0x04ce01ff, 425 .flags = IORESOURCE_MEM, 426 }, 427 [1] = { 428 .start = 100, 429 .flags = IORESOURCE_IRQ, 430 }, 431 }; 432 433 static struct platform_device sdhi0_cn3_device = { 434 .name = "sh_mobile_sdhi", 435 .id = 0, /* "sdhi0" clock */ 436 .num_resources = ARRAY_SIZE(sdhi0_cn3_resources), 437 .resource = sdhi0_cn3_resources, 438 .archdata = { 439 .hwblk_id = HWBLK_SDHI0, 440 }, 441 }; 442 443 static struct resource sdhi1_cn7_resources[] = { 444 [0] = { 445 .name = "SDHI1", 446 .start = 0x04cf0000, 447 .end = 0x04cf01ff, 448 .flags = IORESOURCE_MEM, 449 }, 450 [1] = { 451 .start = 23, 452 .flags = IORESOURCE_IRQ, 453 }, 454 }; 455 456 static struct platform_device sdhi1_cn7_device = { 457 .name = "sh_mobile_sdhi", 458 .id = 1, /* "sdhi1" clock */ 459 .num_resources = ARRAY_SIZE(sdhi1_cn7_resources), 460 .resource = sdhi1_cn7_resources, 461 .archdata = { 462 .hwblk_id = HWBLK_SDHI1, 463 }, 464 }; 465 466 static struct i2c_board_info __initdata ap325rxa_i2c_devices[] = { 467 { 468 I2C_BOARD_INFO("pcf8563", 0x51), 469 }, 470 }; 471 472 static struct i2c_board_info ap325rxa_i2c_camera[] = { 473 { 474 I2C_BOARD_INFO("ov772x", 0x21), 475 }, 476 }; 477 478 static struct ov772x_camera_info ov7725_info = { 479 .flags = OV772X_FLAG_VFLIP | OV772X_FLAG_HFLIP | \ 480 OV772X_FLAG_8BIT, 481 .edgectrl = OV772X_AUTO_EDGECTRL(0xf, 0), 482 }; 483 484 static struct soc_camera_link ov7725_link = { 485 .bus_id = 0, 486 .power = ov7725_power, 487 .board_info = &ap325rxa_i2c_camera[0], 488 .i2c_adapter_id = 0, 489 .priv = &ov7725_info, 490 }; 491 492 static struct platform_device ap325rxa_camera[] = { 493 { 494 .name = "soc-camera-pdrv", 495 .id = 0, 496 .dev = { 497 .platform_data = &ov7725_link, 498 }, 499 }, { 500 .name = "soc-camera-pdrv", 501 .id = 1, 502 .dev = { 503 .platform_data = &camera_link, 504 }, 505 }, 506 }; 507 508 static struct platform_device *ap325rxa_devices[] __initdata = { 509 &smsc9118_device, 510 &ap325rxa_nor_flash_device, 511 &lcdc_device, 512 &ceu_device, 513 &nand_flash_device, 514 &sdhi0_cn3_device, 515 &sdhi1_cn7_device, 516 &ap325rxa_camera[0], 517 &ap325rxa_camera[1], 518 }; 519 520 extern char ap325rxa_sdram_enter_start; 521 extern char ap325rxa_sdram_enter_end; 522 extern char ap325rxa_sdram_leave_start; 523 extern char ap325rxa_sdram_leave_end; 524 525 static int __init ap325rxa_devices_setup(void) 526 { 527 /* register board specific self-refresh code */ 528 sh_mobile_register_self_refresh(SUSP_SH_STANDBY | SUSP_SH_SF, 529 &ap325rxa_sdram_enter_start, 530 &ap325rxa_sdram_enter_end, 531 &ap325rxa_sdram_leave_start, 532 &ap325rxa_sdram_leave_end); 533 534 /* LD3 and LD4 LEDs */ 535 gpio_request(GPIO_PTX5, NULL); /* RUN */ 536 gpio_direction_output(GPIO_PTX5, 1); 537 gpio_export(GPIO_PTX5, 0); 538 539 gpio_request(GPIO_PTX4, NULL); /* INDICATOR */ 540 gpio_direction_output(GPIO_PTX4, 0); 541 gpio_export(GPIO_PTX4, 0); 542 543 /* SW1 input */ 544 gpio_request(GPIO_PTF7, NULL); /* MODE */ 545 gpio_direction_input(GPIO_PTF7); 546 gpio_export(GPIO_PTF7, 0); 547 548 /* LCDC */ 549 gpio_request(GPIO_FN_LCDD15, NULL); 550 gpio_request(GPIO_FN_LCDD14, NULL); 551 gpio_request(GPIO_FN_LCDD13, NULL); 552 gpio_request(GPIO_FN_LCDD12, NULL); 553 gpio_request(GPIO_FN_LCDD11, NULL); 554 gpio_request(GPIO_FN_LCDD10, NULL); 555 gpio_request(GPIO_FN_LCDD9, NULL); 556 gpio_request(GPIO_FN_LCDD8, NULL); 557 gpio_request(GPIO_FN_LCDD7, NULL); 558 gpio_request(GPIO_FN_LCDD6, NULL); 559 gpio_request(GPIO_FN_LCDD5, NULL); 560 gpio_request(GPIO_FN_LCDD4, NULL); 561 gpio_request(GPIO_FN_LCDD3, NULL); 562 gpio_request(GPIO_FN_LCDD2, NULL); 563 gpio_request(GPIO_FN_LCDD1, NULL); 564 gpio_request(GPIO_FN_LCDD0, NULL); 565 gpio_request(GPIO_FN_LCDLCLK_PTR, NULL); 566 gpio_request(GPIO_FN_LCDDCK, NULL); 567 gpio_request(GPIO_FN_LCDVEPWC, NULL); 568 gpio_request(GPIO_FN_LCDVCPWC, NULL); 569 gpio_request(GPIO_FN_LCDVSYN, NULL); 570 gpio_request(GPIO_FN_LCDHSYN, NULL); 571 gpio_request(GPIO_FN_LCDDISP, NULL); 572 gpio_request(GPIO_FN_LCDDON, NULL); 573 574 /* LCD backlight */ 575 gpio_request(GPIO_PTS3, NULL); 576 gpio_direction_output(GPIO_PTS3, 1); 577 578 /* CEU */ 579 gpio_request(GPIO_FN_VIO_CLK2, NULL); 580 gpio_request(GPIO_FN_VIO_VD2, NULL); 581 gpio_request(GPIO_FN_VIO_HD2, NULL); 582 gpio_request(GPIO_FN_VIO_FLD, NULL); 583 gpio_request(GPIO_FN_VIO_CKO, NULL); 584 gpio_request(GPIO_FN_VIO_D15, NULL); 585 gpio_request(GPIO_FN_VIO_D14, NULL); 586 gpio_request(GPIO_FN_VIO_D13, NULL); 587 gpio_request(GPIO_FN_VIO_D12, NULL); 588 gpio_request(GPIO_FN_VIO_D11, NULL); 589 gpio_request(GPIO_FN_VIO_D10, NULL); 590 gpio_request(GPIO_FN_VIO_D9, NULL); 591 gpio_request(GPIO_FN_VIO_D8, NULL); 592 593 gpio_request(GPIO_PTZ7, NULL); 594 gpio_direction_output(GPIO_PTZ7, 0); /* OE_CAM */ 595 gpio_request(GPIO_PTZ6, NULL); 596 gpio_direction_output(GPIO_PTZ6, 0); /* STBY_CAM */ 597 gpio_request(GPIO_PTZ5, NULL); 598 gpio_direction_output(GPIO_PTZ5, 0); /* RST_CAM */ 599 gpio_request(GPIO_PTZ4, NULL); 600 gpio_direction_output(GPIO_PTZ4, 0); /* SADDR */ 601 602 __raw_writew(__raw_readw(PORT_MSELCRB) & ~0x0001, PORT_MSELCRB); 603 604 /* FLCTL */ 605 gpio_request(GPIO_FN_FCE, NULL); 606 gpio_request(GPIO_FN_NAF7, NULL); 607 gpio_request(GPIO_FN_NAF6, NULL); 608 gpio_request(GPIO_FN_NAF5, NULL); 609 gpio_request(GPIO_FN_NAF4, NULL); 610 gpio_request(GPIO_FN_NAF3, NULL); 611 gpio_request(GPIO_FN_NAF2, NULL); 612 gpio_request(GPIO_FN_NAF1, NULL); 613 gpio_request(GPIO_FN_NAF0, NULL); 614 gpio_request(GPIO_FN_FCDE, NULL); 615 gpio_request(GPIO_FN_FOE, NULL); 616 gpio_request(GPIO_FN_FSC, NULL); 617 gpio_request(GPIO_FN_FWE, NULL); 618 gpio_request(GPIO_FN_FRB, NULL); 619 620 __raw_writew(0, PORT_HIZCRC); 621 __raw_writew(0xFFFF, PORT_DRVCRA); 622 __raw_writew(0xFFFF, PORT_DRVCRB); 623 624 platform_resource_setup_memory(&ceu_device, "ceu", 4 << 20); 625 626 /* SDHI0 - CN3 - SD CARD */ 627 gpio_request(GPIO_FN_SDHI0CD_PTD, NULL); 628 gpio_request(GPIO_FN_SDHI0WP_PTD, NULL); 629 gpio_request(GPIO_FN_SDHI0D3_PTD, NULL); 630 gpio_request(GPIO_FN_SDHI0D2_PTD, NULL); 631 gpio_request(GPIO_FN_SDHI0D1_PTD, NULL); 632 gpio_request(GPIO_FN_SDHI0D0_PTD, NULL); 633 gpio_request(GPIO_FN_SDHI0CMD_PTD, NULL); 634 gpio_request(GPIO_FN_SDHI0CLK_PTD, NULL); 635 636 /* SDHI1 - CN7 - MICRO SD CARD */ 637 gpio_request(GPIO_FN_SDHI1CD, NULL); 638 gpio_request(GPIO_FN_SDHI1D3, NULL); 639 gpio_request(GPIO_FN_SDHI1D2, NULL); 640 gpio_request(GPIO_FN_SDHI1D1, NULL); 641 gpio_request(GPIO_FN_SDHI1D0, NULL); 642 gpio_request(GPIO_FN_SDHI1CMD, NULL); 643 gpio_request(GPIO_FN_SDHI1CLK, NULL); 644 645 i2c_register_board_info(0, ap325rxa_i2c_devices, 646 ARRAY_SIZE(ap325rxa_i2c_devices)); 647 648 return platform_add_devices(ap325rxa_devices, 649 ARRAY_SIZE(ap325rxa_devices)); 650 } 651 arch_initcall(ap325rxa_devices_setup); 652 653 /* Return the board specific boot mode pin configuration */ 654 static int ap325rxa_mode_pins(void) 655 { 656 /* MD0=0, MD1=0, MD2=0: Clock Mode 0 657 * MD3=0: 16-bit Area0 Bus Width 658 * MD5=1: Little Endian 659 * TSTMD=1, MD8=1: Test Mode Disabled 660 */ 661 return MODE_PIN5 | MODE_PIN8; 662 } 663 664 static struct sh_machine_vector mv_ap325rxa __initmv = { 665 .mv_name = "AP-325RXA", 666 .mv_mode_pins = ap325rxa_mode_pins, 667 }; 668