1 /* 2 * Renesas - AP-325RXA 3 * (Compatible with Algo System ., LTD. - AP-320A) 4 * 5 * Copyright (C) 2008 Renesas Solutions Corp. 6 * Author : Yusuke Goda <goda.yuske@renesas.com> 7 * 8 * This file is subject to the terms and conditions of the GNU General Public 9 * License. See the file "COPYING" in the main directory of this archive 10 * for more details. 11 */ 12 13 #include <linux/init.h> 14 #include <linux/device.h> 15 #include <linux/interrupt.h> 16 #include <linux/platform_device.h> 17 #include <linux/mfd/sh_mobile_sdhi.h> 18 #include <linux/mmc/host.h> 19 #include <linux/mtd/physmap.h> 20 #include <linux/mtd/sh_flctl.h> 21 #include <linux/delay.h> 22 #include <linux/i2c.h> 23 #include <linux/smsc911x.h> 24 #include <linux/gpio.h> 25 #include <media/ov772x.h> 26 #include <media/soc_camera.h> 27 #include <media/soc_camera_platform.h> 28 #include <media/sh_mobile_ceu.h> 29 #include <video/sh_mobile_lcdc.h> 30 #include <asm/io.h> 31 #include <asm/clock.h> 32 #include <asm/suspend.h> 33 #include <cpu/sh7723.h> 34 35 static struct smsc911x_platform_config smsc911x_config = { 36 .phy_interface = PHY_INTERFACE_MODE_MII, 37 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, 38 .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN, 39 .flags = SMSC911X_USE_32BIT, 40 }; 41 42 static struct resource smsc9118_resources[] = { 43 [0] = { 44 .start = 0xb6080000, 45 .end = 0xb60fffff, 46 .flags = IORESOURCE_MEM, 47 }, 48 [1] = { 49 .start = 35, 50 .end = 35, 51 .flags = IORESOURCE_IRQ, 52 } 53 }; 54 55 static struct platform_device smsc9118_device = { 56 .name = "smsc911x", 57 .id = -1, 58 .num_resources = ARRAY_SIZE(smsc9118_resources), 59 .resource = smsc9118_resources, 60 .dev = { 61 .platform_data = &smsc911x_config, 62 }, 63 }; 64 65 /* 66 * AP320 and AP325RXA has CPLD data in NOR Flash(0xA80000-0xABFFFF). 67 * If this area erased, this board can not boot. 68 */ 69 static struct mtd_partition ap325rxa_nor_flash_partitions[] = { 70 { 71 .name = "uboot", 72 .offset = 0, 73 .size = (1 * 1024 * 1024), 74 .mask_flags = MTD_WRITEABLE, /* Read-only */ 75 }, { 76 .name = "kernel", 77 .offset = MTDPART_OFS_APPEND, 78 .size = (2 * 1024 * 1024), 79 }, { 80 .name = "free-area0", 81 .offset = MTDPART_OFS_APPEND, 82 .size = ((7 * 1024 * 1024) + (512 * 1024)), 83 }, { 84 .name = "CPLD-Data", 85 .offset = MTDPART_OFS_APPEND, 86 .mask_flags = MTD_WRITEABLE, /* Read-only */ 87 .size = (1024 * 128 * 2), 88 }, { 89 .name = "free-area1", 90 .offset = MTDPART_OFS_APPEND, 91 .size = MTDPART_SIZ_FULL, 92 }, 93 }; 94 95 static struct physmap_flash_data ap325rxa_nor_flash_data = { 96 .width = 2, 97 .parts = ap325rxa_nor_flash_partitions, 98 .nr_parts = ARRAY_SIZE(ap325rxa_nor_flash_partitions), 99 }; 100 101 static struct resource ap325rxa_nor_flash_resources[] = { 102 [0] = { 103 .name = "NOR Flash", 104 .start = 0x00000000, 105 .end = 0x00ffffff, 106 .flags = IORESOURCE_MEM, 107 } 108 }; 109 110 static struct platform_device ap325rxa_nor_flash_device = { 111 .name = "physmap-flash", 112 .resource = ap325rxa_nor_flash_resources, 113 .num_resources = ARRAY_SIZE(ap325rxa_nor_flash_resources), 114 .dev = { 115 .platform_data = &ap325rxa_nor_flash_data, 116 }, 117 }; 118 119 static struct mtd_partition nand_partition_info[] = { 120 { 121 .name = "nand_data", 122 .offset = 0, 123 .size = MTDPART_SIZ_FULL, 124 }, 125 }; 126 127 static struct resource nand_flash_resources[] = { 128 [0] = { 129 .start = 0xa4530000, 130 .end = 0xa45300ff, 131 .flags = IORESOURCE_MEM, 132 } 133 }; 134 135 static struct sh_flctl_platform_data nand_flash_data = { 136 .parts = nand_partition_info, 137 .nr_parts = ARRAY_SIZE(nand_partition_info), 138 .flcmncr_val = FCKSEL_E | TYPESEL_SET | NANWF_E, 139 .has_hwecc = 1, 140 }; 141 142 static struct platform_device nand_flash_device = { 143 .name = "sh_flctl", 144 .resource = nand_flash_resources, 145 .num_resources = ARRAY_SIZE(nand_flash_resources), 146 .dev = { 147 .platform_data = &nand_flash_data, 148 }, 149 }; 150 151 #define FPGA_LCDREG 0xB4100180 152 #define FPGA_BKLREG 0xB4100212 153 #define FPGA_LCDREG_VAL 0x0018 154 #define PORT_MSELCRB 0xA4050182 155 #define PORT_HIZCRC 0xA405015C 156 #define PORT_DRVCRA 0xA405018A 157 #define PORT_DRVCRB 0xA405018C 158 159 static void ap320_wvga_power_on(void *board_data, struct fb_info *info) 160 { 161 msleep(100); 162 163 /* ASD AP-320/325 LCD ON */ 164 __raw_writew(FPGA_LCDREG_VAL, FPGA_LCDREG); 165 166 /* backlight */ 167 gpio_set_value(GPIO_PTS3, 0); 168 __raw_writew(0x100, FPGA_BKLREG); 169 } 170 171 static void ap320_wvga_power_off(void *board_data) 172 { 173 /* backlight */ 174 __raw_writew(0, FPGA_BKLREG); 175 gpio_set_value(GPIO_PTS3, 1); 176 177 /* ASD AP-320/325 LCD OFF */ 178 __raw_writew(0, FPGA_LCDREG); 179 } 180 181 const static struct fb_videomode ap325rxa_lcdc_modes[] = { 182 { 183 .name = "LB070WV1", 184 .xres = 800, 185 .yres = 480, 186 .left_margin = 32, 187 .right_margin = 160, 188 .hsync_len = 8, 189 .upper_margin = 63, 190 .lower_margin = 80, 191 .vsync_len = 1, 192 .sync = 0, /* hsync and vsync are active low */ 193 }, 194 }; 195 196 static struct sh_mobile_lcdc_info lcdc_info = { 197 .clock_source = LCDC_CLK_EXTERNAL, 198 .ch[0] = { 199 .chan = LCDC_CHAN_MAINLCD, 200 .bpp = 16, 201 .interface_type = RGB18, 202 .clock_divider = 1, 203 .lcd_cfg = ap325rxa_lcdc_modes, 204 .num_cfg = ARRAY_SIZE(ap325rxa_lcdc_modes), 205 .lcd_size_cfg = { /* 7.0 inch */ 206 .width = 152, 207 .height = 91, 208 }, 209 .board_cfg = { 210 .display_on = ap320_wvga_power_on, 211 .display_off = ap320_wvga_power_off, 212 }, 213 } 214 }; 215 216 static struct resource lcdc_resources[] = { 217 [0] = { 218 .name = "LCDC", 219 .start = 0xfe940000, /* P4-only space */ 220 .end = 0xfe942fff, 221 .flags = IORESOURCE_MEM, 222 }, 223 [1] = { 224 .start = 28, 225 .flags = IORESOURCE_IRQ, 226 }, 227 }; 228 229 static struct platform_device lcdc_device = { 230 .name = "sh_mobile_lcdc_fb", 231 .num_resources = ARRAY_SIZE(lcdc_resources), 232 .resource = lcdc_resources, 233 .dev = { 234 .platform_data = &lcdc_info, 235 }, 236 .archdata = { 237 .hwblk_id = HWBLK_LCDC, 238 }, 239 }; 240 241 static void camera_power(int val) 242 { 243 gpio_set_value(GPIO_PTZ5, val); /* RST_CAM/RSTB */ 244 mdelay(10); 245 } 246 247 #ifdef CONFIG_I2C 248 /* support for the old ncm03j camera */ 249 static unsigned char camera_ncm03j_magic[] = 250 { 251 0x87, 0x00, 0x88, 0x08, 0x89, 0x01, 0x8A, 0xE8, 252 0x1D, 0x00, 0x1E, 0x8A, 0x21, 0x00, 0x33, 0x36, 253 0x36, 0x60, 0x37, 0x08, 0x3B, 0x31, 0x44, 0x0F, 254 0x46, 0xF0, 0x4B, 0x28, 0x4C, 0x21, 0x4D, 0x55, 255 0x4E, 0x1B, 0x4F, 0xC7, 0x50, 0xFC, 0x51, 0x12, 256 0x58, 0x02, 0x66, 0xC0, 0x67, 0x46, 0x6B, 0xA0, 257 0x6C, 0x34, 0x7E, 0x25, 0x7F, 0x25, 0x8D, 0x0F, 258 0x92, 0x40, 0x93, 0x04, 0x94, 0x26, 0x95, 0x0A, 259 0x99, 0x03, 0x9A, 0xF0, 0x9B, 0x14, 0x9D, 0x7A, 260 0xC5, 0x02, 0xD6, 0x07, 0x59, 0x00, 0x5A, 0x1A, 261 0x5B, 0x2A, 0x5C, 0x37, 0x5D, 0x42, 0x5E, 0x56, 262 0xC8, 0x00, 0xC9, 0x1A, 0xCA, 0x2A, 0xCB, 0x37, 263 0xCC, 0x42, 0xCD, 0x56, 0xCE, 0x00, 0xCF, 0x1A, 264 0xD0, 0x2A, 0xD1, 0x37, 0xD2, 0x42, 0xD3, 0x56, 265 0x5F, 0x68, 0x60, 0x87, 0x61, 0xA3, 0x62, 0xBC, 266 0x63, 0xD4, 0x64, 0xEA, 0xD6, 0x0F, 267 }; 268 269 static int camera_probe(void) 270 { 271 struct i2c_adapter *a = i2c_get_adapter(0); 272 struct i2c_msg msg; 273 int ret; 274 275 if (!a) 276 return -ENODEV; 277 278 camera_power(1); 279 msg.addr = 0x6e; 280 msg.buf = camera_ncm03j_magic; 281 msg.len = 2; 282 msg.flags = 0; 283 ret = i2c_transfer(a, &msg, 1); 284 camera_power(0); 285 286 return ret; 287 } 288 289 static int camera_set_capture(struct soc_camera_platform_info *info, 290 int enable) 291 { 292 struct i2c_adapter *a = i2c_get_adapter(0); 293 struct i2c_msg msg; 294 int ret = 0; 295 int i; 296 297 camera_power(0); 298 if (!enable) 299 return 0; /* no disable for now */ 300 301 camera_power(1); 302 for (i = 0; i < ARRAY_SIZE(camera_ncm03j_magic); i += 2) { 303 u_int8_t buf[8]; 304 305 msg.addr = 0x6e; 306 msg.buf = buf; 307 msg.len = 2; 308 msg.flags = 0; 309 310 buf[0] = camera_ncm03j_magic[i]; 311 buf[1] = camera_ncm03j_magic[i + 1]; 312 313 ret = (ret < 0) ? ret : i2c_transfer(a, &msg, 1); 314 } 315 316 return ret; 317 } 318 319 static int ap325rxa_camera_add(struct soc_camera_link *icl, struct device *dev); 320 static void ap325rxa_camera_del(struct soc_camera_link *icl); 321 322 static struct soc_camera_platform_info camera_info = { 323 .format_name = "UYVY", 324 .format_depth = 16, 325 .format = { 326 .code = V4L2_MBUS_FMT_UYVY8_2X8, 327 .colorspace = V4L2_COLORSPACE_SMPTE170M, 328 .field = V4L2_FIELD_NONE, 329 .width = 640, 330 .height = 480, 331 }, 332 .bus_param = SOCAM_PCLK_SAMPLE_RISING | SOCAM_HSYNC_ACTIVE_HIGH | 333 SOCAM_VSYNC_ACTIVE_HIGH | SOCAM_MASTER | SOCAM_DATAWIDTH_8 | 334 SOCAM_DATA_ACTIVE_HIGH, 335 .set_capture = camera_set_capture, 336 }; 337 338 static struct soc_camera_link camera_link = { 339 .bus_id = 0, 340 .add_device = ap325rxa_camera_add, 341 .del_device = ap325rxa_camera_del, 342 .module_name = "soc_camera_platform", 343 .priv = &camera_info, 344 }; 345 346 static void dummy_release(struct device *dev) 347 { 348 } 349 350 static struct platform_device camera_device = { 351 .name = "soc_camera_platform", 352 .dev = { 353 .platform_data = &camera_info, 354 .release = dummy_release, 355 }, 356 }; 357 358 static int ap325rxa_camera_add(struct soc_camera_link *icl, 359 struct device *dev) 360 { 361 if (icl != &camera_link || camera_probe() <= 0) 362 return -ENODEV; 363 364 camera_info.dev = dev; 365 366 return platform_device_register(&camera_device); 367 } 368 369 static void ap325rxa_camera_del(struct soc_camera_link *icl) 370 { 371 if (icl != &camera_link) 372 return; 373 374 platform_device_unregister(&camera_device); 375 memset(&camera_device.dev.kobj, 0, 376 sizeof(camera_device.dev.kobj)); 377 } 378 #endif /* CONFIG_I2C */ 379 380 static int ov7725_power(struct device *dev, int mode) 381 { 382 camera_power(0); 383 if (mode) 384 camera_power(1); 385 386 return 0; 387 } 388 389 static struct sh_mobile_ceu_info sh_mobile_ceu_info = { 390 .flags = SH_CEU_FLAG_USE_8BIT_BUS, 391 }; 392 393 static struct resource ceu_resources[] = { 394 [0] = { 395 .name = "CEU", 396 .start = 0xfe910000, 397 .end = 0xfe91009f, 398 .flags = IORESOURCE_MEM, 399 }, 400 [1] = { 401 .start = 52, 402 .flags = IORESOURCE_IRQ, 403 }, 404 [2] = { 405 /* place holder for contiguous memory */ 406 }, 407 }; 408 409 static struct platform_device ceu_device = { 410 .name = "sh_mobile_ceu", 411 .id = 0, /* "ceu0" clock */ 412 .num_resources = ARRAY_SIZE(ceu_resources), 413 .resource = ceu_resources, 414 .dev = { 415 .platform_data = &sh_mobile_ceu_info, 416 }, 417 .archdata = { 418 .hwblk_id = HWBLK_CEU, 419 }, 420 }; 421 422 static struct resource sdhi0_cn3_resources[] = { 423 [0] = { 424 .name = "SDHI0", 425 .start = 0x04ce0000, 426 .end = 0x04ce01ff, 427 .flags = IORESOURCE_MEM, 428 }, 429 [1] = { 430 .start = 100, 431 .flags = IORESOURCE_IRQ, 432 }, 433 }; 434 435 static struct sh_mobile_sdhi_info sdhi0_cn3_data = { 436 .tmio_caps = MMC_CAP_SDIO_IRQ, 437 }; 438 439 static struct platform_device sdhi0_cn3_device = { 440 .name = "sh_mobile_sdhi", 441 .id = 0, /* "sdhi0" clock */ 442 .num_resources = ARRAY_SIZE(sdhi0_cn3_resources), 443 .resource = sdhi0_cn3_resources, 444 .dev = { 445 .platform_data = &sdhi0_cn3_data, 446 }, 447 .archdata = { 448 .hwblk_id = HWBLK_SDHI0, 449 }, 450 }; 451 452 static struct resource sdhi1_cn7_resources[] = { 453 [0] = { 454 .name = "SDHI1", 455 .start = 0x04cf0000, 456 .end = 0x04cf01ff, 457 .flags = IORESOURCE_MEM, 458 }, 459 [1] = { 460 .start = 23, 461 .flags = IORESOURCE_IRQ, 462 }, 463 }; 464 465 static struct sh_mobile_sdhi_info sdhi1_cn7_data = { 466 .tmio_caps = MMC_CAP_SDIO_IRQ, 467 }; 468 469 static struct platform_device sdhi1_cn7_device = { 470 .name = "sh_mobile_sdhi", 471 .id = 1, /* "sdhi1" clock */ 472 .num_resources = ARRAY_SIZE(sdhi1_cn7_resources), 473 .resource = sdhi1_cn7_resources, 474 .dev = { 475 .platform_data = &sdhi1_cn7_data, 476 }, 477 .archdata = { 478 .hwblk_id = HWBLK_SDHI1, 479 }, 480 }; 481 482 static struct i2c_board_info __initdata ap325rxa_i2c_devices[] = { 483 { 484 I2C_BOARD_INFO("pcf8563", 0x51), 485 }, 486 }; 487 488 static struct i2c_board_info ap325rxa_i2c_camera[] = { 489 { 490 I2C_BOARD_INFO("ov772x", 0x21), 491 }, 492 }; 493 494 static struct ov772x_camera_info ov7725_info = { 495 .flags = OV772X_FLAG_VFLIP | OV772X_FLAG_HFLIP | \ 496 OV772X_FLAG_8BIT, 497 .edgectrl = OV772X_AUTO_EDGECTRL(0xf, 0), 498 }; 499 500 static struct soc_camera_link ov7725_link = { 501 .bus_id = 0, 502 .power = ov7725_power, 503 .board_info = &ap325rxa_i2c_camera[0], 504 .i2c_adapter_id = 0, 505 .priv = &ov7725_info, 506 }; 507 508 static struct platform_device ap325rxa_camera[] = { 509 { 510 .name = "soc-camera-pdrv", 511 .id = 0, 512 .dev = { 513 .platform_data = &ov7725_link, 514 }, 515 }, { 516 .name = "soc-camera-pdrv", 517 .id = 1, 518 .dev = { 519 .platform_data = &camera_link, 520 }, 521 }, 522 }; 523 524 static struct platform_device *ap325rxa_devices[] __initdata = { 525 &smsc9118_device, 526 &ap325rxa_nor_flash_device, 527 &lcdc_device, 528 &ceu_device, 529 &nand_flash_device, 530 &sdhi0_cn3_device, 531 &sdhi1_cn7_device, 532 &ap325rxa_camera[0], 533 &ap325rxa_camera[1], 534 }; 535 536 extern char ap325rxa_sdram_enter_start; 537 extern char ap325rxa_sdram_enter_end; 538 extern char ap325rxa_sdram_leave_start; 539 extern char ap325rxa_sdram_leave_end; 540 541 static int __init ap325rxa_devices_setup(void) 542 { 543 /* register board specific self-refresh code */ 544 sh_mobile_register_self_refresh(SUSP_SH_STANDBY | SUSP_SH_SF, 545 &ap325rxa_sdram_enter_start, 546 &ap325rxa_sdram_enter_end, 547 &ap325rxa_sdram_leave_start, 548 &ap325rxa_sdram_leave_end); 549 550 /* LD3 and LD4 LEDs */ 551 gpio_request(GPIO_PTX5, NULL); /* RUN */ 552 gpio_direction_output(GPIO_PTX5, 1); 553 gpio_export(GPIO_PTX5, 0); 554 555 gpio_request(GPIO_PTX4, NULL); /* INDICATOR */ 556 gpio_direction_output(GPIO_PTX4, 0); 557 gpio_export(GPIO_PTX4, 0); 558 559 /* SW1 input */ 560 gpio_request(GPIO_PTF7, NULL); /* MODE */ 561 gpio_direction_input(GPIO_PTF7); 562 gpio_export(GPIO_PTF7, 0); 563 564 /* LCDC */ 565 gpio_request(GPIO_FN_LCDD15, NULL); 566 gpio_request(GPIO_FN_LCDD14, NULL); 567 gpio_request(GPIO_FN_LCDD13, NULL); 568 gpio_request(GPIO_FN_LCDD12, NULL); 569 gpio_request(GPIO_FN_LCDD11, NULL); 570 gpio_request(GPIO_FN_LCDD10, NULL); 571 gpio_request(GPIO_FN_LCDD9, NULL); 572 gpio_request(GPIO_FN_LCDD8, NULL); 573 gpio_request(GPIO_FN_LCDD7, NULL); 574 gpio_request(GPIO_FN_LCDD6, NULL); 575 gpio_request(GPIO_FN_LCDD5, NULL); 576 gpio_request(GPIO_FN_LCDD4, NULL); 577 gpio_request(GPIO_FN_LCDD3, NULL); 578 gpio_request(GPIO_FN_LCDD2, NULL); 579 gpio_request(GPIO_FN_LCDD1, NULL); 580 gpio_request(GPIO_FN_LCDD0, NULL); 581 gpio_request(GPIO_FN_LCDLCLK_PTR, NULL); 582 gpio_request(GPIO_FN_LCDDCK, NULL); 583 gpio_request(GPIO_FN_LCDVEPWC, NULL); 584 gpio_request(GPIO_FN_LCDVCPWC, NULL); 585 gpio_request(GPIO_FN_LCDVSYN, NULL); 586 gpio_request(GPIO_FN_LCDHSYN, NULL); 587 gpio_request(GPIO_FN_LCDDISP, NULL); 588 gpio_request(GPIO_FN_LCDDON, NULL); 589 590 /* LCD backlight */ 591 gpio_request(GPIO_PTS3, NULL); 592 gpio_direction_output(GPIO_PTS3, 1); 593 594 /* CEU */ 595 gpio_request(GPIO_FN_VIO_CLK2, NULL); 596 gpio_request(GPIO_FN_VIO_VD2, NULL); 597 gpio_request(GPIO_FN_VIO_HD2, NULL); 598 gpio_request(GPIO_FN_VIO_FLD, NULL); 599 gpio_request(GPIO_FN_VIO_CKO, NULL); 600 gpio_request(GPIO_FN_VIO_D15, NULL); 601 gpio_request(GPIO_FN_VIO_D14, NULL); 602 gpio_request(GPIO_FN_VIO_D13, NULL); 603 gpio_request(GPIO_FN_VIO_D12, NULL); 604 gpio_request(GPIO_FN_VIO_D11, NULL); 605 gpio_request(GPIO_FN_VIO_D10, NULL); 606 gpio_request(GPIO_FN_VIO_D9, NULL); 607 gpio_request(GPIO_FN_VIO_D8, NULL); 608 609 gpio_request(GPIO_PTZ7, NULL); 610 gpio_direction_output(GPIO_PTZ7, 0); /* OE_CAM */ 611 gpio_request(GPIO_PTZ6, NULL); 612 gpio_direction_output(GPIO_PTZ6, 0); /* STBY_CAM */ 613 gpio_request(GPIO_PTZ5, NULL); 614 gpio_direction_output(GPIO_PTZ5, 0); /* RST_CAM */ 615 gpio_request(GPIO_PTZ4, NULL); 616 gpio_direction_output(GPIO_PTZ4, 0); /* SADDR */ 617 618 __raw_writew(__raw_readw(PORT_MSELCRB) & ~0x0001, PORT_MSELCRB); 619 620 /* FLCTL */ 621 gpio_request(GPIO_FN_FCE, NULL); 622 gpio_request(GPIO_FN_NAF7, NULL); 623 gpio_request(GPIO_FN_NAF6, NULL); 624 gpio_request(GPIO_FN_NAF5, NULL); 625 gpio_request(GPIO_FN_NAF4, NULL); 626 gpio_request(GPIO_FN_NAF3, NULL); 627 gpio_request(GPIO_FN_NAF2, NULL); 628 gpio_request(GPIO_FN_NAF1, NULL); 629 gpio_request(GPIO_FN_NAF0, NULL); 630 gpio_request(GPIO_FN_FCDE, NULL); 631 gpio_request(GPIO_FN_FOE, NULL); 632 gpio_request(GPIO_FN_FSC, NULL); 633 gpio_request(GPIO_FN_FWE, NULL); 634 gpio_request(GPIO_FN_FRB, NULL); 635 636 __raw_writew(0, PORT_HIZCRC); 637 __raw_writew(0xFFFF, PORT_DRVCRA); 638 __raw_writew(0xFFFF, PORT_DRVCRB); 639 640 platform_resource_setup_memory(&ceu_device, "ceu", 4 << 20); 641 642 /* SDHI0 - CN3 - SD CARD */ 643 gpio_request(GPIO_FN_SDHI0CD_PTD, NULL); 644 gpio_request(GPIO_FN_SDHI0WP_PTD, NULL); 645 gpio_request(GPIO_FN_SDHI0D3_PTD, NULL); 646 gpio_request(GPIO_FN_SDHI0D2_PTD, NULL); 647 gpio_request(GPIO_FN_SDHI0D1_PTD, NULL); 648 gpio_request(GPIO_FN_SDHI0D0_PTD, NULL); 649 gpio_request(GPIO_FN_SDHI0CMD_PTD, NULL); 650 gpio_request(GPIO_FN_SDHI0CLK_PTD, NULL); 651 652 /* SDHI1 - CN7 - MICRO SD CARD */ 653 gpio_request(GPIO_FN_SDHI1CD, NULL); 654 gpio_request(GPIO_FN_SDHI1D3, NULL); 655 gpio_request(GPIO_FN_SDHI1D2, NULL); 656 gpio_request(GPIO_FN_SDHI1D1, NULL); 657 gpio_request(GPIO_FN_SDHI1D0, NULL); 658 gpio_request(GPIO_FN_SDHI1CMD, NULL); 659 gpio_request(GPIO_FN_SDHI1CLK, NULL); 660 661 i2c_register_board_info(0, ap325rxa_i2c_devices, 662 ARRAY_SIZE(ap325rxa_i2c_devices)); 663 664 return platform_add_devices(ap325rxa_devices, 665 ARRAY_SIZE(ap325rxa_devices)); 666 } 667 arch_initcall(ap325rxa_devices_setup); 668 669 /* Return the board specific boot mode pin configuration */ 670 static int ap325rxa_mode_pins(void) 671 { 672 /* MD0=0, MD1=0, MD2=0: Clock Mode 0 673 * MD3=0: 16-bit Area0 Bus Width 674 * MD5=1: Little Endian 675 * TSTMD=1, MD8=1: Test Mode Disabled 676 */ 677 return MODE_PIN5 | MODE_PIN8; 678 } 679 680 static struct sh_machine_vector mv_ap325rxa __initmv = { 681 .mv_name = "AP-325RXA", 682 .mv_mode_pins = ap325rxa_mode_pins, 683 }; 684