1 /* 2 * Renesas - AP-325RXA 3 * (Compatible with Algo System ., LTD. - AP-320A) 4 * 5 * Copyright (C) 2008 Renesas Solutions Corp. 6 * Author : Yusuke Goda <goda.yuske@renesas.com> 7 * 8 * This file is subject to the terms and conditions of the GNU General Public 9 * License. See the file "COPYING" in the main directory of this archive 10 * for more details. 11 */ 12 13 #include <linux/init.h> 14 #include <linux/device.h> 15 #include <linux/interrupt.h> 16 #include <linux/platform_device.h> 17 #include <linux/mmc/host.h> 18 #include <linux/mmc/sh_mobile_sdhi.h> 19 #include <linux/mtd/physmap.h> 20 #include <linux/mtd/sh_flctl.h> 21 #include <linux/delay.h> 22 #include <linux/i2c.h> 23 #include <linux/smsc911x.h> 24 #include <linux/gpio.h> 25 #include <linux/videodev2.h> 26 #include <media/ov772x.h> 27 #include <media/soc_camera.h> 28 #include <media/soc_camera_platform.h> 29 #include <media/sh_mobile_ceu.h> 30 #include <video/sh_mobile_lcdc.h> 31 #include <asm/io.h> 32 #include <asm/clock.h> 33 #include <asm/suspend.h> 34 #include <cpu/sh7723.h> 35 36 static struct smsc911x_platform_config smsc911x_config = { 37 .phy_interface = PHY_INTERFACE_MODE_MII, 38 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, 39 .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN, 40 .flags = SMSC911X_USE_32BIT, 41 }; 42 43 static struct resource smsc9118_resources[] = { 44 [0] = { 45 .start = 0xb6080000, 46 .end = 0xb60fffff, 47 .flags = IORESOURCE_MEM, 48 }, 49 [1] = { 50 .start = 35, 51 .end = 35, 52 .flags = IORESOURCE_IRQ, 53 } 54 }; 55 56 static struct platform_device smsc9118_device = { 57 .name = "smsc911x", 58 .id = -1, 59 .num_resources = ARRAY_SIZE(smsc9118_resources), 60 .resource = smsc9118_resources, 61 .dev = { 62 .platform_data = &smsc911x_config, 63 }, 64 }; 65 66 /* 67 * AP320 and AP325RXA has CPLD data in NOR Flash(0xA80000-0xABFFFF). 68 * If this area erased, this board can not boot. 69 */ 70 static struct mtd_partition ap325rxa_nor_flash_partitions[] = { 71 { 72 .name = "uboot", 73 .offset = 0, 74 .size = (1 * 1024 * 1024), 75 .mask_flags = MTD_WRITEABLE, /* Read-only */ 76 }, { 77 .name = "kernel", 78 .offset = MTDPART_OFS_APPEND, 79 .size = (2 * 1024 * 1024), 80 }, { 81 .name = "free-area0", 82 .offset = MTDPART_OFS_APPEND, 83 .size = ((7 * 1024 * 1024) + (512 * 1024)), 84 }, { 85 .name = "CPLD-Data", 86 .offset = MTDPART_OFS_APPEND, 87 .mask_flags = MTD_WRITEABLE, /* Read-only */ 88 .size = (1024 * 128 * 2), 89 }, { 90 .name = "free-area1", 91 .offset = MTDPART_OFS_APPEND, 92 .size = MTDPART_SIZ_FULL, 93 }, 94 }; 95 96 static struct physmap_flash_data ap325rxa_nor_flash_data = { 97 .width = 2, 98 .parts = ap325rxa_nor_flash_partitions, 99 .nr_parts = ARRAY_SIZE(ap325rxa_nor_flash_partitions), 100 }; 101 102 static struct resource ap325rxa_nor_flash_resources[] = { 103 [0] = { 104 .name = "NOR Flash", 105 .start = 0x00000000, 106 .end = 0x00ffffff, 107 .flags = IORESOURCE_MEM, 108 } 109 }; 110 111 static struct platform_device ap325rxa_nor_flash_device = { 112 .name = "physmap-flash", 113 .resource = ap325rxa_nor_flash_resources, 114 .num_resources = ARRAY_SIZE(ap325rxa_nor_flash_resources), 115 .dev = { 116 .platform_data = &ap325rxa_nor_flash_data, 117 }, 118 }; 119 120 static struct mtd_partition nand_partition_info[] = { 121 { 122 .name = "nand_data", 123 .offset = 0, 124 .size = MTDPART_SIZ_FULL, 125 }, 126 }; 127 128 static struct resource nand_flash_resources[] = { 129 [0] = { 130 .start = 0xa4530000, 131 .end = 0xa45300ff, 132 .flags = IORESOURCE_MEM, 133 } 134 }; 135 136 static struct sh_flctl_platform_data nand_flash_data = { 137 .parts = nand_partition_info, 138 .nr_parts = ARRAY_SIZE(nand_partition_info), 139 .flcmncr_val = FCKSEL_E | TYPESEL_SET | NANWF_E, 140 .has_hwecc = 1, 141 }; 142 143 static struct platform_device nand_flash_device = { 144 .name = "sh_flctl", 145 .resource = nand_flash_resources, 146 .num_resources = ARRAY_SIZE(nand_flash_resources), 147 .dev = { 148 .platform_data = &nand_flash_data, 149 }, 150 }; 151 152 #define FPGA_LCDREG 0xB4100180 153 #define FPGA_BKLREG 0xB4100212 154 #define FPGA_LCDREG_VAL 0x0018 155 #define PORT_MSELCRB 0xA4050182 156 #define PORT_HIZCRC 0xA405015C 157 #define PORT_DRVCRA 0xA405018A 158 #define PORT_DRVCRB 0xA405018C 159 160 static int ap320_wvga_set_brightness(int brightness) 161 { 162 if (brightness) { 163 gpio_set_value(GPIO_PTS3, 0); 164 __raw_writew(0x100, FPGA_BKLREG); 165 } else { 166 __raw_writew(0, FPGA_BKLREG); 167 gpio_set_value(GPIO_PTS3, 1); 168 } 169 170 return 0; 171 } 172 173 static int ap320_wvga_get_brightness(void) 174 { 175 return gpio_get_value(GPIO_PTS3); 176 } 177 178 static void ap320_wvga_power_on(void) 179 { 180 msleep(100); 181 182 /* ASD AP-320/325 LCD ON */ 183 __raw_writew(FPGA_LCDREG_VAL, FPGA_LCDREG); 184 } 185 186 static void ap320_wvga_power_off(void) 187 { 188 /* ASD AP-320/325 LCD OFF */ 189 __raw_writew(0, FPGA_LCDREG); 190 } 191 192 static const struct fb_videomode ap325rxa_lcdc_modes[] = { 193 { 194 .name = "LB070WV1", 195 .xres = 800, 196 .yres = 480, 197 .left_margin = 32, 198 .right_margin = 160, 199 .hsync_len = 8, 200 .upper_margin = 63, 201 .lower_margin = 80, 202 .vsync_len = 1, 203 .sync = 0, /* hsync and vsync are active low */ 204 }, 205 }; 206 207 static struct sh_mobile_lcdc_info lcdc_info = { 208 .clock_source = LCDC_CLK_EXTERNAL, 209 .ch[0] = { 210 .chan = LCDC_CHAN_MAINLCD, 211 .fourcc = V4L2_PIX_FMT_RGB565, 212 .interface_type = RGB18, 213 .clock_divider = 1, 214 .lcd_cfg = ap325rxa_lcdc_modes, 215 .num_cfg = ARRAY_SIZE(ap325rxa_lcdc_modes), 216 .lcd_size_cfg = { /* 7.0 inch */ 217 .width = 152, 218 .height = 91, 219 }, 220 .board_cfg = { 221 .display_on = ap320_wvga_power_on, 222 .display_off = ap320_wvga_power_off, 223 .set_brightness = ap320_wvga_set_brightness, 224 .get_brightness = ap320_wvga_get_brightness, 225 }, 226 .bl_info = { 227 .name = "sh_mobile_lcdc_bl", 228 .max_brightness = 1, 229 }, 230 } 231 }; 232 233 static struct resource lcdc_resources[] = { 234 [0] = { 235 .name = "LCDC", 236 .start = 0xfe940000, /* P4-only space */ 237 .end = 0xfe942fff, 238 .flags = IORESOURCE_MEM, 239 }, 240 [1] = { 241 .start = 28, 242 .flags = IORESOURCE_IRQ, 243 }, 244 }; 245 246 static struct platform_device lcdc_device = { 247 .name = "sh_mobile_lcdc_fb", 248 .num_resources = ARRAY_SIZE(lcdc_resources), 249 .resource = lcdc_resources, 250 .dev = { 251 .platform_data = &lcdc_info, 252 }, 253 }; 254 255 static void camera_power(int val) 256 { 257 gpio_set_value(GPIO_PTZ5, val); /* RST_CAM/RSTB */ 258 mdelay(10); 259 } 260 261 #ifdef CONFIG_I2C 262 /* support for the old ncm03j camera */ 263 static unsigned char camera_ncm03j_magic[] = 264 { 265 0x87, 0x00, 0x88, 0x08, 0x89, 0x01, 0x8A, 0xE8, 266 0x1D, 0x00, 0x1E, 0x8A, 0x21, 0x00, 0x33, 0x36, 267 0x36, 0x60, 0x37, 0x08, 0x3B, 0x31, 0x44, 0x0F, 268 0x46, 0xF0, 0x4B, 0x28, 0x4C, 0x21, 0x4D, 0x55, 269 0x4E, 0x1B, 0x4F, 0xC7, 0x50, 0xFC, 0x51, 0x12, 270 0x58, 0x02, 0x66, 0xC0, 0x67, 0x46, 0x6B, 0xA0, 271 0x6C, 0x34, 0x7E, 0x25, 0x7F, 0x25, 0x8D, 0x0F, 272 0x92, 0x40, 0x93, 0x04, 0x94, 0x26, 0x95, 0x0A, 273 0x99, 0x03, 0x9A, 0xF0, 0x9B, 0x14, 0x9D, 0x7A, 274 0xC5, 0x02, 0xD6, 0x07, 0x59, 0x00, 0x5A, 0x1A, 275 0x5B, 0x2A, 0x5C, 0x37, 0x5D, 0x42, 0x5E, 0x56, 276 0xC8, 0x00, 0xC9, 0x1A, 0xCA, 0x2A, 0xCB, 0x37, 277 0xCC, 0x42, 0xCD, 0x56, 0xCE, 0x00, 0xCF, 0x1A, 278 0xD0, 0x2A, 0xD1, 0x37, 0xD2, 0x42, 0xD3, 0x56, 279 0x5F, 0x68, 0x60, 0x87, 0x61, 0xA3, 0x62, 0xBC, 280 0x63, 0xD4, 0x64, 0xEA, 0xD6, 0x0F, 281 }; 282 283 static int camera_probe(void) 284 { 285 struct i2c_adapter *a = i2c_get_adapter(0); 286 struct i2c_msg msg; 287 int ret; 288 289 if (!a) 290 return -ENODEV; 291 292 camera_power(1); 293 msg.addr = 0x6e; 294 msg.buf = camera_ncm03j_magic; 295 msg.len = 2; 296 msg.flags = 0; 297 ret = i2c_transfer(a, &msg, 1); 298 camera_power(0); 299 300 return ret; 301 } 302 303 static int camera_set_capture(struct soc_camera_platform_info *info, 304 int enable) 305 { 306 struct i2c_adapter *a = i2c_get_adapter(0); 307 struct i2c_msg msg; 308 int ret = 0; 309 int i; 310 311 camera_power(0); 312 if (!enable) 313 return 0; /* no disable for now */ 314 315 camera_power(1); 316 for (i = 0; i < ARRAY_SIZE(camera_ncm03j_magic); i += 2) { 317 u_int8_t buf[8]; 318 319 msg.addr = 0x6e; 320 msg.buf = buf; 321 msg.len = 2; 322 msg.flags = 0; 323 324 buf[0] = camera_ncm03j_magic[i]; 325 buf[1] = camera_ncm03j_magic[i + 1]; 326 327 ret = (ret < 0) ? ret : i2c_transfer(a, &msg, 1); 328 } 329 330 return ret; 331 } 332 333 static int ap325rxa_camera_add(struct soc_camera_device *icd); 334 static void ap325rxa_camera_del(struct soc_camera_device *icd); 335 336 static struct soc_camera_platform_info camera_info = { 337 .format_name = "UYVY", 338 .format_depth = 16, 339 .format = { 340 .code = V4L2_MBUS_FMT_UYVY8_2X8, 341 .colorspace = V4L2_COLORSPACE_SMPTE170M, 342 .field = V4L2_FIELD_NONE, 343 .width = 640, 344 .height = 480, 345 }, 346 .mbus_param = V4L2_MBUS_PCLK_SAMPLE_RISING | V4L2_MBUS_MASTER | 347 V4L2_MBUS_VSYNC_ACTIVE_HIGH | V4L2_MBUS_HSYNC_ACTIVE_HIGH | 348 V4L2_MBUS_DATA_ACTIVE_HIGH, 349 .mbus_type = V4L2_MBUS_PARALLEL, 350 .set_capture = camera_set_capture, 351 }; 352 353 static struct soc_camera_link camera_link = { 354 .bus_id = 0, 355 .add_device = ap325rxa_camera_add, 356 .del_device = ap325rxa_camera_del, 357 .module_name = "soc_camera_platform", 358 .priv = &camera_info, 359 }; 360 361 static struct platform_device *camera_device; 362 363 static void ap325rxa_camera_release(struct device *dev) 364 { 365 soc_camera_platform_release(&camera_device); 366 } 367 368 static int ap325rxa_camera_add(struct soc_camera_device *icd) 369 { 370 int ret = soc_camera_platform_add(icd, &camera_device, &camera_link, 371 ap325rxa_camera_release, 0); 372 if (ret < 0) 373 return ret; 374 375 ret = camera_probe(); 376 if (ret < 0) 377 soc_camera_platform_del(icd, camera_device, &camera_link); 378 379 return ret; 380 } 381 382 static void ap325rxa_camera_del(struct soc_camera_device *icd) 383 { 384 soc_camera_platform_del(icd, camera_device, &camera_link); 385 } 386 #endif /* CONFIG_I2C */ 387 388 static int ov7725_power(struct device *dev, int mode) 389 { 390 camera_power(0); 391 if (mode) 392 camera_power(1); 393 394 return 0; 395 } 396 397 static struct sh_mobile_ceu_info sh_mobile_ceu_info = { 398 .flags = SH_CEU_FLAG_USE_8BIT_BUS, 399 }; 400 401 static struct resource ceu_resources[] = { 402 [0] = { 403 .name = "CEU", 404 .start = 0xfe910000, 405 .end = 0xfe91009f, 406 .flags = IORESOURCE_MEM, 407 }, 408 [1] = { 409 .start = 52, 410 .flags = IORESOURCE_IRQ, 411 }, 412 [2] = { 413 /* place holder for contiguous memory */ 414 }, 415 }; 416 417 static struct platform_device ceu_device = { 418 .name = "sh_mobile_ceu", 419 .id = 0, /* "ceu0" clock */ 420 .num_resources = ARRAY_SIZE(ceu_resources), 421 .resource = ceu_resources, 422 .dev = { 423 .platform_data = &sh_mobile_ceu_info, 424 }, 425 }; 426 427 static struct resource sdhi0_cn3_resources[] = { 428 [0] = { 429 .name = "SDHI0", 430 .start = 0x04ce0000, 431 .end = 0x04ce00ff, 432 .flags = IORESOURCE_MEM, 433 }, 434 [1] = { 435 .start = 100, 436 .flags = IORESOURCE_IRQ, 437 }, 438 }; 439 440 static struct sh_mobile_sdhi_info sdhi0_cn3_data = { 441 .tmio_caps = MMC_CAP_SDIO_IRQ, 442 }; 443 444 static struct platform_device sdhi0_cn3_device = { 445 .name = "sh_mobile_sdhi", 446 .id = 0, /* "sdhi0" clock */ 447 .num_resources = ARRAY_SIZE(sdhi0_cn3_resources), 448 .resource = sdhi0_cn3_resources, 449 .dev = { 450 .platform_data = &sdhi0_cn3_data, 451 }, 452 }; 453 454 static struct resource sdhi1_cn7_resources[] = { 455 [0] = { 456 .name = "SDHI1", 457 .start = 0x04cf0000, 458 .end = 0x04cf00ff, 459 .flags = IORESOURCE_MEM, 460 }, 461 [1] = { 462 .start = 23, 463 .flags = IORESOURCE_IRQ, 464 }, 465 }; 466 467 static struct sh_mobile_sdhi_info sdhi1_cn7_data = { 468 .tmio_caps = MMC_CAP_SDIO_IRQ, 469 }; 470 471 static struct platform_device sdhi1_cn7_device = { 472 .name = "sh_mobile_sdhi", 473 .id = 1, /* "sdhi1" clock */ 474 .num_resources = ARRAY_SIZE(sdhi1_cn7_resources), 475 .resource = sdhi1_cn7_resources, 476 .dev = { 477 .platform_data = &sdhi1_cn7_data, 478 }, 479 }; 480 481 static struct i2c_board_info __initdata ap325rxa_i2c_devices[] = { 482 { 483 I2C_BOARD_INFO("pcf8563", 0x51), 484 }, 485 }; 486 487 static struct i2c_board_info ap325rxa_i2c_camera[] = { 488 { 489 I2C_BOARD_INFO("ov772x", 0x21), 490 }, 491 }; 492 493 static struct ov772x_camera_info ov7725_info = { 494 .flags = OV772X_FLAG_VFLIP | OV772X_FLAG_HFLIP, 495 .edgectrl = OV772X_AUTO_EDGECTRL(0xf, 0), 496 }; 497 498 static struct soc_camera_link ov7725_link = { 499 .bus_id = 0, 500 .power = ov7725_power, 501 .board_info = &ap325rxa_i2c_camera[0], 502 .i2c_adapter_id = 0, 503 .priv = &ov7725_info, 504 }; 505 506 static struct platform_device ap325rxa_camera[] = { 507 { 508 .name = "soc-camera-pdrv", 509 .id = 0, 510 .dev = { 511 .platform_data = &ov7725_link, 512 }, 513 }, { 514 .name = "soc-camera-pdrv", 515 .id = 1, 516 .dev = { 517 .platform_data = &camera_link, 518 }, 519 }, 520 }; 521 522 static struct platform_device *ap325rxa_devices[] __initdata = { 523 &smsc9118_device, 524 &ap325rxa_nor_flash_device, 525 &lcdc_device, 526 &ceu_device, 527 &nand_flash_device, 528 &sdhi0_cn3_device, 529 &sdhi1_cn7_device, 530 &ap325rxa_camera[0], 531 &ap325rxa_camera[1], 532 }; 533 534 extern char ap325rxa_sdram_enter_start; 535 extern char ap325rxa_sdram_enter_end; 536 extern char ap325rxa_sdram_leave_start; 537 extern char ap325rxa_sdram_leave_end; 538 539 static int __init ap325rxa_devices_setup(void) 540 { 541 /* register board specific self-refresh code */ 542 sh_mobile_register_self_refresh(SUSP_SH_STANDBY | SUSP_SH_SF, 543 &ap325rxa_sdram_enter_start, 544 &ap325rxa_sdram_enter_end, 545 &ap325rxa_sdram_leave_start, 546 &ap325rxa_sdram_leave_end); 547 548 /* LD3 and LD4 LEDs */ 549 gpio_request(GPIO_PTX5, NULL); /* RUN */ 550 gpio_direction_output(GPIO_PTX5, 1); 551 gpio_export(GPIO_PTX5, 0); 552 553 gpio_request(GPIO_PTX4, NULL); /* INDICATOR */ 554 gpio_direction_output(GPIO_PTX4, 0); 555 gpio_export(GPIO_PTX4, 0); 556 557 /* SW1 input */ 558 gpio_request(GPIO_PTF7, NULL); /* MODE */ 559 gpio_direction_input(GPIO_PTF7); 560 gpio_export(GPIO_PTF7, 0); 561 562 /* LCDC */ 563 gpio_request(GPIO_FN_LCDD15, NULL); 564 gpio_request(GPIO_FN_LCDD14, NULL); 565 gpio_request(GPIO_FN_LCDD13, NULL); 566 gpio_request(GPIO_FN_LCDD12, NULL); 567 gpio_request(GPIO_FN_LCDD11, NULL); 568 gpio_request(GPIO_FN_LCDD10, NULL); 569 gpio_request(GPIO_FN_LCDD9, NULL); 570 gpio_request(GPIO_FN_LCDD8, NULL); 571 gpio_request(GPIO_FN_LCDD7, NULL); 572 gpio_request(GPIO_FN_LCDD6, NULL); 573 gpio_request(GPIO_FN_LCDD5, NULL); 574 gpio_request(GPIO_FN_LCDD4, NULL); 575 gpio_request(GPIO_FN_LCDD3, NULL); 576 gpio_request(GPIO_FN_LCDD2, NULL); 577 gpio_request(GPIO_FN_LCDD1, NULL); 578 gpio_request(GPIO_FN_LCDD0, NULL); 579 gpio_request(GPIO_FN_LCDLCLK_PTR, NULL); 580 gpio_request(GPIO_FN_LCDDCK, NULL); 581 gpio_request(GPIO_FN_LCDVEPWC, NULL); 582 gpio_request(GPIO_FN_LCDVCPWC, NULL); 583 gpio_request(GPIO_FN_LCDVSYN, NULL); 584 gpio_request(GPIO_FN_LCDHSYN, NULL); 585 gpio_request(GPIO_FN_LCDDISP, NULL); 586 gpio_request(GPIO_FN_LCDDON, NULL); 587 588 /* LCD backlight */ 589 gpio_request(GPIO_PTS3, NULL); 590 gpio_direction_output(GPIO_PTS3, 1); 591 592 /* CEU */ 593 gpio_request(GPIO_FN_VIO_CLK2, NULL); 594 gpio_request(GPIO_FN_VIO_VD2, NULL); 595 gpio_request(GPIO_FN_VIO_HD2, NULL); 596 gpio_request(GPIO_FN_VIO_FLD, NULL); 597 gpio_request(GPIO_FN_VIO_CKO, NULL); 598 gpio_request(GPIO_FN_VIO_D15, NULL); 599 gpio_request(GPIO_FN_VIO_D14, NULL); 600 gpio_request(GPIO_FN_VIO_D13, NULL); 601 gpio_request(GPIO_FN_VIO_D12, NULL); 602 gpio_request(GPIO_FN_VIO_D11, NULL); 603 gpio_request(GPIO_FN_VIO_D10, NULL); 604 gpio_request(GPIO_FN_VIO_D9, NULL); 605 gpio_request(GPIO_FN_VIO_D8, NULL); 606 607 gpio_request(GPIO_PTZ7, NULL); 608 gpio_direction_output(GPIO_PTZ7, 0); /* OE_CAM */ 609 gpio_request(GPIO_PTZ6, NULL); 610 gpio_direction_output(GPIO_PTZ6, 0); /* STBY_CAM */ 611 gpio_request(GPIO_PTZ5, NULL); 612 gpio_direction_output(GPIO_PTZ5, 0); /* RST_CAM */ 613 gpio_request(GPIO_PTZ4, NULL); 614 gpio_direction_output(GPIO_PTZ4, 0); /* SADDR */ 615 616 __raw_writew(__raw_readw(PORT_MSELCRB) & ~0x0001, PORT_MSELCRB); 617 618 /* FLCTL */ 619 gpio_request(GPIO_FN_FCE, NULL); 620 gpio_request(GPIO_FN_NAF7, NULL); 621 gpio_request(GPIO_FN_NAF6, NULL); 622 gpio_request(GPIO_FN_NAF5, NULL); 623 gpio_request(GPIO_FN_NAF4, NULL); 624 gpio_request(GPIO_FN_NAF3, NULL); 625 gpio_request(GPIO_FN_NAF2, NULL); 626 gpio_request(GPIO_FN_NAF1, NULL); 627 gpio_request(GPIO_FN_NAF0, NULL); 628 gpio_request(GPIO_FN_FCDE, NULL); 629 gpio_request(GPIO_FN_FOE, NULL); 630 gpio_request(GPIO_FN_FSC, NULL); 631 gpio_request(GPIO_FN_FWE, NULL); 632 gpio_request(GPIO_FN_FRB, NULL); 633 634 __raw_writew(0, PORT_HIZCRC); 635 __raw_writew(0xFFFF, PORT_DRVCRA); 636 __raw_writew(0xFFFF, PORT_DRVCRB); 637 638 platform_resource_setup_memory(&ceu_device, "ceu", 4 << 20); 639 640 /* SDHI0 - CN3 - SD CARD */ 641 gpio_request(GPIO_FN_SDHI0CD_PTD, NULL); 642 gpio_request(GPIO_FN_SDHI0WP_PTD, NULL); 643 gpio_request(GPIO_FN_SDHI0D3_PTD, NULL); 644 gpio_request(GPIO_FN_SDHI0D2_PTD, NULL); 645 gpio_request(GPIO_FN_SDHI0D1_PTD, NULL); 646 gpio_request(GPIO_FN_SDHI0D0_PTD, NULL); 647 gpio_request(GPIO_FN_SDHI0CMD_PTD, NULL); 648 gpio_request(GPIO_FN_SDHI0CLK_PTD, NULL); 649 650 /* SDHI1 - CN7 - MICRO SD CARD */ 651 gpio_request(GPIO_FN_SDHI1CD, NULL); 652 gpio_request(GPIO_FN_SDHI1D3, NULL); 653 gpio_request(GPIO_FN_SDHI1D2, NULL); 654 gpio_request(GPIO_FN_SDHI1D1, NULL); 655 gpio_request(GPIO_FN_SDHI1D0, NULL); 656 gpio_request(GPIO_FN_SDHI1CMD, NULL); 657 gpio_request(GPIO_FN_SDHI1CLK, NULL); 658 659 i2c_register_board_info(0, ap325rxa_i2c_devices, 660 ARRAY_SIZE(ap325rxa_i2c_devices)); 661 662 return platform_add_devices(ap325rxa_devices, 663 ARRAY_SIZE(ap325rxa_devices)); 664 } 665 arch_initcall(ap325rxa_devices_setup); 666 667 /* Return the board specific boot mode pin configuration */ 668 static int ap325rxa_mode_pins(void) 669 { 670 /* MD0=0, MD1=0, MD2=0: Clock Mode 0 671 * MD3=0: 16-bit Area0 Bus Width 672 * MD5=1: Little Endian 673 * TSTMD=1, MD8=1: Test Mode Disabled 674 */ 675 return MODE_PIN5 | MODE_PIN8; 676 } 677 678 static struct sh_machine_vector mv_ap325rxa __initmv = { 679 .mv_name = "AP-325RXA", 680 .mv_mode_pins = ap325rxa_mode_pins, 681 }; 682