1 /* 2 * Renesas Technology Corp. SH7786 Urquell Support. 3 * 4 * Copyright (C) 2008 Kuninori Morimoto <morimoto.kuninori@renesas.com> 5 * Copyright (C) 2009 Paul Mundt 6 * 7 * Based on board-sh7785lcr.c 8 * Copyright (C) 2008 Yoshihiro Shimoda 9 * 10 * This file is subject to the terms and conditions of the GNU General Public 11 * License. See the file "COPYING" in the main directory of this archive 12 * for more details. 13 */ 14 #include <linux/init.h> 15 #include <linux/platform_device.h> 16 #include <linux/fb.h> 17 #include <linux/smc91x.h> 18 #include <linux/mtd/physmap.h> 19 #include <linux/delay.h> 20 #include <linux/gpio.h> 21 #include <linux/irq.h> 22 #include <mach/urquell.h> 23 #include <cpu/sh7786.h> 24 #include <asm/heartbeat.h> 25 #include <asm/sizes.h> 26 27 /* 28 * bit 1234 5678 29 *---------------------------- 30 * SW1 0101 0010 -> Pck 33MHz version 31 * (1101 0010) Pck 66MHz version 32 * SW2 0x1x xxxx -> little endian 33 * 29bit mode 34 * SW47 0001 1000 -> CS0 : on-board flash 35 * CS1 : SRAM, registers, LAN, PCMCIA 36 * 38400 bps for SCIF1 37 * 38 * Address 39 * 0x00000000 - 0x04000000 (CS0) Nor Flash 40 * 0x04000000 - 0x04200000 (CS1) SRAM 41 * 0x05000000 - 0x05800000 (CS1) on board register 42 * 0x05800000 - 0x06000000 (CS1) LAN91C111 43 * 0x06000000 - 0x06400000 (CS1) PCMCIA 44 * 0x08000000 - 0x10000000 (CS2-CS3) DDR3 45 * 0x10000000 - 0x14000000 (CS4) PCIe 46 * 0x14000000 - 0x14800000 (CS5) Core0 LRAM/URAM 47 * 0x14800000 - 0x15000000 (CS5) Core1 LRAM/URAM 48 * 0x18000000 - 0x1C000000 (CS6) ATA/NAND-Flash 49 * 0x1C000000 - (CS7) SH7786 Control register 50 */ 51 52 /* HeartBeat */ 53 static struct resource heartbeat_resources[] = { 54 [0] = { 55 .start = BOARDREG(SLEDR), 56 .end = BOARDREG(SLEDR), 57 .flags = IORESOURCE_MEM, 58 }, 59 }; 60 61 static struct heartbeat_data heartbeat_data = { 62 .regsize = 16, 63 }; 64 65 static struct platform_device heartbeat_device = { 66 .name = "heartbeat", 67 .id = -1, 68 .dev = { 69 .platform_data = &heartbeat_data, 70 }, 71 .num_resources = ARRAY_SIZE(heartbeat_resources), 72 .resource = heartbeat_resources, 73 }; 74 75 /* LAN91C111 */ 76 static struct smc91x_platdata smc91x_info = { 77 .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, 78 }; 79 80 static struct resource smc91x_eth_resources[] = { 81 [0] = { 82 .name = "SMC91C111" , 83 .start = 0x05800300, 84 .end = 0x0580030f, 85 .flags = IORESOURCE_MEM, 86 }, 87 [1] = { 88 .start = 11, 89 .flags = IORESOURCE_IRQ, 90 }, 91 }; 92 93 static struct platform_device smc91x_eth_device = { 94 .name = "smc91x", 95 .num_resources = ARRAY_SIZE(smc91x_eth_resources), 96 .resource = smc91x_eth_resources, 97 .dev = { 98 .platform_data = &smc91x_info, 99 }, 100 }; 101 102 /* Nor Flash */ 103 static struct mtd_partition nor_flash_partitions[] = { 104 { 105 .name = "loader", 106 .offset = 0x00000000, 107 .size = SZ_512K, 108 .mask_flags = MTD_WRITEABLE, /* Read-only */ 109 }, 110 { 111 .name = "bootenv", 112 .offset = MTDPART_OFS_APPEND, 113 .size = SZ_512K, 114 .mask_flags = MTD_WRITEABLE, /* Read-only */ 115 }, 116 { 117 .name = "kernel", 118 .offset = MTDPART_OFS_APPEND, 119 .size = SZ_4M, 120 }, 121 { 122 .name = "data", 123 .offset = MTDPART_OFS_APPEND, 124 .size = MTDPART_SIZ_FULL, 125 }, 126 }; 127 128 static struct physmap_flash_data nor_flash_data = { 129 .width = 2, 130 .parts = nor_flash_partitions, 131 .nr_parts = ARRAY_SIZE(nor_flash_partitions), 132 }; 133 134 static struct resource nor_flash_resources[] = { 135 [0] = { 136 .start = NOR_FLASH_ADDR, 137 .end = NOR_FLASH_ADDR + NOR_FLASH_SIZE - 1, 138 .flags = IORESOURCE_MEM, 139 } 140 }; 141 142 static struct platform_device nor_flash_device = { 143 .name = "physmap-flash", 144 .dev = { 145 .platform_data = &nor_flash_data, 146 }, 147 .num_resources = ARRAY_SIZE(nor_flash_resources), 148 .resource = nor_flash_resources, 149 }; 150 151 static struct platform_device *urquell_devices[] __initdata = { 152 &heartbeat_device, 153 &smc91x_eth_device, 154 &nor_flash_device, 155 }; 156 157 static int __init urquell_devices_setup(void) 158 { 159 /* USB */ 160 gpio_request(GPIO_FN_USB_OVC0, NULL); 161 gpio_request(GPIO_FN_USB_PENC0, NULL); 162 163 /* enable LAN */ 164 __raw_writew(__raw_readw(UBOARDREG(IRL2MSKR)) & ~0x00000001, 165 UBOARDREG(IRL2MSKR)); 166 167 return platform_add_devices(urquell_devices, 168 ARRAY_SIZE(urquell_devices)); 169 } 170 device_initcall(urquell_devices_setup); 171 172 static void urquell_power_off(void) 173 { 174 __raw_writew(0xa5a5, UBOARDREG(SRSTR)); 175 } 176 177 static void __init urquell_init_irq(void) 178 { 179 plat_irq_setup_pins(IRQ_MODE_IRL3210_MASK); 180 } 181 182 static int urquell_mode_pins(void) 183 { 184 return __raw_readw(UBOARDREG(MDSWMR)); 185 } 186 187 /* Initialize the board */ 188 static void __init urquell_setup(char **cmdline_p) 189 { 190 printk(KERN_INFO "Renesas Technology Corp. Urquell support.\n"); 191 192 pm_power_off = urquell_power_off; 193 } 194 195 /* 196 * The Machine Vector 197 */ 198 static struct sh_machine_vector mv_urquell __initmv = { 199 .mv_name = "Urquell", 200 .mv_setup = urquell_setup, 201 .mv_init_irq = urquell_init_irq, 202 .mv_mode_pins = urquell_mode_pins, 203 }; 204