1 /* 2 * Renesas Technology Corp. SH7786 Urquell Support. 3 * 4 * Copyright (C) 2008 Kuninori Morimoto <morimoto.kuninori@renesas.com> 5 * 6 * Based on board-sh7785lcr.c 7 * Copyright (C) 2008 Yoshihiro Shimoda 8 * 9 * This file is subject to the terms and conditions of the GNU General Public 10 * License. See the file "COPYING" in the main directory of this archive 11 * for more details. 12 */ 13 #include <linux/init.h> 14 #include <linux/platform_device.h> 15 #include <linux/fb.h> 16 #include <linux/smc91x.h> 17 #include <linux/mtd/physmap.h> 18 #include <linux/delay.h> 19 #include <linux/gpio.h> 20 #include <linux/irq.h> 21 #include <mach/urquell.h> 22 #include <cpu/sh7786.h> 23 #include <asm/heartbeat.h> 24 #include <asm/sizes.h> 25 26 /* 27 * bit 1234 5678 28 *---------------------------- 29 * SW1 0101 0010 -> Pck 33MHz version 30 * (1101 0010) Pck 66MHz version 31 * SW2 0x1x xxxx -> little endian 32 * 29bit mode 33 * SW47 0001 1000 -> CS0 : on-board flash 34 * CS1 : SRAM, registers, LAN, PCMCIA 35 * 38400 bps for SCIF1 36 * 37 * Address 38 * 0x00000000 - 0x04000000 (CS0) Nor Flash 39 * 0x04000000 - 0x04200000 (CS1) SRAM 40 * 0x05000000 - 0x05800000 (CS1) on board register 41 * 0x05800000 - 0x06000000 (CS1) LAN91C111 42 * 0x06000000 - 0x06400000 (CS1) PCMCIA 43 * 0x08000000 - 0x10000000 (CS2-CS3) DDR3 44 * 0x10000000 - 0x14000000 (CS4) PCIe 45 * 0x14000000 - 0x14800000 (CS5) Core0 LRAM/URAM 46 * 0x14800000 - 0x15000000 (CS5) Core1 LRAM/URAM 47 * 0x18000000 - 0x1C000000 (CS6) ATA/NAND-Flash 48 * 0x1C000000 - (CS7) SH7786 Control register 49 */ 50 51 /* HeartBeat */ 52 static struct resource heartbeat_resources[] = { 53 [0] = { 54 .start = BOARDREG(SLEDR), 55 .end = BOARDREG(SLEDR), 56 .flags = IORESOURCE_MEM, 57 }, 58 }; 59 60 static struct heartbeat_data heartbeat_data = { 61 .regsize = 16, 62 }; 63 64 static struct platform_device heartbeat_device = { 65 .name = "heartbeat", 66 .id = -1, 67 .dev = { 68 .platform_data = &heartbeat_data, 69 }, 70 .num_resources = ARRAY_SIZE(heartbeat_resources), 71 .resource = heartbeat_resources, 72 }; 73 74 /* LAN91C111 */ 75 static struct smc91x_platdata smc91x_info = { 76 .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, 77 }; 78 79 static struct resource smc91x_eth_resources[] = { 80 [0] = { 81 .name = "SMC91C111" , 82 .start = 0x05800300, 83 .end = 0x0580030f, 84 .flags = IORESOURCE_MEM, 85 }, 86 [1] = { 87 .start = 11, 88 .flags = IORESOURCE_IRQ, 89 }, 90 }; 91 92 static struct platform_device smc91x_eth_device = { 93 .name = "smc91x", 94 .num_resources = ARRAY_SIZE(smc91x_eth_resources), 95 .resource = smc91x_eth_resources, 96 .dev = { 97 .platform_data = &smc91x_info, 98 }, 99 }; 100 101 /* Nor Flash */ 102 static struct mtd_partition nor_flash_partitions[] = { 103 { 104 .name = "loader", 105 .offset = 0x00000000, 106 .size = SZ_512K, 107 .mask_flags = MTD_WRITEABLE, /* Read-only */ 108 }, 109 { 110 .name = "bootenv", 111 .offset = MTDPART_OFS_APPEND, 112 .size = SZ_512K, 113 .mask_flags = MTD_WRITEABLE, /* Read-only */ 114 }, 115 { 116 .name = "kernel", 117 .offset = MTDPART_OFS_APPEND, 118 .size = SZ_4M, 119 }, 120 { 121 .name = "data", 122 .offset = MTDPART_OFS_APPEND, 123 .size = MTDPART_SIZ_FULL, 124 }, 125 }; 126 127 static struct physmap_flash_data nor_flash_data = { 128 .width = 2, 129 .parts = nor_flash_partitions, 130 .nr_parts = ARRAY_SIZE(nor_flash_partitions), 131 }; 132 133 static struct resource nor_flash_resources[] = { 134 [0] = { 135 .start = NOR_FLASH_ADDR, 136 .end = NOR_FLASH_ADDR + NOR_FLASH_SIZE - 1, 137 .flags = IORESOURCE_MEM, 138 } 139 }; 140 141 static struct platform_device nor_flash_device = { 142 .name = "physmap-flash", 143 .dev = { 144 .platform_data = &nor_flash_data, 145 }, 146 .num_resources = ARRAY_SIZE(nor_flash_resources), 147 .resource = nor_flash_resources, 148 }; 149 150 static struct platform_device *urquell_devices[] __initdata = { 151 &heartbeat_device, 152 &smc91x_eth_device, 153 &nor_flash_device, 154 }; 155 156 static int __init urquell_devices_setup(void) 157 { 158 /* USB */ 159 gpio_request(GPIO_FN_USB_OVC0, NULL); 160 gpio_request(GPIO_FN_USB_PENC0, NULL); 161 162 /* enable LAN */ 163 __raw_writew(__raw_readw(UBOARDREG(IRL2MSKR)) & ~0x00000001, 164 UBOARDREG(IRL2MSKR)); 165 166 return platform_add_devices(urquell_devices, 167 ARRAY_SIZE(urquell_devices)); 168 } 169 device_initcall(urquell_devices_setup); 170 171 static void urquell_power_off(void) 172 { 173 __raw_writew(0xa5a5, UBOARDREG(SRSTR)); 174 } 175 176 static void __init urquell_init_irq(void) 177 { 178 plat_irq_setup_pins(IRQ_MODE_IRL3210_MASK); 179 } 180 181 /* Initialize the board */ 182 static void __init urquell_setup(char **cmdline_p) 183 { 184 printk(KERN_INFO "Renesas Technology Corp. Urquell support.\n"); 185 186 pm_power_off = urquell_power_off; 187 } 188 189 /* 190 * The Machine Vector 191 */ 192 static struct sh_machine_vector mv_urquell __initmv = { 193 .mv_name = "Urquell", 194 .mv_setup = urquell_setup, 195 .mv_init_irq = urquell_init_irq, 196 }; 197