1 /* 2 * Renesas Technology Corp. SH7786 Urquell Support. 3 * 4 * Copyright (C) 2008 Kuninori Morimoto <morimoto.kuninori@renesas.com> 5 * Copyright (C) 2009, 2010 Paul Mundt 6 * 7 * Based on board-sh7785lcr.c 8 * Copyright (C) 2008 Yoshihiro Shimoda 9 * 10 * This file is subject to the terms and conditions of the GNU General Public 11 * License. See the file "COPYING" in the main directory of this archive 12 * for more details. 13 */ 14 #include <linux/init.h> 15 #include <linux/platform_device.h> 16 #include <linux/fb.h> 17 #include <linux/smc91x.h> 18 #include <linux/mtd/physmap.h> 19 #include <linux/delay.h> 20 #include <linux/gpio.h> 21 #include <linux/irq.h> 22 #include <linux/clk.h> 23 #include <mach/urquell.h> 24 #include <cpu/sh7786.h> 25 #include <asm/heartbeat.h> 26 #include <asm/sizes.h> 27 #include <asm/smp-ops.h> 28 29 /* 30 * bit 1234 5678 31 *---------------------------- 32 * SW1 0101 0010 -> Pck 33MHz version 33 * (1101 0010) Pck 66MHz version 34 * SW2 0x1x xxxx -> little endian 35 * 29bit mode 36 * SW47 0001 1000 -> CS0 : on-board flash 37 * CS1 : SRAM, registers, LAN, PCMCIA 38 * 38400 bps for SCIF1 39 * 40 * Address 41 * 0x00000000 - 0x04000000 (CS0) Nor Flash 42 * 0x04000000 - 0x04200000 (CS1) SRAM 43 * 0x05000000 - 0x05800000 (CS1) on board register 44 * 0x05800000 - 0x06000000 (CS1) LAN91C111 45 * 0x06000000 - 0x06400000 (CS1) PCMCIA 46 * 0x08000000 - 0x10000000 (CS2-CS3) DDR3 47 * 0x10000000 - 0x14000000 (CS4) PCIe 48 * 0x14000000 - 0x14800000 (CS5) Core0 LRAM/URAM 49 * 0x14800000 - 0x15000000 (CS5) Core1 LRAM/URAM 50 * 0x18000000 - 0x1C000000 (CS6) ATA/NAND-Flash 51 * 0x1C000000 - (CS7) SH7786 Control register 52 */ 53 54 /* HeartBeat */ 55 static struct resource heartbeat_resource = { 56 .start = BOARDREG(SLEDR), 57 .end = BOARDREG(SLEDR), 58 .flags = IORESOURCE_MEM | IORESOURCE_MEM_16BIT, 59 }; 60 61 static struct platform_device heartbeat_device = { 62 .name = "heartbeat", 63 .id = -1, 64 .num_resources = 1, 65 .resource = &heartbeat_resource, 66 }; 67 68 /* LAN91C111 */ 69 static struct smc91x_platdata smc91x_info = { 70 .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, 71 }; 72 73 static struct resource smc91x_eth_resources[] = { 74 [0] = { 75 .name = "SMC91C111" , 76 .start = 0x05800300, 77 .end = 0x0580030f, 78 .flags = IORESOURCE_MEM, 79 }, 80 [1] = { 81 .start = 11, 82 .flags = IORESOURCE_IRQ, 83 }, 84 }; 85 86 static struct platform_device smc91x_eth_device = { 87 .name = "smc91x", 88 .num_resources = ARRAY_SIZE(smc91x_eth_resources), 89 .resource = smc91x_eth_resources, 90 .dev = { 91 .platform_data = &smc91x_info, 92 }, 93 }; 94 95 /* Nor Flash */ 96 static struct mtd_partition nor_flash_partitions[] = { 97 { 98 .name = "loader", 99 .offset = 0x00000000, 100 .size = SZ_512K, 101 .mask_flags = MTD_WRITEABLE, /* Read-only */ 102 }, 103 { 104 .name = "bootenv", 105 .offset = MTDPART_OFS_APPEND, 106 .size = SZ_512K, 107 .mask_flags = MTD_WRITEABLE, /* Read-only */ 108 }, 109 { 110 .name = "kernel", 111 .offset = MTDPART_OFS_APPEND, 112 .size = SZ_4M, 113 }, 114 { 115 .name = "data", 116 .offset = MTDPART_OFS_APPEND, 117 .size = MTDPART_SIZ_FULL, 118 }, 119 }; 120 121 static struct physmap_flash_data nor_flash_data = { 122 .width = 2, 123 .parts = nor_flash_partitions, 124 .nr_parts = ARRAY_SIZE(nor_flash_partitions), 125 }; 126 127 static struct resource nor_flash_resources[] = { 128 [0] = { 129 .start = NOR_FLASH_ADDR, 130 .end = NOR_FLASH_ADDR + NOR_FLASH_SIZE - 1, 131 .flags = IORESOURCE_MEM, 132 } 133 }; 134 135 static struct platform_device nor_flash_device = { 136 .name = "physmap-flash", 137 .dev = { 138 .platform_data = &nor_flash_data, 139 }, 140 .num_resources = ARRAY_SIZE(nor_flash_resources), 141 .resource = nor_flash_resources, 142 }; 143 144 static struct platform_device *urquell_devices[] __initdata = { 145 &heartbeat_device, 146 &smc91x_eth_device, 147 &nor_flash_device, 148 }; 149 150 static int __init urquell_devices_setup(void) 151 { 152 /* USB */ 153 gpio_request(GPIO_FN_USB_OVC0, NULL); 154 gpio_request(GPIO_FN_USB_PENC0, NULL); 155 156 /* enable LAN */ 157 __raw_writew(__raw_readw(UBOARDREG(IRL2MSKR)) & ~0x00000001, 158 UBOARDREG(IRL2MSKR)); 159 160 return platform_add_devices(urquell_devices, 161 ARRAY_SIZE(urquell_devices)); 162 } 163 device_initcall(urquell_devices_setup); 164 165 static void urquell_power_off(void) 166 { 167 __raw_writew(0xa5a5, UBOARDREG(SRSTR)); 168 } 169 170 static void __init urquell_init_irq(void) 171 { 172 plat_irq_setup_pins(IRQ_MODE_IRL3210_MASK); 173 } 174 175 static int urquell_mode_pins(void) 176 { 177 return __raw_readw(UBOARDREG(MDSWMR)); 178 } 179 180 static int urquell_clk_init(void) 181 { 182 struct clk *clk; 183 int ret; 184 185 /* 186 * Only handle the EXTAL case, anyone interfacing a crystal 187 * resonator will need to provide their own input clock. 188 */ 189 if (test_mode_pin(MODE_PIN9)) 190 return -EINVAL; 191 192 clk = clk_get(NULL, "extal"); 193 if (IS_ERR(clk)) 194 return PTR_ERR(clk); 195 ret = clk_set_rate(clk, 33333333); 196 clk_put(clk); 197 198 return ret; 199 } 200 201 /* Initialize the board */ 202 static void __init urquell_setup(char **cmdline_p) 203 { 204 printk(KERN_INFO "Renesas Technology Corp. Urquell support.\n"); 205 206 pm_power_off = urquell_power_off; 207 208 register_smp_ops(&shx3_smp_ops); 209 } 210 211 /* 212 * The Machine Vector 213 */ 214 static struct sh_machine_vector mv_urquell __initmv = { 215 .mv_name = "Urquell", 216 .mv_setup = urquell_setup, 217 .mv_init_irq = urquell_init_irq, 218 .mv_mode_pins = urquell_mode_pins, 219 .mv_clk_init = urquell_clk_init, 220 }; 221