1 /* 2 * Renesas Technology Corp. R0P7785LC0011RL Support. 3 * 4 * Copyright (C) 2008 Yoshihiro Shimoda 5 * Copyright (C) 2009 Paul Mundt 6 * 7 * This file is subject to the terms and conditions of the GNU General Public 8 * License. See the file "COPYING" in the main directory of this archive 9 * for more details. 10 */ 11 #include <linux/init.h> 12 #include <linux/platform_device.h> 13 #include <linux/sm501.h> 14 #include <linux/sm501-regs.h> 15 #include <linux/fb.h> 16 #include <linux/mtd/physmap.h> 17 #include <linux/delay.h> 18 #include <linux/interrupt.h> 19 #include <linux/i2c.h> 20 #include <linux/i2c-pca-platform.h> 21 #include <linux/i2c-algo-pca.h> 22 #include <linux/usb/r8a66597.h> 23 #include <linux/irq.h> 24 #include <linux/clk.h> 25 #include <linux/errno.h> 26 #include <mach/sh7785lcr.h> 27 #include <cpu/sh7785.h> 28 #include <asm/heartbeat.h> 29 #include <asm/clock.h> 30 31 /* 32 * NOTE: This board has 2 physical memory maps. 33 * Please look at include/asm-sh/sh7785lcr.h or hardware manual. 34 */ 35 static struct resource heartbeat_resources[] = { 36 [0] = { 37 .start = PLD_LEDCR, 38 .end = PLD_LEDCR, 39 .flags = IORESOURCE_MEM, 40 }, 41 }; 42 43 static struct heartbeat_data heartbeat_data = { 44 .regsize = 8, 45 }; 46 47 static struct platform_device heartbeat_device = { 48 .name = "heartbeat", 49 .id = -1, 50 .dev = { 51 .platform_data = &heartbeat_data, 52 }, 53 .num_resources = ARRAY_SIZE(heartbeat_resources), 54 .resource = heartbeat_resources, 55 }; 56 57 static struct mtd_partition nor_flash_partitions[] = { 58 { 59 .name = "loader", 60 .offset = 0x00000000, 61 .size = 512 * 1024, 62 }, 63 { 64 .name = "bootenv", 65 .offset = MTDPART_OFS_APPEND, 66 .size = 512 * 1024, 67 }, 68 { 69 .name = "kernel", 70 .offset = MTDPART_OFS_APPEND, 71 .size = 4 * 1024 * 1024, 72 }, 73 { 74 .name = "data", 75 .offset = MTDPART_OFS_APPEND, 76 .size = MTDPART_SIZ_FULL, 77 }, 78 }; 79 80 static struct physmap_flash_data nor_flash_data = { 81 .width = 4, 82 .parts = nor_flash_partitions, 83 .nr_parts = ARRAY_SIZE(nor_flash_partitions), 84 }; 85 86 static struct resource nor_flash_resources[] = { 87 [0] = { 88 .start = NOR_FLASH_ADDR, 89 .end = NOR_FLASH_ADDR + NOR_FLASH_SIZE - 1, 90 .flags = IORESOURCE_MEM, 91 } 92 }; 93 94 static struct platform_device nor_flash_device = { 95 .name = "physmap-flash", 96 .dev = { 97 .platform_data = &nor_flash_data, 98 }, 99 .num_resources = ARRAY_SIZE(nor_flash_resources), 100 .resource = nor_flash_resources, 101 }; 102 103 static struct r8a66597_platdata r8a66597_data = { 104 .xtal = R8A66597_PLATDATA_XTAL_12MHZ, 105 .vif = 1, 106 }; 107 108 static struct resource r8a66597_usb_host_resources[] = { 109 [0] = { 110 .start = R8A66597_ADDR, 111 .end = R8A66597_ADDR + R8A66597_SIZE - 1, 112 .flags = IORESOURCE_MEM, 113 }, 114 [1] = { 115 .start = 2, 116 .end = 2, 117 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW, 118 }, 119 }; 120 121 static struct platform_device r8a66597_usb_host_device = { 122 .name = "r8a66597_hcd", 123 .id = -1, 124 .dev = { 125 .dma_mask = NULL, 126 .coherent_dma_mask = 0xffffffff, 127 .platform_data = &r8a66597_data, 128 }, 129 .num_resources = ARRAY_SIZE(r8a66597_usb_host_resources), 130 .resource = r8a66597_usb_host_resources, 131 }; 132 133 static struct resource sm501_resources[] = { 134 [0] = { 135 .start = SM107_MEM_ADDR, 136 .end = SM107_MEM_ADDR + SM107_MEM_SIZE - 1, 137 .flags = IORESOURCE_MEM, 138 }, 139 [1] = { 140 .start = SM107_REG_ADDR, 141 .end = SM107_REG_ADDR + SM107_REG_SIZE - 1, 142 .flags = IORESOURCE_MEM, 143 }, 144 [2] = { 145 .start = 10, 146 .flags = IORESOURCE_IRQ, 147 }, 148 }; 149 150 static struct fb_videomode sm501_default_mode_crt = { 151 .pixclock = 35714, /* 28MHz */ 152 .xres = 640, 153 .yres = 480, 154 .left_margin = 105, 155 .right_margin = 16, 156 .upper_margin = 33, 157 .lower_margin = 10, 158 .hsync_len = 39, 159 .vsync_len = 2, 160 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 161 }; 162 163 static struct fb_videomode sm501_default_mode_pnl = { 164 .pixclock = 40000, /* 25MHz */ 165 .xres = 640, 166 .yres = 480, 167 .left_margin = 2, 168 .right_margin = 16, 169 .upper_margin = 33, 170 .lower_margin = 10, 171 .hsync_len = 39, 172 .vsync_len = 2, 173 .sync = 0, 174 }; 175 176 static struct sm501_platdata_fbsub sm501_pdata_fbsub_pnl = { 177 .def_bpp = 16, 178 .def_mode = &sm501_default_mode_pnl, 179 .flags = SM501FB_FLAG_USE_INIT_MODE | 180 SM501FB_FLAG_USE_HWCURSOR | 181 SM501FB_FLAG_USE_HWACCEL | 182 SM501FB_FLAG_DISABLE_AT_EXIT | 183 SM501FB_FLAG_PANEL_NO_VBIASEN, 184 }; 185 186 static struct sm501_platdata_fbsub sm501_pdata_fbsub_crt = { 187 .def_bpp = 16, 188 .def_mode = &sm501_default_mode_crt, 189 .flags = SM501FB_FLAG_USE_INIT_MODE | 190 SM501FB_FLAG_USE_HWCURSOR | 191 SM501FB_FLAG_USE_HWACCEL | 192 SM501FB_FLAG_DISABLE_AT_EXIT, 193 }; 194 195 static struct sm501_platdata_fb sm501_fb_pdata = { 196 .fb_route = SM501_FB_OWN, 197 .fb_crt = &sm501_pdata_fbsub_crt, 198 .fb_pnl = &sm501_pdata_fbsub_pnl, 199 }; 200 201 static struct sm501_initdata sm501_initdata = { 202 .gpio_high = { 203 .set = 0x00001fe0, 204 .mask = 0x0, 205 }, 206 .devices = 0, 207 .mclk = 84 * 1000000, 208 .m1xclk = 112 * 1000000, 209 }; 210 211 static struct sm501_platdata sm501_platform_data = { 212 .init = &sm501_initdata, 213 .fb = &sm501_fb_pdata, 214 }; 215 216 static struct platform_device sm501_device = { 217 .name = "sm501", 218 .id = -1, 219 .dev = { 220 .platform_data = &sm501_platform_data, 221 }, 222 .num_resources = ARRAY_SIZE(sm501_resources), 223 .resource = sm501_resources, 224 }; 225 226 static struct resource i2c_proto_resources[] = { 227 [0] = { 228 .start = PCA9564_PROTO_32BIT_ADDR, 229 .end = PCA9564_PROTO_32BIT_ADDR + PCA9564_SIZE - 1, 230 .flags = IORESOURCE_MEM | IORESOURCE_MEM_8BIT, 231 }, 232 [1] = { 233 .start = 12, 234 .end = 12, 235 .flags = IORESOURCE_IRQ, 236 }, 237 }; 238 239 static struct resource i2c_resources[] = { 240 [0] = { 241 .start = PCA9564_ADDR, 242 .end = PCA9564_ADDR + PCA9564_SIZE - 1, 243 .flags = IORESOURCE_MEM | IORESOURCE_MEM_8BIT, 244 }, 245 [1] = { 246 .start = 12, 247 .end = 12, 248 .flags = IORESOURCE_IRQ, 249 }, 250 }; 251 252 static struct i2c_pca9564_pf_platform_data i2c_platform_data = { 253 .gpio = 0, 254 .i2c_clock_speed = I2C_PCA_CON_330kHz, 255 .timeout = HZ, 256 }; 257 258 static struct platform_device i2c_device = { 259 .name = "i2c-pca-platform", 260 .id = -1, 261 .dev = { 262 .platform_data = &i2c_platform_data, 263 }, 264 .num_resources = ARRAY_SIZE(i2c_resources), 265 .resource = i2c_resources, 266 }; 267 268 static struct platform_device *sh7785lcr_devices[] __initdata = { 269 &heartbeat_device, 270 &nor_flash_device, 271 &r8a66597_usb_host_device, 272 &sm501_device, 273 &i2c_device, 274 }; 275 276 static struct i2c_board_info __initdata sh7785lcr_i2c_devices[] = { 277 { 278 I2C_BOARD_INFO("r2025sd", 0x32), 279 }, 280 }; 281 282 static int __init sh7785lcr_devices_setup(void) 283 { 284 i2c_register_board_info(0, sh7785lcr_i2c_devices, 285 ARRAY_SIZE(sh7785lcr_i2c_devices)); 286 287 if (mach_is_sh7785lcr_pt()) { 288 i2c_device.resource = i2c_proto_resources; 289 i2c_device.num_resources = ARRAY_SIZE(i2c_proto_resources); 290 } 291 292 return platform_add_devices(sh7785lcr_devices, 293 ARRAY_SIZE(sh7785lcr_devices)); 294 } 295 __initcall(sh7785lcr_devices_setup); 296 297 /* Initialize IRQ setting */ 298 void __init init_sh7785lcr_IRQ(void) 299 { 300 plat_irq_setup_pins(IRQ_MODE_IRQ7654); 301 plat_irq_setup_pins(IRQ_MODE_IRQ3210); 302 } 303 304 static int sh7785lcr_clk_init(void) 305 { 306 struct clk *clk; 307 int ret; 308 309 clk = clk_get(NULL, "extal"); 310 if (!clk || IS_ERR(clk)) 311 return PTR_ERR(clk); 312 ret = clk_set_rate(clk, 33333333); 313 clk_put(clk); 314 315 return ret; 316 } 317 318 static void sh7785lcr_power_off(void) 319 { 320 unsigned char *p; 321 322 p = ioremap(PLD_POFCR, PLD_POFCR + 1); 323 if (!p) { 324 printk(KERN_ERR "%s: ioremap error.\n", __func__); 325 return; 326 } 327 *p = 0x01; 328 iounmap(p); 329 set_bl_bit(); 330 while (1) 331 cpu_relax(); 332 } 333 334 /* Initialize the board */ 335 static void __init sh7785lcr_setup(char **cmdline_p) 336 { 337 void __iomem *sm501_reg; 338 339 printk(KERN_INFO "Renesas Technology Corp. R0P7785LC0011RL support.\n"); 340 341 pm_power_off = sh7785lcr_power_off; 342 343 /* sm501 DRAM configuration */ 344 sm501_reg = (void __iomem *)0xb3e00000 + SM501_DRAM_CONTROL; 345 writel(0x000307c2, sm501_reg); 346 } 347 348 /* Return the board specific boot mode pin configuration */ 349 static int sh7785lcr_mode_pins(void) 350 { 351 int value = 0; 352 353 /* These are the factory default settings of S1 and S2. 354 * If you change these dip switches then you will need to 355 * adjust the values below as well. 356 */ 357 value |= MODE_PIN4; /* Clock Mode 16 */ 358 value |= MODE_PIN5; /* 32-bit Area0 bus width */ 359 value |= MODE_PIN6; /* 32-bit Area0 bus width */ 360 value |= MODE_PIN7; /* Area 0 SRAM interface [fixed] */ 361 value |= MODE_PIN8; /* Little Endian */ 362 value |= MODE_PIN9; /* Master Mode */ 363 value |= MODE_PIN14; /* No PLL step-up */ 364 365 return value; 366 } 367 368 /* 369 * The Machine Vector 370 */ 371 static struct sh_machine_vector mv_sh7785lcr __initmv = { 372 .mv_name = "SH7785LCR", 373 .mv_setup = sh7785lcr_setup, 374 .mv_clk_init = sh7785lcr_clk_init, 375 .mv_init_irq = init_sh7785lcr_IRQ, 376 .mv_mode_pins = sh7785lcr_mode_pins, 377 }; 378 379