1 /* 2 * Renesas R0P7757LC0012RL Support. 3 * 4 * Copyright (C) 2009 - 2010 Renesas Solutions Corp. 5 * 6 * This file is subject to the terms and conditions of the GNU General Public 7 * License. See the file "COPYING" in the main directory of this archive 8 * for more details. 9 */ 10 11 #include <linux/init.h> 12 #include <linux/platform_device.h> 13 #include <linux/gpio.h> 14 #include <linux/irq.h> 15 #include <linux/regulator/fixed.h> 16 #include <linux/regulator/machine.h> 17 #include <linux/spi/spi.h> 18 #include <linux/spi/flash.h> 19 #include <linux/io.h> 20 #include <linux/mfd/tmio.h> 21 #include <linux/mmc/host.h> 22 #include <linux/mmc/sh_mmcif.h> 23 #include <linux/sh_eth.h> 24 #include <linux/sh_intc.h> 25 #include <linux/usb/renesas_usbhs.h> 26 #include <cpu/sh7757.h> 27 #include <asm/heartbeat.h> 28 29 static struct resource heartbeat_resource = { 30 .start = 0xffec005c, /* PUDR */ 31 .end = 0xffec005c, 32 .flags = IORESOURCE_MEM | IORESOURCE_MEM_8BIT, 33 }; 34 35 static unsigned char heartbeat_bit_pos[] = { 0, 1, 2, 3 }; 36 37 static struct heartbeat_data heartbeat_data = { 38 .bit_pos = heartbeat_bit_pos, 39 .nr_bits = ARRAY_SIZE(heartbeat_bit_pos), 40 .flags = HEARTBEAT_INVERTED, 41 }; 42 43 static struct platform_device heartbeat_device = { 44 .name = "heartbeat", 45 .id = -1, 46 .dev = { 47 .platform_data = &heartbeat_data, 48 }, 49 .num_resources = 1, 50 .resource = &heartbeat_resource, 51 }; 52 53 /* Fast Ethernet */ 54 #define GBECONT 0xffc10100 55 #define GBECONT_RMII1 BIT(17) 56 #define GBECONT_RMII0 BIT(16) 57 static void sh7757_eth_set_mdio_gate(void *addr) 58 { 59 if (((unsigned long)addr & 0x00000fff) < 0x0800) 60 writel(readl(GBECONT) | GBECONT_RMII0, GBECONT); 61 else 62 writel(readl(GBECONT) | GBECONT_RMII1, GBECONT); 63 } 64 65 static struct resource sh_eth0_resources[] = { 66 { 67 .start = 0xfef00000, 68 .end = 0xfef001ff, 69 .flags = IORESOURCE_MEM, 70 }, { 71 .start = evt2irq(0xc80), 72 .end = evt2irq(0xc80), 73 .flags = IORESOURCE_IRQ, 74 }, 75 }; 76 77 static struct sh_eth_plat_data sh7757_eth0_pdata = { 78 .phy = 1, 79 .set_mdio_gate = sh7757_eth_set_mdio_gate, 80 }; 81 82 static struct platform_device sh7757_eth0_device = { 83 .name = "sh7757-ether", 84 .resource = sh_eth0_resources, 85 .id = 0, 86 .num_resources = ARRAY_SIZE(sh_eth0_resources), 87 .dev = { 88 .platform_data = &sh7757_eth0_pdata, 89 }, 90 }; 91 92 static struct resource sh_eth1_resources[] = { 93 { 94 .start = 0xfef00800, 95 .end = 0xfef009ff, 96 .flags = IORESOURCE_MEM, 97 }, { 98 .start = evt2irq(0xc80), 99 .end = evt2irq(0xc80), 100 .flags = IORESOURCE_IRQ, 101 }, 102 }; 103 104 static struct sh_eth_plat_data sh7757_eth1_pdata = { 105 .phy = 1, 106 .set_mdio_gate = sh7757_eth_set_mdio_gate, 107 }; 108 109 static struct platform_device sh7757_eth1_device = { 110 .name = "sh7757-ether", 111 .resource = sh_eth1_resources, 112 .id = 1, 113 .num_resources = ARRAY_SIZE(sh_eth1_resources), 114 .dev = { 115 .platform_data = &sh7757_eth1_pdata, 116 }, 117 }; 118 119 static void sh7757_eth_giga_set_mdio_gate(void *addr) 120 { 121 if (((unsigned long)addr & 0x00000fff) < 0x0800) { 122 gpio_set_value(GPIO_PTT4, 1); 123 writel(readl(GBECONT) & ~GBECONT_RMII0, GBECONT); 124 } else { 125 gpio_set_value(GPIO_PTT4, 0); 126 writel(readl(GBECONT) & ~GBECONT_RMII1, GBECONT); 127 } 128 } 129 130 static struct resource sh_eth_giga0_resources[] = { 131 { 132 .start = 0xfee00000, 133 .end = 0xfee007ff, 134 .flags = IORESOURCE_MEM, 135 }, { 136 /* TSU */ 137 .start = 0xfee01800, 138 .end = 0xfee01fff, 139 .flags = IORESOURCE_MEM, 140 }, { 141 .start = evt2irq(0x2960), 142 .end = evt2irq(0x2960), 143 .flags = IORESOURCE_IRQ, 144 }, 145 }; 146 147 static struct sh_eth_plat_data sh7757_eth_giga0_pdata = { 148 .phy = 18, 149 .set_mdio_gate = sh7757_eth_giga_set_mdio_gate, 150 .phy_interface = PHY_INTERFACE_MODE_RGMII_ID, 151 }; 152 153 static struct platform_device sh7757_eth_giga0_device = { 154 .name = "sh7757-gether", 155 .resource = sh_eth_giga0_resources, 156 .id = 2, 157 .num_resources = ARRAY_SIZE(sh_eth_giga0_resources), 158 .dev = { 159 .platform_data = &sh7757_eth_giga0_pdata, 160 }, 161 }; 162 163 static struct resource sh_eth_giga1_resources[] = { 164 { 165 .start = 0xfee00800, 166 .end = 0xfee00fff, 167 .flags = IORESOURCE_MEM, 168 }, { 169 /* TSU */ 170 .start = 0xfee01800, 171 .end = 0xfee01fff, 172 .flags = IORESOURCE_MEM, 173 }, { 174 .start = evt2irq(0x2980), 175 .end = evt2irq(0x2980), 176 .flags = IORESOURCE_IRQ, 177 }, 178 }; 179 180 static struct sh_eth_plat_data sh7757_eth_giga1_pdata = { 181 .phy = 19, 182 .set_mdio_gate = sh7757_eth_giga_set_mdio_gate, 183 .phy_interface = PHY_INTERFACE_MODE_RGMII_ID, 184 }; 185 186 static struct platform_device sh7757_eth_giga1_device = { 187 .name = "sh7757-gether", 188 .resource = sh_eth_giga1_resources, 189 .id = 3, 190 .num_resources = ARRAY_SIZE(sh_eth_giga1_resources), 191 .dev = { 192 .platform_data = &sh7757_eth_giga1_pdata, 193 }, 194 }; 195 196 /* Fixed 3.3V regulator to be used by SDHI0, MMCIF */ 197 static struct regulator_consumer_supply fixed3v3_power_consumers[] = 198 { 199 REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"), 200 REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"), 201 REGULATOR_SUPPLY("vmmc", "sh_mmcif.0"), 202 REGULATOR_SUPPLY("vqmmc", "sh_mmcif.0"), 203 }; 204 205 /* SH_MMCIF */ 206 static struct resource sh_mmcif_resources[] = { 207 [0] = { 208 .start = 0xffcb0000, 209 .end = 0xffcb00ff, 210 .flags = IORESOURCE_MEM, 211 }, 212 [1] = { 213 .start = evt2irq(0x1c60), 214 .flags = IORESOURCE_IRQ, 215 }, 216 [2] = { 217 .start = evt2irq(0x1c80), 218 .flags = IORESOURCE_IRQ, 219 }, 220 }; 221 222 static struct sh_mmcif_plat_data sh_mmcif_plat = { 223 .sup_pclk = 0x0f, 224 .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA | 225 MMC_CAP_NONREMOVABLE, 226 .ocr = MMC_VDD_32_33 | MMC_VDD_33_34, 227 .slave_id_tx = SHDMA_SLAVE_MMCIF_TX, 228 .slave_id_rx = SHDMA_SLAVE_MMCIF_RX, 229 }; 230 231 static struct platform_device sh_mmcif_device = { 232 .name = "sh_mmcif", 233 .id = 0, 234 .dev = { 235 .platform_data = &sh_mmcif_plat, 236 }, 237 .num_resources = ARRAY_SIZE(sh_mmcif_resources), 238 .resource = sh_mmcif_resources, 239 }; 240 241 /* SDHI0 */ 242 static struct tmio_mmc_data sdhi_info = { 243 .chan_priv_tx = (void *)SHDMA_SLAVE_SDHI_TX, 244 .chan_priv_rx = (void *)SHDMA_SLAVE_SDHI_RX, 245 .capabilities = MMC_CAP_SD_HIGHSPEED, 246 }; 247 248 static struct resource sdhi_resources[] = { 249 [0] = { 250 .start = 0xffe50000, 251 .end = 0xffe500ff, 252 .flags = IORESOURCE_MEM, 253 }, 254 [1] = { 255 .start = evt2irq(0x480), 256 .flags = IORESOURCE_IRQ, 257 }, 258 }; 259 260 static struct platform_device sdhi_device = { 261 .name = "sh_mobile_sdhi", 262 .num_resources = ARRAY_SIZE(sdhi_resources), 263 .resource = sdhi_resources, 264 .id = 0, 265 .dev = { 266 .platform_data = &sdhi_info, 267 }, 268 }; 269 270 static int usbhs0_get_id(struct platform_device *pdev) 271 { 272 return USBHS_GADGET; 273 } 274 275 static struct renesas_usbhs_platform_info usb0_data = { 276 .platform_callback = { 277 .get_id = usbhs0_get_id, 278 }, 279 .driver_param = { 280 .buswait_bwait = 5, 281 } 282 }; 283 284 static struct resource usb0_resources[] = { 285 [0] = { 286 .start = 0xfe450000, 287 .end = 0xfe4501ff, 288 .flags = IORESOURCE_MEM, 289 }, 290 [1] = { 291 .start = evt2irq(0x840), 292 .end = evt2irq(0x840), 293 .flags = IORESOURCE_IRQ, 294 }, 295 }; 296 297 static struct platform_device usb0_device = { 298 .name = "renesas_usbhs", 299 .id = 0, 300 .dev = { 301 .platform_data = &usb0_data, 302 }, 303 .num_resources = ARRAY_SIZE(usb0_resources), 304 .resource = usb0_resources, 305 }; 306 307 static struct platform_device *sh7757lcr_devices[] __initdata = { 308 &heartbeat_device, 309 &sh7757_eth0_device, 310 &sh7757_eth1_device, 311 &sh7757_eth_giga0_device, 312 &sh7757_eth_giga1_device, 313 &sh_mmcif_device, 314 &sdhi_device, 315 &usb0_device, 316 }; 317 318 static struct flash_platform_data spi_flash_data = { 319 .name = "m25p80", 320 .type = "m25px64", 321 }; 322 323 static struct spi_board_info spi_board_info[] = { 324 { 325 .modalias = "m25p80", 326 .max_speed_hz = 25000000, 327 .bus_num = 0, 328 .chip_select = 1, 329 .platform_data = &spi_flash_data, 330 }, 331 }; 332 333 static int __init sh7757lcr_devices_setup(void) 334 { 335 regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers, 336 ARRAY_SIZE(fixed3v3_power_consumers), 3300000); 337 338 /* RGMII (PTA) */ 339 gpio_request(GPIO_FN_ET0_MDC, NULL); 340 gpio_request(GPIO_FN_ET0_MDIO, NULL); 341 gpio_request(GPIO_FN_ET1_MDC, NULL); 342 gpio_request(GPIO_FN_ET1_MDIO, NULL); 343 344 /* ONFI (PTB, PTZ) */ 345 gpio_request(GPIO_FN_ON_NRE, NULL); 346 gpio_request(GPIO_FN_ON_NWE, NULL); 347 gpio_request(GPIO_FN_ON_NWP, NULL); 348 gpio_request(GPIO_FN_ON_NCE0, NULL); 349 gpio_request(GPIO_FN_ON_R_B0, NULL); 350 gpio_request(GPIO_FN_ON_ALE, NULL); 351 gpio_request(GPIO_FN_ON_CLE, NULL); 352 353 gpio_request(GPIO_FN_ON_DQ7, NULL); 354 gpio_request(GPIO_FN_ON_DQ6, NULL); 355 gpio_request(GPIO_FN_ON_DQ5, NULL); 356 gpio_request(GPIO_FN_ON_DQ4, NULL); 357 gpio_request(GPIO_FN_ON_DQ3, NULL); 358 gpio_request(GPIO_FN_ON_DQ2, NULL); 359 gpio_request(GPIO_FN_ON_DQ1, NULL); 360 gpio_request(GPIO_FN_ON_DQ0, NULL); 361 362 /* IRQ8 to 0 (PTB, PTC) */ 363 gpio_request(GPIO_FN_IRQ8, NULL); 364 gpio_request(GPIO_FN_IRQ7, NULL); 365 gpio_request(GPIO_FN_IRQ6, NULL); 366 gpio_request(GPIO_FN_IRQ5, NULL); 367 gpio_request(GPIO_FN_IRQ4, NULL); 368 gpio_request(GPIO_FN_IRQ3, NULL); 369 gpio_request(GPIO_FN_IRQ2, NULL); 370 gpio_request(GPIO_FN_IRQ1, NULL); 371 gpio_request(GPIO_FN_IRQ0, NULL); 372 373 /* SPI0 (PTD) */ 374 gpio_request(GPIO_FN_SP0_MOSI, NULL); 375 gpio_request(GPIO_FN_SP0_MISO, NULL); 376 gpio_request(GPIO_FN_SP0_SCK, NULL); 377 gpio_request(GPIO_FN_SP0_SCK_FB, NULL); 378 gpio_request(GPIO_FN_SP0_SS0, NULL); 379 gpio_request(GPIO_FN_SP0_SS1, NULL); 380 gpio_request(GPIO_FN_SP0_SS2, NULL); 381 gpio_request(GPIO_FN_SP0_SS3, NULL); 382 383 /* RMII 0/1 (PTE, PTF) */ 384 gpio_request(GPIO_FN_RMII0_CRS_DV, NULL); 385 gpio_request(GPIO_FN_RMII0_TXD1, NULL); 386 gpio_request(GPIO_FN_RMII0_TXD0, NULL); 387 gpio_request(GPIO_FN_RMII0_TXEN, NULL); 388 gpio_request(GPIO_FN_RMII0_REFCLK, NULL); 389 gpio_request(GPIO_FN_RMII0_RXD1, NULL); 390 gpio_request(GPIO_FN_RMII0_RXD0, NULL); 391 gpio_request(GPIO_FN_RMII0_RX_ER, NULL); 392 gpio_request(GPIO_FN_RMII1_CRS_DV, NULL); 393 gpio_request(GPIO_FN_RMII1_TXD1, NULL); 394 gpio_request(GPIO_FN_RMII1_TXD0, NULL); 395 gpio_request(GPIO_FN_RMII1_TXEN, NULL); 396 gpio_request(GPIO_FN_RMII1_REFCLK, NULL); 397 gpio_request(GPIO_FN_RMII1_RXD1, NULL); 398 gpio_request(GPIO_FN_RMII1_RXD0, NULL); 399 gpio_request(GPIO_FN_RMII1_RX_ER, NULL); 400 401 /* eMMC (PTG) */ 402 gpio_request(GPIO_FN_MMCCLK, NULL); 403 gpio_request(GPIO_FN_MMCCMD, NULL); 404 gpio_request(GPIO_FN_MMCDAT7, NULL); 405 gpio_request(GPIO_FN_MMCDAT6, NULL); 406 gpio_request(GPIO_FN_MMCDAT5, NULL); 407 gpio_request(GPIO_FN_MMCDAT4, NULL); 408 gpio_request(GPIO_FN_MMCDAT3, NULL); 409 gpio_request(GPIO_FN_MMCDAT2, NULL); 410 gpio_request(GPIO_FN_MMCDAT1, NULL); 411 gpio_request(GPIO_FN_MMCDAT0, NULL); 412 413 /* LPC (PTG, PTH, PTQ, PTU) */ 414 gpio_request(GPIO_FN_SERIRQ, NULL); 415 gpio_request(GPIO_FN_LPCPD, NULL); 416 gpio_request(GPIO_FN_LDRQ, NULL); 417 gpio_request(GPIO_FN_WP, NULL); 418 gpio_request(GPIO_FN_FMS0, NULL); 419 gpio_request(GPIO_FN_LAD3, NULL); 420 gpio_request(GPIO_FN_LAD2, NULL); 421 gpio_request(GPIO_FN_LAD1, NULL); 422 gpio_request(GPIO_FN_LAD0, NULL); 423 gpio_request(GPIO_FN_LFRAME, NULL); 424 gpio_request(GPIO_FN_LRESET, NULL); 425 gpio_request(GPIO_FN_LCLK, NULL); 426 gpio_request(GPIO_FN_LGPIO7, NULL); 427 gpio_request(GPIO_FN_LGPIO6, NULL); 428 gpio_request(GPIO_FN_LGPIO5, NULL); 429 gpio_request(GPIO_FN_LGPIO4, NULL); 430 431 /* SPI1 (PTH) */ 432 gpio_request(GPIO_FN_SP1_MOSI, NULL); 433 gpio_request(GPIO_FN_SP1_MISO, NULL); 434 gpio_request(GPIO_FN_SP1_SCK, NULL); 435 gpio_request(GPIO_FN_SP1_SCK_FB, NULL); 436 gpio_request(GPIO_FN_SP1_SS0, NULL); 437 gpio_request(GPIO_FN_SP1_SS1, NULL); 438 439 /* SDHI (PTI) */ 440 gpio_request(GPIO_FN_SD_WP, NULL); 441 gpio_request(GPIO_FN_SD_CD, NULL); 442 gpio_request(GPIO_FN_SD_CLK, NULL); 443 gpio_request(GPIO_FN_SD_CMD, NULL); 444 gpio_request(GPIO_FN_SD_D3, NULL); 445 gpio_request(GPIO_FN_SD_D2, NULL); 446 gpio_request(GPIO_FN_SD_D1, NULL); 447 gpio_request(GPIO_FN_SD_D0, NULL); 448 449 /* SCIF3/4 (PTJ, PTW) */ 450 gpio_request(GPIO_FN_RTS3, NULL); 451 gpio_request(GPIO_FN_CTS3, NULL); 452 gpio_request(GPIO_FN_TXD3, NULL); 453 gpio_request(GPIO_FN_RXD3, NULL); 454 gpio_request(GPIO_FN_RTS4, NULL); 455 gpio_request(GPIO_FN_RXD4, NULL); 456 gpio_request(GPIO_FN_TXD4, NULL); 457 gpio_request(GPIO_FN_CTS4, NULL); 458 459 /* SERMUX (PTK, PTL, PTO, PTV) */ 460 gpio_request(GPIO_FN_COM2_TXD, NULL); 461 gpio_request(GPIO_FN_COM2_RXD, NULL); 462 gpio_request(GPIO_FN_COM2_RTS, NULL); 463 gpio_request(GPIO_FN_COM2_CTS, NULL); 464 gpio_request(GPIO_FN_COM2_DTR, NULL); 465 gpio_request(GPIO_FN_COM2_DSR, NULL); 466 gpio_request(GPIO_FN_COM2_DCD, NULL); 467 gpio_request(GPIO_FN_COM2_RI, NULL); 468 gpio_request(GPIO_FN_RAC_RXD, NULL); 469 gpio_request(GPIO_FN_RAC_RTS, NULL); 470 gpio_request(GPIO_FN_RAC_CTS, NULL); 471 gpio_request(GPIO_FN_RAC_DTR, NULL); 472 gpio_request(GPIO_FN_RAC_DSR, NULL); 473 gpio_request(GPIO_FN_RAC_DCD, NULL); 474 gpio_request(GPIO_FN_RAC_TXD, NULL); 475 gpio_request(GPIO_FN_COM1_TXD, NULL); 476 gpio_request(GPIO_FN_COM1_RXD, NULL); 477 gpio_request(GPIO_FN_COM1_RTS, NULL); 478 gpio_request(GPIO_FN_COM1_CTS, NULL); 479 480 writeb(0x10, 0xfe470000); /* SMR0: SerMux mode 0 */ 481 482 /* IIC (PTM, PTR, PTS) */ 483 gpio_request(GPIO_FN_SDA7, NULL); 484 gpio_request(GPIO_FN_SCL7, NULL); 485 gpio_request(GPIO_FN_SDA6, NULL); 486 gpio_request(GPIO_FN_SCL6, NULL); 487 gpio_request(GPIO_FN_SDA5, NULL); 488 gpio_request(GPIO_FN_SCL5, NULL); 489 gpio_request(GPIO_FN_SDA4, NULL); 490 gpio_request(GPIO_FN_SCL4, NULL); 491 gpio_request(GPIO_FN_SDA3, NULL); 492 gpio_request(GPIO_FN_SCL3, NULL); 493 gpio_request(GPIO_FN_SDA2, NULL); 494 gpio_request(GPIO_FN_SCL2, NULL); 495 gpio_request(GPIO_FN_SDA1, NULL); 496 gpio_request(GPIO_FN_SCL1, NULL); 497 gpio_request(GPIO_FN_SDA0, NULL); 498 gpio_request(GPIO_FN_SCL0, NULL); 499 500 /* USB (PTN) */ 501 gpio_request(GPIO_FN_VBUS_EN, NULL); 502 gpio_request(GPIO_FN_VBUS_OC, NULL); 503 504 /* SGPIO1/0 (PTN, PTO) */ 505 gpio_request(GPIO_FN_SGPIO1_CLK, NULL); 506 gpio_request(GPIO_FN_SGPIO1_LOAD, NULL); 507 gpio_request(GPIO_FN_SGPIO1_DI, NULL); 508 gpio_request(GPIO_FN_SGPIO1_DO, NULL); 509 gpio_request(GPIO_FN_SGPIO0_CLK, NULL); 510 gpio_request(GPIO_FN_SGPIO0_LOAD, NULL); 511 gpio_request(GPIO_FN_SGPIO0_DI, NULL); 512 gpio_request(GPIO_FN_SGPIO0_DO, NULL); 513 514 /* WDT (PTN) */ 515 gpio_request(GPIO_FN_SUB_CLKIN, NULL); 516 517 /* System (PTT) */ 518 gpio_request(GPIO_FN_STATUS1, NULL); 519 gpio_request(GPIO_FN_STATUS0, NULL); 520 521 /* PWMX (PTT) */ 522 gpio_request(GPIO_FN_PWMX1, NULL); 523 gpio_request(GPIO_FN_PWMX0, NULL); 524 525 /* R-SPI (PTV) */ 526 gpio_request(GPIO_FN_R_SPI_MOSI, NULL); 527 gpio_request(GPIO_FN_R_SPI_MISO, NULL); 528 gpio_request(GPIO_FN_R_SPI_RSPCK, NULL); 529 gpio_request(GPIO_FN_R_SPI_SSL0, NULL); 530 gpio_request(GPIO_FN_R_SPI_SSL1, NULL); 531 532 /* EVC (PTV, PTW) */ 533 gpio_request(GPIO_FN_EVENT7, NULL); 534 gpio_request(GPIO_FN_EVENT6, NULL); 535 gpio_request(GPIO_FN_EVENT5, NULL); 536 gpio_request(GPIO_FN_EVENT4, NULL); 537 gpio_request(GPIO_FN_EVENT3, NULL); 538 gpio_request(GPIO_FN_EVENT2, NULL); 539 gpio_request(GPIO_FN_EVENT1, NULL); 540 gpio_request(GPIO_FN_EVENT0, NULL); 541 542 /* LED for heartbeat */ 543 gpio_request(GPIO_PTU3, NULL); 544 gpio_direction_output(GPIO_PTU3, 1); 545 gpio_request(GPIO_PTU2, NULL); 546 gpio_direction_output(GPIO_PTU2, 1); 547 gpio_request(GPIO_PTU1, NULL); 548 gpio_direction_output(GPIO_PTU1, 1); 549 gpio_request(GPIO_PTU0, NULL); 550 gpio_direction_output(GPIO_PTU0, 1); 551 552 /* control for MDIO of Gigabit Ethernet */ 553 gpio_request(GPIO_PTT4, NULL); 554 gpio_direction_output(GPIO_PTT4, 1); 555 556 /* control for eMMC */ 557 gpio_request(GPIO_PTT7, NULL); /* eMMC_RST# */ 558 gpio_direction_output(GPIO_PTT7, 0); 559 gpio_request(GPIO_PTT6, NULL); /* eMMC_INDEX# */ 560 gpio_direction_output(GPIO_PTT6, 0); 561 gpio_request(GPIO_PTT5, NULL); /* eMMC_PRST# */ 562 gpio_direction_output(GPIO_PTT5, 1); 563 564 /* register SPI device information */ 565 spi_register_board_info(spi_board_info, 566 ARRAY_SIZE(spi_board_info)); 567 568 /* General platform */ 569 return platform_add_devices(sh7757lcr_devices, 570 ARRAY_SIZE(sh7757lcr_devices)); 571 } 572 arch_initcall(sh7757lcr_devices_setup); 573 574 /* Initialize IRQ setting */ 575 void __init init_sh7757lcr_IRQ(void) 576 { 577 plat_irq_setup_pins(IRQ_MODE_IRQ7654); 578 plat_irq_setup_pins(IRQ_MODE_IRQ3210); 579 } 580 581 /* Initialize the board */ 582 static void __init sh7757lcr_setup(char **cmdline_p) 583 { 584 printk(KERN_INFO "Renesas R0P7757LC0012RL support.\n"); 585 } 586 587 static int sh7757lcr_mode_pins(void) 588 { 589 int value = 0; 590 591 /* These are the factory default settings of S3 (Low active). 592 * If you change these dip switches then you will need to 593 * adjust the values below as well. 594 */ 595 value |= MODE_PIN0; /* Clock Mode: 1 */ 596 597 return value; 598 } 599 600 /* The Machine Vector */ 601 static struct sh_machine_vector mv_sh7757lcr __initmv = { 602 .mv_name = "SH7757LCR", 603 .mv_setup = sh7757lcr_setup, 604 .mv_init_irq = init_sh7757lcr_IRQ, 605 .mv_mode_pins = sh7757lcr_mode_pins, 606 }; 607 608