1 /* 2 * linux/arch/sh/boards/magicpanel/setup.c 3 * 4 * Copyright (C) 2007 Markus Brunner, Mark Jonas 5 * 6 * Magic Panel Release 2 board setup 7 * 8 * This file is subject to the terms and conditions of the GNU General Public 9 * License. See the file "COPYING" in the main directory of this archive 10 * for more details. 11 */ 12 #include <linux/init.h> 13 #include <linux/irq.h> 14 #include <linux/platform_device.h> 15 #include <linux/delay.h> 16 #include <linux/gpio.h> 17 #include <linux/mtd/mtd.h> 18 #include <linux/mtd/partitions.h> 19 #include <linux/mtd/physmap.h> 20 #include <linux/mtd/map.h> 21 #include <mach/magicpanelr2.h> 22 #include <asm/heartbeat.h> 23 #include <cpu/sh7720.h> 24 25 #define LAN9115_READY (ctrl_inl(0xA8000084UL) & 0x00000001UL) 26 27 /* Prefer cmdline over RedBoot */ 28 static const char *probes[] = { "cmdlinepart", "RedBoot", NULL }; 29 30 /* Wait until reset finished. Timeout is 100ms. */ 31 static int __init ethernet_reset_finished(void) 32 { 33 int i; 34 35 if (LAN9115_READY) 36 return 1; 37 38 for (i = 0; i < 10; ++i) { 39 mdelay(10); 40 if (LAN9115_READY) 41 return 1; 42 } 43 44 return 0; 45 } 46 47 static void __init reset_ethernet(void) 48 { 49 /* PMDR: LAN_RESET=on */ 50 CLRBITS_OUTB(0x10, PORT_PMDR); 51 52 udelay(200); 53 54 /* PMDR: LAN_RESET=off */ 55 SETBITS_OUTB(0x10, PORT_PMDR); 56 } 57 58 static void __init setup_chip_select(void) 59 { 60 /* CS2: LAN (0x08000000 - 0x0bffffff) */ 61 /* no idle cycles, normal space, 8 bit data bus */ 62 ctrl_outl(0x36db0400, CS2BCR); 63 /* (SW:1.5 WR:3 HW:1.5), ext. wait */ 64 ctrl_outl(0x000003c0, CS2WCR); 65 66 /* CS4: CAN1 (0xb0000000 - 0xb3ffffff) */ 67 /* no idle cycles, normal space, 8 bit data bus */ 68 ctrl_outl(0x00000200, CS4BCR); 69 /* (SW:1.5 WR:3 HW:1.5), ext. wait */ 70 ctrl_outl(0x00100981, CS4WCR); 71 72 /* CS5a: CAN2 (0xb4000000 - 0xb5ffffff) */ 73 /* no idle cycles, normal space, 8 bit data bus */ 74 ctrl_outl(0x00000200, CS5ABCR); 75 /* (SW:1.5 WR:3 HW:1.5), ext. wait */ 76 ctrl_outl(0x00100981, CS5AWCR); 77 78 /* CS5b: CAN3 (0xb6000000 - 0xb7ffffff) */ 79 /* no idle cycles, normal space, 8 bit data bus */ 80 ctrl_outl(0x00000200, CS5BBCR); 81 /* (SW:1.5 WR:3 HW:1.5), ext. wait */ 82 ctrl_outl(0x00100981, CS5BWCR); 83 84 /* CS6a: Rotary (0xb8000000 - 0xb9ffffff) */ 85 /* no idle cycles, normal space, 8 bit data bus */ 86 ctrl_outl(0x00000200, CS6ABCR); 87 /* (SW:1.5 WR:3 HW:1.5), no ext. wait */ 88 ctrl_outl(0x001009C1, CS6AWCR); 89 } 90 91 static void __init setup_port_multiplexing(void) 92 { 93 /* A7 GPO(LED8); A6 GPO(LED7); A5 GPO(LED6); A4 GPO(LED5); 94 * A3 GPO(LED4); A2 GPO(LED3); A1 GPO(LED2); A0 GPO(LED1); 95 */ 96 ctrl_outw(0x5555, PORT_PACR); /* 01 01 01 01 01 01 01 01 */ 97 98 /* B7 GPO(RST4); B6 GPO(RST3); B5 GPO(RST2); B4 GPO(RST1); 99 * B3 GPO(PB3); B2 GPO(PB2); B1 GPO(PB1); B0 GPO(PB0); 100 */ 101 ctrl_outw(0x5555, PORT_PBCR); /* 01 01 01 01 01 01 01 01 */ 102 103 /* C7 GPO(PC7); C6 GPO(PC6); C5 GPO(PC5); C4 GPO(PC4); 104 * C3 LCD_DATA3; C2 LCD_DATA2; C1 LCD_DATA1; C0 LCD_DATA0; 105 */ 106 ctrl_outw(0x5500, PORT_PCCR); /* 01 01 01 01 00 00 00 00 */ 107 108 /* D7 GPO(PD7); D6 GPO(PD6); D5 GPO(PD5); D4 GPO(PD4); 109 * D3 GPO(PD3); D2 GPO(PD2); D1 GPO(PD1); D0 GPO(PD0); 110 */ 111 ctrl_outw(0x5555, PORT_PDCR); /* 01 01 01 01 01 01 01 01 */ 112 113 /* E7 (x); E6 GPI(nu); E5 GPI(nu); E4 LCD_M_DISP; 114 * E3 LCD_CL1; E2 LCD_CL2; E1 LCD_DON; E0 LCD_FLM; 115 */ 116 ctrl_outw(0x3C00, PORT_PECR); /* 00 11 11 00 00 00 00 00 */ 117 118 /* F7 (x); F6 DA1(VLCD); F5 DA0(nc); F4 AN3; 119 * F3 AN2(MID_AD); F2 AN1(EARTH_AD); F1 AN0(TEMP); F0 GPI+(nc); 120 */ 121 ctrl_outw(0x0002, PORT_PFCR); /* 00 00 00 00 00 00 00 10 */ 122 123 /* G7 (x); G6 IRQ5(TOUCH_BUSY); G5 IRQ4(TOUCH_IRQ); G4 GPI(KEY2); 124 * G3 GPI(KEY1); G2 GPO(LED11); G1 GPO(LED10); G0 GPO(LED9); 125 */ 126 ctrl_outw(0x03D5, PORT_PGCR); /* 00 00 00 11 11 01 01 01 */ 127 128 /* H7 (x); H6 /RAS(BRAS); H5 /CAS(BCAS); H4 CKE(BCKE); 129 * H3 GPO(EARTH_OFF); H2 GPO(EARTH_TEST); H1 USB2_PWR; H0 USB1_PWR; 130 */ 131 ctrl_outw(0x0050, PORT_PHCR); /* 00 00 00 00 01 01 00 00 */ 132 133 /* J7 (x); J6 AUDCK; J5 ASEBRKAK; J4 AUDATA3; 134 * J3 AUDATA2; J2 AUDATA1; J1 AUDATA0; J0 AUDSYNC; 135 */ 136 ctrl_outw(0x0000, PORT_PJCR); /* 00 00 00 00 00 00 00 00 */ 137 138 /* K7 (x); K6 (x); K5 (x); K4 (x); 139 * K3 PINT7(/PWR2); K2 PINT6(/PWR1); K1 PINT5(nu); K0 PINT4(FLASH_READY) 140 */ 141 ctrl_outw(0x00FF, PORT_PKCR); /* 00 00 00 00 11 11 11 11 */ 142 143 /* L7 TRST; L6 TMS; L5 TDO; L4 TDI; 144 * L3 TCK; L2 (x); L1 (x); L0 (x); 145 */ 146 ctrl_outw(0x0000, PORT_PLCR); /* 00 00 00 00 00 00 00 00 */ 147 148 /* M7 GPO(CURRENT_SINK); M6 GPO(PWR_SWITCH); M5 GPO(LAN_SPEED); 149 * M4 GPO(LAN_RESET); M3 GPO(BUZZER); M2 GPO(LCD_BL); 150 * M1 CS5B(CAN3_CS); M0 GPI+(nc); 151 */ 152 ctrl_outw(0x5552, PORT_PMCR); /* 01 01 01 01 01 01 00 10 */ 153 154 /* CURRENT_SINK=off, PWR_SWITCH=off, LAN_SPEED=100MBit, 155 * LAN_RESET=off, BUZZER=off, LCD_BL=off 156 */ 157 #if CONFIG_SH_MAGIC_PANEL_R2_VERSION == 2 158 ctrl_outb(0x30, PORT_PMDR); 159 #elif CONFIG_SH_MAGIC_PANEL_R2_VERSION == 3 160 ctrl_outb(0xF0, PORT_PMDR); 161 #else 162 #error Unknown revision of PLATFORM_MP_R2 163 #endif 164 165 /* P7 (x); P6 (x); P5 (x); 166 * P4 GPO(nu); P3 IRQ3(LAN_IRQ); P2 IRQ2(CAN3_IRQ); 167 * P1 IRQ1(CAN2_IRQ); P0 IRQ0(CAN1_IRQ) 168 */ 169 ctrl_outw(0x0100, PORT_PPCR); /* 00 00 00 01 00 00 00 00 */ 170 ctrl_outb(0x10, PORT_PPDR); 171 172 /* R7 A25; R6 A24; R5 A23; R4 A22; 173 * R3 A21; R2 A20; R1 A19; R0 A0; 174 */ 175 gpio_request(GPIO_FN_A25, NULL); 176 gpio_request(GPIO_FN_A24, NULL); 177 gpio_request(GPIO_FN_A23, NULL); 178 gpio_request(GPIO_FN_A22, NULL); 179 gpio_request(GPIO_FN_A21, NULL); 180 gpio_request(GPIO_FN_A20, NULL); 181 gpio_request(GPIO_FN_A19, NULL); 182 gpio_request(GPIO_FN_A0, NULL); 183 184 /* S7 (x); S6 (x); S5 (x); S4 GPO(EEPROM_CS2); 185 * S3 GPO(EEPROM_CS1); S2 SIOF0_TXD; S1 SIOF0_RXD; S0 SIOF0_SCK; 186 */ 187 ctrl_outw(0x0140, PORT_PSCR); /* 00 00 00 01 01 00 00 00 */ 188 189 /* T7 (x); T6 (x); T5 (x); T4 COM1_CTS; 190 * T3 COM1_RTS; T2 COM1_TXD; T1 COM1_RXD; T0 GPO(WDOG) 191 */ 192 ctrl_outw(0x0001, PORT_PTCR); /* 00 00 00 00 00 00 00 01 */ 193 194 /* U7 (x); U6 (x); U5 (x); U4 GPI+(/AC_FAULT); 195 * U3 GPO(TOUCH_CS); U2 TOUCH_TXD; U1 TOUCH_RXD; U0 TOUCH_SCK; 196 */ 197 ctrl_outw(0x0240, PORT_PUCR); /* 00 00 00 10 01 00 00 00 */ 198 199 /* V7 (x); V6 (x); V5 (x); V4 GPO(MID2); 200 * V3 GPO(MID1); V2 CARD_TxD; V1 CARD_RxD; V0 GPI+(/BAT_FAULT); 201 */ 202 ctrl_outw(0x0142, PORT_PVCR); /* 00 00 00 01 01 00 00 10 */ 203 } 204 205 static void __init mpr2_setup(char **cmdline_p) 206 { 207 __set_io_port_base(0xa0000000); 208 209 /* set Pin Select Register A: 210 * /PCC_CD1, /PCC_CD2, PCC_BVD1, PCC_BVD2, 211 * /IOIS16, IRQ4, IRQ5, USB1d_SUSPEND 212 */ 213 ctrl_outw(0xAABC, PORT_PSELA); 214 /* set Pin Select Register B: 215 * /SCIF0_RTS, /SCIF0_CTS, LCD_VCPWC, 216 * LCD_VEPWC, IIC_SDA, IIC_SCL, Reserved 217 */ 218 ctrl_outw(0x3C00, PORT_PSELB); 219 /* set Pin Select Register C: 220 * SIOF1_SCK, SIOF1_RxD, SCIF1_RxD, SCIF1_TxD, Reserved 221 */ 222 ctrl_outw(0x0000, PORT_PSELC); 223 /* set Pin Select Register D: Reserved, SIOF1_TxD, Reserved, SIOF1_MCLK, 224 * Reserved, SIOF1_SYNC, Reserved, SCIF1_SCK, Reserved 225 */ 226 ctrl_outw(0x0000, PORT_PSELD); 227 /* set USB TxRx Control: Reserved, DRV, Reserved, USB_TRANS, USB_SEL */ 228 ctrl_outw(0x0101, PORT_UTRCTL); 229 /* set USB Clock Control: USSCS, USSTB, Reserved (HighByte always A5) */ 230 ctrl_outw(0xA5C0, PORT_UCLKCR_W); 231 232 setup_chip_select(); 233 234 setup_port_multiplexing(); 235 236 reset_ethernet(); 237 238 printk(KERN_INFO "Magic Panel Release 2 A.%i\n", 239 CONFIG_SH_MAGIC_PANEL_R2_VERSION); 240 241 if (ethernet_reset_finished() == 0) 242 printk(KERN_WARNING "Ethernet not ready\n"); 243 } 244 245 static struct resource smc911x_resources[] = { 246 [0] = { 247 .start = 0xa8000000, 248 .end = 0xabffffff, 249 .flags = IORESOURCE_MEM, 250 }, 251 [1] = { 252 .start = 35, 253 .end = 35, 254 .flags = IORESOURCE_IRQ, 255 }, 256 }; 257 258 static struct platform_device smc911x_device = { 259 .name = "smc911x", 260 .id = -1, 261 .num_resources = ARRAY_SIZE(smc911x_resources), 262 .resource = smc911x_resources, 263 }; 264 265 static struct resource heartbeat_resources[] = { 266 [0] = { 267 .start = PA_LED, 268 .end = PA_LED, 269 .flags = IORESOURCE_MEM, 270 }, 271 }; 272 273 static struct heartbeat_data heartbeat_data = { 274 .flags = HEARTBEAT_INVERTED, 275 }; 276 277 static struct platform_device heartbeat_device = { 278 .name = "heartbeat", 279 .id = -1, 280 .dev = { 281 .platform_data = &heartbeat_data, 282 }, 283 .num_resources = ARRAY_SIZE(heartbeat_resources), 284 .resource = heartbeat_resources, 285 }; 286 287 static struct mtd_partition *parsed_partitions; 288 289 static struct mtd_partition mpr2_partitions[] = { 290 /* Reserved for bootloader, read-only */ 291 { 292 .name = "Bootloader", 293 .offset = 0x00000000UL, 294 .size = MPR2_MTD_BOOTLOADER_SIZE, 295 .mask_flags = MTD_WRITEABLE, 296 }, 297 /* Reserved for kernel image */ 298 { 299 .name = "Kernel", 300 .offset = MTDPART_OFS_NXTBLK, 301 .size = MPR2_MTD_KERNEL_SIZE, 302 }, 303 /* Rest is used for Flash FS */ 304 { 305 .name = "Flash_FS", 306 .offset = MTDPART_OFS_NXTBLK, 307 .size = MTDPART_SIZ_FULL, 308 } 309 }; 310 311 static struct physmap_flash_data flash_data = { 312 .width = 2, 313 }; 314 315 static struct resource flash_resource = { 316 .start = 0x00000000, 317 .end = 0x2000000UL, 318 .flags = IORESOURCE_MEM, 319 }; 320 321 static struct platform_device flash_device = { 322 .name = "physmap-flash", 323 .id = -1, 324 .resource = &flash_resource, 325 .num_resources = 1, 326 .dev = { 327 .platform_data = &flash_data, 328 }, 329 }; 330 331 static struct mtd_info *flash_mtd; 332 333 static struct map_info mpr2_flash_map = { 334 .name = "Magic Panel R2 Flash", 335 .size = 0x2000000UL, 336 .bankwidth = 2, 337 }; 338 339 static void __init set_mtd_partitions(void) 340 { 341 int nr_parts = 0; 342 343 simple_map_init(&mpr2_flash_map); 344 flash_mtd = do_map_probe("cfi_probe", &mpr2_flash_map); 345 nr_parts = parse_mtd_partitions(flash_mtd, probes, 346 &parsed_partitions, 0); 347 /* If there is no partition table, used the hard coded table */ 348 if (nr_parts <= 0) { 349 flash_data.parts = mpr2_partitions; 350 flash_data.nr_parts = ARRAY_SIZE(mpr2_partitions); 351 } else { 352 flash_data.nr_parts = nr_parts; 353 flash_data.parts = parsed_partitions; 354 } 355 } 356 357 /* 358 * Add all resources to the platform_device 359 */ 360 361 static struct platform_device *mpr2_devices[] __initdata = { 362 &heartbeat_device, 363 &smc911x_device, 364 &flash_device, 365 }; 366 367 368 static int __init mpr2_devices_setup(void) 369 { 370 set_mtd_partitions(); 371 return platform_add_devices(mpr2_devices, ARRAY_SIZE(mpr2_devices)); 372 } 373 device_initcall(mpr2_devices_setup); 374 375 /* 376 * Initialize IRQ setting 377 */ 378 static void __init init_mpr2_IRQ(void) 379 { 380 plat_irq_setup_pins(IRQ_MODE_IRQ); /* install handlers for IRQ0-5 */ 381 382 set_irq_type(32, IRQ_TYPE_LEVEL_LOW); /* IRQ0 CAN1 */ 383 set_irq_type(33, IRQ_TYPE_LEVEL_LOW); /* IRQ1 CAN2 */ 384 set_irq_type(34, IRQ_TYPE_LEVEL_LOW); /* IRQ2 CAN3 */ 385 set_irq_type(35, IRQ_TYPE_LEVEL_LOW); /* IRQ3 SMSC9115 */ 386 set_irq_type(36, IRQ_TYPE_EDGE_RISING); /* IRQ4 touchscreen */ 387 set_irq_type(37, IRQ_TYPE_EDGE_FALLING); /* IRQ5 touchscreen */ 388 389 intc_set_priority(32, 13); /* IRQ0 CAN1 */ 390 intc_set_priority(33, 13); /* IRQ0 CAN2 */ 391 intc_set_priority(34, 13); /* IRQ0 CAN3 */ 392 intc_set_priority(35, 6); /* IRQ3 SMSC9115 */ 393 } 394 395 /* 396 * The Machine Vector 397 */ 398 399 static struct sh_machine_vector mv_mpr2 __initmv = { 400 .mv_name = "mpr2", 401 .mv_setup = mpr2_setup, 402 .mv_init_irq = init_mpr2_IRQ, 403 }; 404