1 /* 2 * linux/arch/sh/boards/magicpanel/setup.c 3 * 4 * Copyright (C) 2007 Markus Brunner, Mark Jonas 5 * 6 * Magic Panel Release 2 board setup 7 * 8 * This file is subject to the terms and conditions of the GNU General Public 9 * License. See the file "COPYING" in the main directory of this archive 10 * for more details. 11 */ 12 #include <linux/init.h> 13 #include <linux/irq.h> 14 #include <linux/platform_device.h> 15 #include <linux/delay.h> 16 #include <linux/gpio.h> 17 #include <linux/smsc911x.h> 18 #include <linux/mtd/mtd.h> 19 #include <linux/mtd/partitions.h> 20 #include <linux/mtd/physmap.h> 21 #include <linux/mtd/map.h> 22 #include <linux/sh_intc.h> 23 #include <mach/magicpanelr2.h> 24 #include <asm/heartbeat.h> 25 #include <cpu/sh7720.h> 26 27 #define LAN9115_READY (__raw_readl(0xA8000084UL) & 0x00000001UL) 28 29 /* Wait until reset finished. Timeout is 100ms. */ 30 static int __init ethernet_reset_finished(void) 31 { 32 int i; 33 34 if (LAN9115_READY) 35 return 1; 36 37 for (i = 0; i < 10; ++i) { 38 mdelay(10); 39 if (LAN9115_READY) 40 return 1; 41 } 42 43 return 0; 44 } 45 46 static void __init reset_ethernet(void) 47 { 48 /* PMDR: LAN_RESET=on */ 49 CLRBITS_OUTB(0x10, PORT_PMDR); 50 51 udelay(200); 52 53 /* PMDR: LAN_RESET=off */ 54 SETBITS_OUTB(0x10, PORT_PMDR); 55 } 56 57 static void __init setup_chip_select(void) 58 { 59 /* CS2: LAN (0x08000000 - 0x0bffffff) */ 60 /* no idle cycles, normal space, 8 bit data bus */ 61 __raw_writel(0x36db0400, CS2BCR); 62 /* (SW:1.5 WR:3 HW:1.5), ext. wait */ 63 __raw_writel(0x000003c0, CS2WCR); 64 65 /* CS4: CAN1 (0xb0000000 - 0xb3ffffff) */ 66 /* no idle cycles, normal space, 8 bit data bus */ 67 __raw_writel(0x00000200, CS4BCR); 68 /* (SW:1.5 WR:3 HW:1.5), ext. wait */ 69 __raw_writel(0x00100981, CS4WCR); 70 71 /* CS5a: CAN2 (0xb4000000 - 0xb5ffffff) */ 72 /* no idle cycles, normal space, 8 bit data bus */ 73 __raw_writel(0x00000200, CS5ABCR); 74 /* (SW:1.5 WR:3 HW:1.5), ext. wait */ 75 __raw_writel(0x00100981, CS5AWCR); 76 77 /* CS5b: CAN3 (0xb6000000 - 0xb7ffffff) */ 78 /* no idle cycles, normal space, 8 bit data bus */ 79 __raw_writel(0x00000200, CS5BBCR); 80 /* (SW:1.5 WR:3 HW:1.5), ext. wait */ 81 __raw_writel(0x00100981, CS5BWCR); 82 83 /* CS6a: Rotary (0xb8000000 - 0xb9ffffff) */ 84 /* no idle cycles, normal space, 8 bit data bus */ 85 __raw_writel(0x00000200, CS6ABCR); 86 /* (SW:1.5 WR:3 HW:1.5), no ext. wait */ 87 __raw_writel(0x001009C1, CS6AWCR); 88 } 89 90 static void __init setup_port_multiplexing(void) 91 { 92 /* A7 GPO(LED8); A6 GPO(LED7); A5 GPO(LED6); A4 GPO(LED5); 93 * A3 GPO(LED4); A2 GPO(LED3); A1 GPO(LED2); A0 GPO(LED1); 94 */ 95 __raw_writew(0x5555, PORT_PACR); /* 01 01 01 01 01 01 01 01 */ 96 97 /* B7 GPO(RST4); B6 GPO(RST3); B5 GPO(RST2); B4 GPO(RST1); 98 * B3 GPO(PB3); B2 GPO(PB2); B1 GPO(PB1); B0 GPO(PB0); 99 */ 100 __raw_writew(0x5555, PORT_PBCR); /* 01 01 01 01 01 01 01 01 */ 101 102 /* C7 GPO(PC7); C6 GPO(PC6); C5 GPO(PC5); C4 GPO(PC4); 103 * C3 LCD_DATA3; C2 LCD_DATA2; C1 LCD_DATA1; C0 LCD_DATA0; 104 */ 105 __raw_writew(0x5500, PORT_PCCR); /* 01 01 01 01 00 00 00 00 */ 106 107 /* D7 GPO(PD7); D6 GPO(PD6); D5 GPO(PD5); D4 GPO(PD4); 108 * D3 GPO(PD3); D2 GPO(PD2); D1 GPO(PD1); D0 GPO(PD0); 109 */ 110 __raw_writew(0x5555, PORT_PDCR); /* 01 01 01 01 01 01 01 01 */ 111 112 /* E7 (x); E6 GPI(nu); E5 GPI(nu); E4 LCD_M_DISP; 113 * E3 LCD_CL1; E2 LCD_CL2; E1 LCD_DON; E0 LCD_FLM; 114 */ 115 __raw_writew(0x3C00, PORT_PECR); /* 00 11 11 00 00 00 00 00 */ 116 117 /* F7 (x); F6 DA1(VLCD); F5 DA0(nc); F4 AN3; 118 * F3 AN2(MID_AD); F2 AN1(EARTH_AD); F1 AN0(TEMP); F0 GPI+(nc); 119 */ 120 __raw_writew(0x0002, PORT_PFCR); /* 00 00 00 00 00 00 00 10 */ 121 122 /* G7 (x); G6 IRQ5(TOUCH_BUSY); G5 IRQ4(TOUCH_IRQ); G4 GPI(KEY2); 123 * G3 GPI(KEY1); G2 GPO(LED11); G1 GPO(LED10); G0 GPO(LED9); 124 */ 125 __raw_writew(0x03D5, PORT_PGCR); /* 00 00 00 11 11 01 01 01 */ 126 127 /* H7 (x); H6 /RAS(BRAS); H5 /CAS(BCAS); H4 CKE(BCKE); 128 * H3 GPO(EARTH_OFF); H2 GPO(EARTH_TEST); H1 USB2_PWR; H0 USB1_PWR; 129 */ 130 __raw_writew(0x0050, PORT_PHCR); /* 00 00 00 00 01 01 00 00 */ 131 132 /* J7 (x); J6 AUDCK; J5 ASEBRKAK; J4 AUDATA3; 133 * J3 AUDATA2; J2 AUDATA1; J1 AUDATA0; J0 AUDSYNC; 134 */ 135 __raw_writew(0x0000, PORT_PJCR); /* 00 00 00 00 00 00 00 00 */ 136 137 /* K7 (x); K6 (x); K5 (x); K4 (x); 138 * K3 PINT7(/PWR2); K2 PINT6(/PWR1); K1 PINT5(nu); K0 PINT4(FLASH_READY) 139 */ 140 __raw_writew(0x00FF, PORT_PKCR); /* 00 00 00 00 11 11 11 11 */ 141 142 /* L7 TRST; L6 TMS; L5 TDO; L4 TDI; 143 * L3 TCK; L2 (x); L1 (x); L0 (x); 144 */ 145 __raw_writew(0x0000, PORT_PLCR); /* 00 00 00 00 00 00 00 00 */ 146 147 /* M7 GPO(CURRENT_SINK); M6 GPO(PWR_SWITCH); M5 GPO(LAN_SPEED); 148 * M4 GPO(LAN_RESET); M3 GPO(BUZZER); M2 GPO(LCD_BL); 149 * M1 CS5B(CAN3_CS); M0 GPI+(nc); 150 */ 151 __raw_writew(0x5552, PORT_PMCR); /* 01 01 01 01 01 01 00 10 */ 152 153 /* CURRENT_SINK=off, PWR_SWITCH=off, LAN_SPEED=100MBit, 154 * LAN_RESET=off, BUZZER=off, LCD_BL=off 155 */ 156 #if CONFIG_SH_MAGIC_PANEL_R2_VERSION == 2 157 __raw_writeb(0x30, PORT_PMDR); 158 #elif CONFIG_SH_MAGIC_PANEL_R2_VERSION == 3 159 __raw_writeb(0xF0, PORT_PMDR); 160 #else 161 #error Unknown revision of PLATFORM_MP_R2 162 #endif 163 164 /* P7 (x); P6 (x); P5 (x); 165 * P4 GPO(nu); P3 IRQ3(LAN_IRQ); P2 IRQ2(CAN3_IRQ); 166 * P1 IRQ1(CAN2_IRQ); P0 IRQ0(CAN1_IRQ) 167 */ 168 __raw_writew(0x0100, PORT_PPCR); /* 00 00 00 01 00 00 00 00 */ 169 __raw_writeb(0x10, PORT_PPDR); 170 171 /* R7 A25; R6 A24; R5 A23; R4 A22; 172 * R3 A21; R2 A20; R1 A19; R0 A0; 173 */ 174 gpio_request(GPIO_FN_A25, NULL); 175 gpio_request(GPIO_FN_A24, NULL); 176 gpio_request(GPIO_FN_A23, NULL); 177 gpio_request(GPIO_FN_A22, NULL); 178 gpio_request(GPIO_FN_A21, NULL); 179 gpio_request(GPIO_FN_A20, NULL); 180 gpio_request(GPIO_FN_A19, NULL); 181 gpio_request(GPIO_FN_A0, NULL); 182 183 /* S7 (x); S6 (x); S5 (x); S4 GPO(EEPROM_CS2); 184 * S3 GPO(EEPROM_CS1); S2 SIOF0_TXD; S1 SIOF0_RXD; S0 SIOF0_SCK; 185 */ 186 __raw_writew(0x0140, PORT_PSCR); /* 00 00 00 01 01 00 00 00 */ 187 188 /* T7 (x); T6 (x); T5 (x); T4 COM1_CTS; 189 * T3 COM1_RTS; T2 COM1_TXD; T1 COM1_RXD; T0 GPO(WDOG) 190 */ 191 __raw_writew(0x0001, PORT_PTCR); /* 00 00 00 00 00 00 00 01 */ 192 193 /* U7 (x); U6 (x); U5 (x); U4 GPI+(/AC_FAULT); 194 * U3 GPO(TOUCH_CS); U2 TOUCH_TXD; U1 TOUCH_RXD; U0 TOUCH_SCK; 195 */ 196 __raw_writew(0x0240, PORT_PUCR); /* 00 00 00 10 01 00 00 00 */ 197 198 /* V7 (x); V6 (x); V5 (x); V4 GPO(MID2); 199 * V3 GPO(MID1); V2 CARD_TxD; V1 CARD_RxD; V0 GPI+(/BAT_FAULT); 200 */ 201 __raw_writew(0x0142, PORT_PVCR); /* 00 00 00 01 01 00 00 10 */ 202 } 203 204 static void __init mpr2_setup(char **cmdline_p) 205 { 206 /* set Pin Select Register A: 207 * /PCC_CD1, /PCC_CD2, PCC_BVD1, PCC_BVD2, 208 * /IOIS16, IRQ4, IRQ5, USB1d_SUSPEND 209 */ 210 __raw_writew(0xAABC, PORT_PSELA); 211 /* set Pin Select Register B: 212 * /SCIF0_RTS, /SCIF0_CTS, LCD_VCPWC, 213 * LCD_VEPWC, IIC_SDA, IIC_SCL, Reserved 214 */ 215 __raw_writew(0x3C00, PORT_PSELB); 216 /* set Pin Select Register C: 217 * SIOF1_SCK, SIOF1_RxD, SCIF1_RxD, SCIF1_TxD, Reserved 218 */ 219 __raw_writew(0x0000, PORT_PSELC); 220 /* set Pin Select Register D: Reserved, SIOF1_TxD, Reserved, SIOF1_MCLK, 221 * Reserved, SIOF1_SYNC, Reserved, SCIF1_SCK, Reserved 222 */ 223 __raw_writew(0x0000, PORT_PSELD); 224 /* set USB TxRx Control: Reserved, DRV, Reserved, USB_TRANS, USB_SEL */ 225 __raw_writew(0x0101, PORT_UTRCTL); 226 /* set USB Clock Control: USSCS, USSTB, Reserved (HighByte always A5) */ 227 __raw_writew(0xA5C0, PORT_UCLKCR_W); 228 229 setup_chip_select(); 230 231 setup_port_multiplexing(); 232 233 reset_ethernet(); 234 235 printk(KERN_INFO "Magic Panel Release 2 A.%i\n", 236 CONFIG_SH_MAGIC_PANEL_R2_VERSION); 237 238 if (ethernet_reset_finished() == 0) 239 printk(KERN_WARNING "Ethernet not ready\n"); 240 } 241 242 static struct resource smsc911x_resources[] = { 243 [0] = { 244 .start = 0xa8000000, 245 .end = 0xabffffff, 246 .flags = IORESOURCE_MEM, 247 }, 248 [1] = { 249 .start = evt2irq(0x660), 250 .end = evt2irq(0x660), 251 .flags = IORESOURCE_IRQ, 252 }, 253 }; 254 255 static struct smsc911x_platform_config smsc911x_config = { 256 .phy_interface = PHY_INTERFACE_MODE_MII, 257 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, 258 .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN, 259 .flags = SMSC911X_USE_32BIT, 260 }; 261 262 static struct platform_device smsc911x_device = { 263 .name = "smsc911x", 264 .id = -1, 265 .num_resources = ARRAY_SIZE(smsc911x_resources), 266 .resource = smsc911x_resources, 267 .dev = { 268 .platform_data = &smsc911x_config, 269 }, 270 }; 271 272 static struct resource heartbeat_resources[] = { 273 [0] = { 274 .start = PA_LED, 275 .end = PA_LED, 276 .flags = IORESOURCE_MEM, 277 }, 278 }; 279 280 static struct heartbeat_data heartbeat_data = { 281 .flags = HEARTBEAT_INVERTED, 282 }; 283 284 static struct platform_device heartbeat_device = { 285 .name = "heartbeat", 286 .id = -1, 287 .dev = { 288 .platform_data = &heartbeat_data, 289 }, 290 .num_resources = ARRAY_SIZE(heartbeat_resources), 291 .resource = heartbeat_resources, 292 }; 293 294 static struct mtd_partition mpr2_partitions[] = { 295 /* Reserved for bootloader, read-only */ 296 { 297 .name = "Bootloader", 298 .offset = 0x00000000UL, 299 .size = MPR2_MTD_BOOTLOADER_SIZE, 300 .mask_flags = MTD_WRITEABLE, 301 }, 302 /* Reserved for kernel image */ 303 { 304 .name = "Kernel", 305 .offset = MTDPART_OFS_NXTBLK, 306 .size = MPR2_MTD_KERNEL_SIZE, 307 }, 308 /* Rest is used for Flash FS */ 309 { 310 .name = "Flash_FS", 311 .offset = MTDPART_OFS_NXTBLK, 312 .size = MTDPART_SIZ_FULL, 313 } 314 }; 315 316 static struct physmap_flash_data flash_data = { 317 .parts = mpr2_partitions, 318 .nr_parts = ARRAY_SIZE(mpr2_partitions), 319 .width = 2, 320 }; 321 322 static struct resource flash_resource = { 323 .start = 0x00000000, 324 .end = 0x2000000UL, 325 .flags = IORESOURCE_MEM, 326 }; 327 328 static struct platform_device flash_device = { 329 .name = "physmap-flash", 330 .id = -1, 331 .resource = &flash_resource, 332 .num_resources = 1, 333 .dev = { 334 .platform_data = &flash_data, 335 }, 336 }; 337 338 /* 339 * Add all resources to the platform_device 340 */ 341 342 static struct platform_device *mpr2_devices[] __initdata = { 343 &heartbeat_device, 344 &smsc911x_device, 345 &flash_device, 346 }; 347 348 349 static int __init mpr2_devices_setup(void) 350 { 351 return platform_add_devices(mpr2_devices, ARRAY_SIZE(mpr2_devices)); 352 } 353 device_initcall(mpr2_devices_setup); 354 355 /* 356 * Initialize IRQ setting 357 */ 358 static void __init init_mpr2_IRQ(void) 359 { 360 plat_irq_setup_pins(IRQ_MODE_IRQ); /* install handlers for IRQ0-5 */ 361 362 irq_set_irq_type(evt2irq(0x600), IRQ_TYPE_LEVEL_LOW); /* IRQ0 CAN1 */ 363 irq_set_irq_type(evt2irq(0x620), IRQ_TYPE_LEVEL_LOW); /* IRQ1 CAN2 */ 364 irq_set_irq_type(evt2irq(0x640), IRQ_TYPE_LEVEL_LOW); /* IRQ2 CAN3 */ 365 irq_set_irq_type(evt2irq(0x660), IRQ_TYPE_LEVEL_LOW); /* IRQ3 SMSC9115 */ 366 irq_set_irq_type(evt2irq(0x680), IRQ_TYPE_EDGE_RISING); /* IRQ4 touchscreen */ 367 irq_set_irq_type(evt2irq(0x6a0), IRQ_TYPE_EDGE_FALLING); /* IRQ5 touchscreen */ 368 369 intc_set_priority(evt2irq(0x600), 13); /* IRQ0 CAN1 */ 370 intc_set_priority(evt2irq(0x620), 13); /* IRQ0 CAN2 */ 371 intc_set_priority(evt2irq(0x640), 13); /* IRQ0 CAN3 */ 372 intc_set_priority(evt2irq(0x660), 6); /* IRQ3 SMSC9115 */ 373 } 374 375 /* 376 * The Machine Vector 377 */ 378 379 static struct sh_machine_vector mv_mpr2 __initmv = { 380 .mv_name = "mpr2", 381 .mv_setup = mpr2_setup, 382 .mv_init_irq = init_mpr2_IRQ, 383 }; 384