1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright IBM Corp. 2012 4 * 5 * Author(s): 6 * Jan Glauber <jang@linux.vnet.ibm.com> 7 */ 8 9 #define KMSG_COMPONENT "zpci" 10 #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt 11 12 #include <linux/compat.h> 13 #include <linux/kernel.h> 14 #include <linux/miscdevice.h> 15 #include <linux/slab.h> 16 #include <linux/err.h> 17 #include <linux/delay.h> 18 #include <linux/pci.h> 19 #include <linux/uaccess.h> 20 #include <asm/asm-extable.h> 21 #include <asm/pci_debug.h> 22 #include <asm/pci_clp.h> 23 #include <asm/clp.h> 24 #include <uapi/asm/clp.h> 25 26 bool zpci_unique_uid; 27 28 void update_uid_checking(bool new) 29 { 30 if (zpci_unique_uid != new) 31 zpci_dbg(1, "uid checking:%d\n", new); 32 33 zpci_unique_uid = new; 34 } 35 36 static inline void zpci_err_clp(unsigned int rsp, int rc) 37 { 38 struct { 39 unsigned int rsp; 40 int rc; 41 } __packed data = {rsp, rc}; 42 43 zpci_err_hex(&data, sizeof(data)); 44 } 45 46 /* 47 * Call Logical Processor with c=1, lps=0 and command 1 48 * to get the bit mask of installed logical processors 49 */ 50 static inline int clp_get_ilp(unsigned long *ilp) 51 { 52 unsigned long mask; 53 int cc = 3; 54 55 asm volatile ( 56 " .insn rrf,0xb9a00000,%[mask],%[cmd],8,0\n" 57 "0: ipm %[cc]\n" 58 " srl %[cc],28\n" 59 "1:\n" 60 EX_TABLE(0b, 1b) 61 : [cc] "+d" (cc), [mask] "=d" (mask) : [cmd] "a" (1) 62 : "cc"); 63 *ilp = mask; 64 return cc; 65 } 66 67 /* 68 * Call Logical Processor with c=0, the give constant lps and an lpcb request. 69 */ 70 static __always_inline int clp_req(void *data, unsigned int lps) 71 { 72 struct { u8 _[CLP_BLK_SIZE]; } *req = data; 73 u64 ignored; 74 int cc = 3; 75 76 asm volatile ( 77 " .insn rrf,0xb9a00000,%[ign],%[req],0,%[lps]\n" 78 "0: ipm %[cc]\n" 79 " srl %[cc],28\n" 80 "1:\n" 81 EX_TABLE(0b, 1b) 82 : [cc] "+d" (cc), [ign] "=d" (ignored), "+m" (*req) 83 : [req] "a" (req), [lps] "i" (lps) 84 : "cc"); 85 return cc; 86 } 87 88 static void *clp_alloc_block(gfp_t gfp_mask) 89 { 90 return (void *) __get_free_pages(gfp_mask, get_order(CLP_BLK_SIZE)); 91 } 92 93 static void clp_free_block(void *ptr) 94 { 95 free_pages((unsigned long) ptr, get_order(CLP_BLK_SIZE)); 96 } 97 98 static void clp_store_query_pci_fngrp(struct zpci_dev *zdev, 99 struct clp_rsp_query_pci_grp *response) 100 { 101 zdev->tlb_refresh = response->refresh; 102 zdev->dma_mask = response->dasm; 103 zdev->msi_addr = response->msia; 104 zdev->max_msi = response->noi; 105 zdev->fmb_update = response->mui; 106 zdev->version = response->version; 107 108 switch (response->version) { 109 case 1: 110 zdev->max_bus_speed = PCIE_SPEED_5_0GT; 111 break; 112 default: 113 zdev->max_bus_speed = PCI_SPEED_UNKNOWN; 114 break; 115 } 116 } 117 118 static int clp_query_pci_fngrp(struct zpci_dev *zdev, u8 pfgid) 119 { 120 struct clp_req_rsp_query_pci_grp *rrb; 121 int rc; 122 123 rrb = clp_alloc_block(GFP_KERNEL); 124 if (!rrb) 125 return -ENOMEM; 126 127 memset(rrb, 0, sizeof(*rrb)); 128 rrb->request.hdr.len = sizeof(rrb->request); 129 rrb->request.hdr.cmd = CLP_QUERY_PCI_FNGRP; 130 rrb->response.hdr.len = sizeof(rrb->response); 131 rrb->request.pfgid = pfgid; 132 133 rc = clp_req(rrb, CLP_LPS_PCI); 134 if (!rc && rrb->response.hdr.rsp == CLP_RC_OK) 135 clp_store_query_pci_fngrp(zdev, &rrb->response); 136 else { 137 zpci_err("Q PCI FGRP:\n"); 138 zpci_err_clp(rrb->response.hdr.rsp, rc); 139 rc = -EIO; 140 } 141 clp_free_block(rrb); 142 return rc; 143 } 144 145 static int clp_store_query_pci_fn(struct zpci_dev *zdev, 146 struct clp_rsp_query_pci *response) 147 { 148 int i; 149 150 for (i = 0; i < PCI_STD_NUM_BARS; i++) { 151 zdev->bars[i].val = le32_to_cpu(response->bar[i]); 152 zdev->bars[i].size = response->bar_size[i]; 153 } 154 zdev->start_dma = response->sdma; 155 zdev->end_dma = response->edma; 156 zdev->pchid = response->pchid; 157 zdev->pfgid = response->pfgid; 158 zdev->pft = response->pft; 159 zdev->vfn = response->vfn; 160 zdev->port = response->port; 161 zdev->uid = response->uid; 162 zdev->fmb_length = sizeof(u32) * response->fmb_len; 163 zdev->rid_available = response->rid_avail; 164 zdev->is_physfn = response->is_physfn; 165 if (!s390_pci_no_rid && zdev->rid_available) 166 zdev->devfn = response->rid & ZPCI_RID_MASK_DEVFN; 167 168 memcpy(zdev->pfip, response->pfip, sizeof(zdev->pfip)); 169 if (response->util_str_avail) { 170 memcpy(zdev->util_str, response->util_str, 171 sizeof(zdev->util_str)); 172 zdev->util_str_avail = 1; 173 } 174 zdev->mio_capable = response->mio_addr_avail; 175 for (i = 0; i < PCI_STD_NUM_BARS; i++) { 176 if (!(response->mio.valid & (1 << (PCI_STD_NUM_BARS - i - 1)))) 177 continue; 178 179 zdev->bars[i].mio_wb = (void __iomem *) response->mio.addr[i].wb; 180 zdev->bars[i].mio_wt = (void __iomem *) response->mio.addr[i].wt; 181 } 182 return 0; 183 } 184 185 int clp_query_pci_fn(struct zpci_dev *zdev) 186 { 187 struct clp_req_rsp_query_pci *rrb; 188 int rc; 189 190 rrb = clp_alloc_block(GFP_KERNEL); 191 if (!rrb) 192 return -ENOMEM; 193 194 memset(rrb, 0, sizeof(*rrb)); 195 rrb->request.hdr.len = sizeof(rrb->request); 196 rrb->request.hdr.cmd = CLP_QUERY_PCI_FN; 197 rrb->response.hdr.len = sizeof(rrb->response); 198 rrb->request.fh = zdev->fh; 199 200 rc = clp_req(rrb, CLP_LPS_PCI); 201 if (!rc && rrb->response.hdr.rsp == CLP_RC_OK) { 202 rc = clp_store_query_pci_fn(zdev, &rrb->response); 203 if (rc) 204 goto out; 205 rc = clp_query_pci_fngrp(zdev, rrb->response.pfgid); 206 } else { 207 zpci_err("Q PCI FN:\n"); 208 zpci_err_clp(rrb->response.hdr.rsp, rc); 209 rc = -EIO; 210 } 211 out: 212 clp_free_block(rrb); 213 return rc; 214 } 215 216 /** 217 * clp_set_pci_fn() - Execute a command on a PCI function 218 * @zdev: Function that will be affected 219 * @fh: Out parameter for updated function handle 220 * @nr_dma_as: DMA address space number 221 * @command: The command code to execute 222 * 223 * Returns: 0 on success, < 0 for Linux errors (e.g. -ENOMEM), and 224 * > 0 for non-success platform responses 225 */ 226 static int clp_set_pci_fn(struct zpci_dev *zdev, u32 *fh, u8 nr_dma_as, u8 command) 227 { 228 struct clp_req_rsp_set_pci *rrb; 229 int rc, retries = 100; 230 231 *fh = 0; 232 rrb = clp_alloc_block(GFP_KERNEL); 233 if (!rrb) 234 return -ENOMEM; 235 236 do { 237 memset(rrb, 0, sizeof(*rrb)); 238 rrb->request.hdr.len = sizeof(rrb->request); 239 rrb->request.hdr.cmd = CLP_SET_PCI_FN; 240 rrb->response.hdr.len = sizeof(rrb->response); 241 rrb->request.fh = zdev->fh; 242 rrb->request.oc = command; 243 rrb->request.ndas = nr_dma_as; 244 245 rc = clp_req(rrb, CLP_LPS_PCI); 246 if (rrb->response.hdr.rsp == CLP_RC_SETPCIFN_BUSY) { 247 retries--; 248 if (retries < 0) 249 break; 250 msleep(20); 251 } 252 } while (rrb->response.hdr.rsp == CLP_RC_SETPCIFN_BUSY); 253 254 if (!rc && rrb->response.hdr.rsp == CLP_RC_OK) { 255 *fh = rrb->response.fh; 256 } else { 257 zpci_err("Set PCI FN:\n"); 258 zpci_err_clp(rrb->response.hdr.rsp, rc); 259 if (!rc) 260 rc = rrb->response.hdr.rsp; 261 } 262 clp_free_block(rrb); 263 return rc; 264 } 265 266 int clp_setup_writeback_mio(void) 267 { 268 struct clp_req_rsp_slpc_pci *rrb; 269 u8 wb_bit_pos; 270 int rc; 271 272 rrb = clp_alloc_block(GFP_KERNEL); 273 if (!rrb) 274 return -ENOMEM; 275 276 memset(rrb, 0, sizeof(*rrb)); 277 rrb->request.hdr.len = sizeof(rrb->request); 278 rrb->request.hdr.cmd = CLP_SLPC; 279 rrb->response.hdr.len = sizeof(rrb->response); 280 281 rc = clp_req(rrb, CLP_LPS_PCI); 282 if (!rc && rrb->response.hdr.rsp == CLP_RC_OK) { 283 if (rrb->response.vwb) { 284 wb_bit_pos = rrb->response.mio_wb; 285 set_bit_inv(wb_bit_pos, &mio_wb_bit_mask); 286 zpci_dbg(3, "wb bit: %d\n", wb_bit_pos); 287 } else { 288 zpci_dbg(3, "wb bit: n.a.\n"); 289 } 290 291 } else { 292 zpci_err("SLPC PCI:\n"); 293 zpci_err_clp(rrb->response.hdr.rsp, rc); 294 rc = -EIO; 295 } 296 clp_free_block(rrb); 297 return rc; 298 } 299 300 int clp_enable_fh(struct zpci_dev *zdev, u32 *fh, u8 nr_dma_as) 301 { 302 int rc; 303 304 rc = clp_set_pci_fn(zdev, fh, nr_dma_as, CLP_SET_ENABLE_PCI_FN); 305 zpci_dbg(3, "ena fid:%x, fh:%x, rc:%d\n", zdev->fid, *fh, rc); 306 if (!rc && zpci_use_mio(zdev)) { 307 rc = clp_set_pci_fn(zdev, fh, nr_dma_as, CLP_SET_ENABLE_MIO); 308 zpci_dbg(3, "ena mio fid:%x, fh:%x, rc:%d\n", 309 zdev->fid, *fh, rc); 310 if (rc) 311 clp_disable_fh(zdev, fh); 312 } 313 return rc; 314 } 315 316 int clp_disable_fh(struct zpci_dev *zdev, u32 *fh) 317 { 318 int rc; 319 320 if (!zdev_enabled(zdev)) 321 return 0; 322 323 rc = clp_set_pci_fn(zdev, fh, 0, CLP_SET_DISABLE_PCI_FN); 324 zpci_dbg(3, "dis fid:%x, fh:%x, rc:%d\n", zdev->fid, *fh, rc); 325 return rc; 326 } 327 328 static int clp_list_pci_req(struct clp_req_rsp_list_pci *rrb, 329 u64 *resume_token, int *nentries) 330 { 331 int rc; 332 333 memset(rrb, 0, sizeof(*rrb)); 334 rrb->request.hdr.len = sizeof(rrb->request); 335 rrb->request.hdr.cmd = CLP_LIST_PCI; 336 /* store as many entries as possible */ 337 rrb->response.hdr.len = CLP_BLK_SIZE - LIST_PCI_HDR_LEN; 338 rrb->request.resume_token = *resume_token; 339 340 /* Get PCI function handle list */ 341 rc = clp_req(rrb, CLP_LPS_PCI); 342 if (rc || rrb->response.hdr.rsp != CLP_RC_OK) { 343 zpci_err("List PCI FN:\n"); 344 zpci_err_clp(rrb->response.hdr.rsp, rc); 345 return -EIO; 346 } 347 348 update_uid_checking(rrb->response.uid_checking); 349 WARN_ON_ONCE(rrb->response.entry_size != 350 sizeof(struct clp_fh_list_entry)); 351 352 *nentries = (rrb->response.hdr.len - LIST_PCI_HDR_LEN) / 353 rrb->response.entry_size; 354 *resume_token = rrb->response.resume_token; 355 356 return rc; 357 } 358 359 static int clp_list_pci(struct clp_req_rsp_list_pci *rrb, void *data, 360 void (*cb)(struct clp_fh_list_entry *, void *)) 361 { 362 u64 resume_token = 0; 363 int nentries, i, rc; 364 365 do { 366 rc = clp_list_pci_req(rrb, &resume_token, &nentries); 367 if (rc) 368 return rc; 369 for (i = 0; i < nentries; i++) 370 cb(&rrb->response.fh_list[i], data); 371 } while (resume_token); 372 373 return rc; 374 } 375 376 static int clp_find_pci(struct clp_req_rsp_list_pci *rrb, u32 fid, 377 struct clp_fh_list_entry *entry) 378 { 379 struct clp_fh_list_entry *fh_list; 380 u64 resume_token = 0; 381 int nentries, i, rc; 382 383 do { 384 rc = clp_list_pci_req(rrb, &resume_token, &nentries); 385 if (rc) 386 return rc; 387 fh_list = rrb->response.fh_list; 388 for (i = 0; i < nentries; i++) { 389 if (fh_list[i].fid == fid) { 390 *entry = fh_list[i]; 391 return 0; 392 } 393 } 394 } while (resume_token); 395 396 return -ENODEV; 397 } 398 399 static void __clp_add(struct clp_fh_list_entry *entry, void *data) 400 { 401 struct zpci_dev *zdev; 402 403 if (!entry->vendor_id) 404 return; 405 406 zdev = get_zdev_by_fid(entry->fid); 407 if (!zdev) 408 zpci_create_device(entry->fid, entry->fh, entry->config_state); 409 } 410 411 int clp_scan_pci_devices(void) 412 { 413 struct clp_req_rsp_list_pci *rrb; 414 int rc; 415 416 rrb = clp_alloc_block(GFP_KERNEL); 417 if (!rrb) 418 return -ENOMEM; 419 420 rc = clp_list_pci(rrb, NULL, __clp_add); 421 422 clp_free_block(rrb); 423 return rc; 424 } 425 426 /* 427 * Get the current function handle of the function matching @fid 428 */ 429 int clp_refresh_fh(u32 fid, u32 *fh) 430 { 431 struct clp_req_rsp_list_pci *rrb; 432 struct clp_fh_list_entry entry; 433 int rc; 434 435 rrb = clp_alloc_block(GFP_NOWAIT); 436 if (!rrb) 437 return -ENOMEM; 438 439 rc = clp_find_pci(rrb, fid, &entry); 440 if (!rc) 441 *fh = entry.fh; 442 443 clp_free_block(rrb); 444 return rc; 445 } 446 447 int clp_get_state(u32 fid, enum zpci_state *state) 448 { 449 struct clp_req_rsp_list_pci *rrb; 450 struct clp_fh_list_entry entry; 451 int rc; 452 453 rrb = clp_alloc_block(GFP_ATOMIC); 454 if (!rrb) 455 return -ENOMEM; 456 457 rc = clp_find_pci(rrb, fid, &entry); 458 if (!rc) { 459 *state = entry.config_state; 460 } else if (rc == -ENODEV) { 461 *state = ZPCI_FN_STATE_RESERVED; 462 rc = 0; 463 } 464 465 clp_free_block(rrb); 466 return rc; 467 } 468 469 static int clp_base_slpc(struct clp_req *req, struct clp_req_rsp_slpc *lpcb) 470 { 471 unsigned long limit = PAGE_SIZE - sizeof(lpcb->request); 472 473 if (lpcb->request.hdr.len != sizeof(lpcb->request) || 474 lpcb->response.hdr.len > limit) 475 return -EINVAL; 476 return clp_req(lpcb, CLP_LPS_BASE) ? -EOPNOTSUPP : 0; 477 } 478 479 static int clp_base_command(struct clp_req *req, struct clp_req_hdr *lpcb) 480 { 481 switch (lpcb->cmd) { 482 case 0x0001: /* store logical-processor characteristics */ 483 return clp_base_slpc(req, (void *) lpcb); 484 default: 485 return -EINVAL; 486 } 487 } 488 489 static int clp_pci_slpc(struct clp_req *req, struct clp_req_rsp_slpc_pci *lpcb) 490 { 491 unsigned long limit = PAGE_SIZE - sizeof(lpcb->request); 492 493 if (lpcb->request.hdr.len != sizeof(lpcb->request) || 494 lpcb->response.hdr.len > limit) 495 return -EINVAL; 496 return clp_req(lpcb, CLP_LPS_PCI) ? -EOPNOTSUPP : 0; 497 } 498 499 static int clp_pci_list(struct clp_req *req, struct clp_req_rsp_list_pci *lpcb) 500 { 501 unsigned long limit = PAGE_SIZE - sizeof(lpcb->request); 502 503 if (lpcb->request.hdr.len != sizeof(lpcb->request) || 504 lpcb->response.hdr.len > limit) 505 return -EINVAL; 506 if (lpcb->request.reserved2 != 0) 507 return -EINVAL; 508 return clp_req(lpcb, CLP_LPS_PCI) ? -EOPNOTSUPP : 0; 509 } 510 511 static int clp_pci_query(struct clp_req *req, 512 struct clp_req_rsp_query_pci *lpcb) 513 { 514 unsigned long limit = PAGE_SIZE - sizeof(lpcb->request); 515 516 if (lpcb->request.hdr.len != sizeof(lpcb->request) || 517 lpcb->response.hdr.len > limit) 518 return -EINVAL; 519 if (lpcb->request.reserved2 != 0 || lpcb->request.reserved3 != 0) 520 return -EINVAL; 521 return clp_req(lpcb, CLP_LPS_PCI) ? -EOPNOTSUPP : 0; 522 } 523 524 static int clp_pci_query_grp(struct clp_req *req, 525 struct clp_req_rsp_query_pci_grp *lpcb) 526 { 527 unsigned long limit = PAGE_SIZE - sizeof(lpcb->request); 528 529 if (lpcb->request.hdr.len != sizeof(lpcb->request) || 530 lpcb->response.hdr.len > limit) 531 return -EINVAL; 532 if (lpcb->request.reserved2 != 0 || lpcb->request.reserved3 != 0 || 533 lpcb->request.reserved4 != 0) 534 return -EINVAL; 535 return clp_req(lpcb, CLP_LPS_PCI) ? -EOPNOTSUPP : 0; 536 } 537 538 static int clp_pci_command(struct clp_req *req, struct clp_req_hdr *lpcb) 539 { 540 switch (lpcb->cmd) { 541 case 0x0001: /* store logical-processor characteristics */ 542 return clp_pci_slpc(req, (void *) lpcb); 543 case 0x0002: /* list PCI functions */ 544 return clp_pci_list(req, (void *) lpcb); 545 case 0x0003: /* query PCI function */ 546 return clp_pci_query(req, (void *) lpcb); 547 case 0x0004: /* query PCI function group */ 548 return clp_pci_query_grp(req, (void *) lpcb); 549 default: 550 return -EINVAL; 551 } 552 } 553 554 static int clp_normal_command(struct clp_req *req) 555 { 556 struct clp_req_hdr *lpcb; 557 void __user *uptr; 558 int rc; 559 560 rc = -EINVAL; 561 if (req->lps != 0 && req->lps != 2) 562 goto out; 563 564 rc = -ENOMEM; 565 lpcb = clp_alloc_block(GFP_KERNEL); 566 if (!lpcb) 567 goto out; 568 569 rc = -EFAULT; 570 uptr = (void __force __user *)(unsigned long) req->data_p; 571 if (copy_from_user(lpcb, uptr, PAGE_SIZE) != 0) 572 goto out_free; 573 574 rc = -EINVAL; 575 if (lpcb->fmt != 0 || lpcb->reserved1 != 0 || lpcb->reserved2 != 0) 576 goto out_free; 577 578 switch (req->lps) { 579 case 0: 580 rc = clp_base_command(req, lpcb); 581 break; 582 case 2: 583 rc = clp_pci_command(req, lpcb); 584 break; 585 } 586 if (rc) 587 goto out_free; 588 589 rc = -EFAULT; 590 if (copy_to_user(uptr, lpcb, PAGE_SIZE) != 0) 591 goto out_free; 592 593 rc = 0; 594 595 out_free: 596 clp_free_block(lpcb); 597 out: 598 return rc; 599 } 600 601 static int clp_immediate_command(struct clp_req *req) 602 { 603 void __user *uptr; 604 unsigned long ilp; 605 int exists; 606 607 if (req->cmd > 1 || clp_get_ilp(&ilp) != 0) 608 return -EINVAL; 609 610 uptr = (void __force __user *)(unsigned long) req->data_p; 611 if (req->cmd == 0) { 612 /* Command code 0: test for a specific processor */ 613 exists = test_bit_inv(req->lps, &ilp); 614 return put_user(exists, (int __user *) uptr); 615 } 616 /* Command code 1: return bit mask of installed processors */ 617 return put_user(ilp, (unsigned long __user *) uptr); 618 } 619 620 static long clp_misc_ioctl(struct file *filp, unsigned int cmd, 621 unsigned long arg) 622 { 623 struct clp_req req; 624 void __user *argp; 625 626 if (cmd != CLP_SYNC) 627 return -EINVAL; 628 629 argp = is_compat_task() ? compat_ptr(arg) : (void __user *) arg; 630 if (copy_from_user(&req, argp, sizeof(req))) 631 return -EFAULT; 632 if (req.r != 0) 633 return -EINVAL; 634 return req.c ? clp_immediate_command(&req) : clp_normal_command(&req); 635 } 636 637 static int clp_misc_release(struct inode *inode, struct file *filp) 638 { 639 return 0; 640 } 641 642 static const struct file_operations clp_misc_fops = { 643 .owner = THIS_MODULE, 644 .open = nonseekable_open, 645 .release = clp_misc_release, 646 .unlocked_ioctl = clp_misc_ioctl, 647 .compat_ioctl = clp_misc_ioctl, 648 .llseek = no_llseek, 649 }; 650 651 static struct miscdevice clp_misc_device = { 652 .minor = MISC_DYNAMIC_MINOR, 653 .name = "clp", 654 .fops = &clp_misc_fops, 655 }; 656 657 static int __init clp_misc_init(void) 658 { 659 return misc_register(&clp_misc_device); 660 } 661 662 device_initcall(clp_misc_init); 663