1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * BPF Jit compiler for s390. 4 * 5 * Minimum build requirements: 6 * 7 * - HAVE_MARCH_Z196_FEATURES: laal, laalg 8 * - HAVE_MARCH_Z10_FEATURES: msfi, cgrj, clgrj 9 * - HAVE_MARCH_Z9_109_FEATURES: alfi, llilf, clfi, oilf, nilf 10 * - PACK_STACK 11 * - 64BIT 12 * 13 * Copyright IBM Corp. 2012,2015 14 * 15 * Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com> 16 * Michael Holzheu <holzheu@linux.vnet.ibm.com> 17 */ 18 19 #define KMSG_COMPONENT "bpf_jit" 20 #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt 21 22 #include <linux/netdevice.h> 23 #include <linux/filter.h> 24 #include <linux/init.h> 25 #include <linux/bpf.h> 26 #include <asm/cacheflush.h> 27 #include <asm/dis.h> 28 #include <asm/set_memory.h> 29 #include "bpf_jit.h" 30 31 struct bpf_jit { 32 u32 seen; /* Flags to remember seen eBPF instructions */ 33 u32 seen_reg[16]; /* Array to remember which registers are used */ 34 u32 *addrs; /* Array with relative instruction addresses */ 35 u8 *prg_buf; /* Start of program */ 36 int size; /* Size of program and literal pool */ 37 int size_prg; /* Size of program */ 38 int prg; /* Current position in program */ 39 int lit_start; /* Start of literal pool */ 40 int lit; /* Current position in literal pool */ 41 int base_ip; /* Base address for literal pool */ 42 int ret0_ip; /* Address of return 0 */ 43 int exit_ip; /* Address of exit */ 44 int tail_call_start; /* Tail call start offset */ 45 int labels[1]; /* Labels for local jumps */ 46 }; 47 48 #define BPF_SIZE_MAX 0xffff /* Max size for program (16 bit branches) */ 49 50 #define SEEN_SKB 1 /* skb access */ 51 #define SEEN_MEM 2 /* use mem[] for temporary storage */ 52 #define SEEN_RET0 4 /* ret0_ip points to a valid return 0 */ 53 #define SEEN_LITERAL 8 /* code uses literals */ 54 #define SEEN_FUNC 16 /* calls C functions */ 55 #define SEEN_TAIL_CALL 32 /* code uses tail calls */ 56 #define SEEN_REG_AX 64 /* code uses constant blinding */ 57 #define SEEN_STACK (SEEN_FUNC | SEEN_MEM | SEEN_SKB) 58 59 /* 60 * s390 registers 61 */ 62 #define REG_W0 (MAX_BPF_JIT_REG + 0) /* Work register 1 (even) */ 63 #define REG_W1 (MAX_BPF_JIT_REG + 1) /* Work register 2 (odd) */ 64 #define REG_SKB_DATA (MAX_BPF_JIT_REG + 2) /* SKB data register */ 65 #define REG_L (MAX_BPF_JIT_REG + 3) /* Literal pool register */ 66 #define REG_15 (MAX_BPF_JIT_REG + 4) /* Register 15 */ 67 #define REG_0 REG_W0 /* Register 0 */ 68 #define REG_1 REG_W1 /* Register 1 */ 69 #define REG_2 BPF_REG_1 /* Register 2 */ 70 #define REG_14 BPF_REG_0 /* Register 14 */ 71 72 /* 73 * Mapping of BPF registers to s390 registers 74 */ 75 static const int reg2hex[] = { 76 /* Return code */ 77 [BPF_REG_0] = 14, 78 /* Function parameters */ 79 [BPF_REG_1] = 2, 80 [BPF_REG_2] = 3, 81 [BPF_REG_3] = 4, 82 [BPF_REG_4] = 5, 83 [BPF_REG_5] = 6, 84 /* Call saved registers */ 85 [BPF_REG_6] = 7, 86 [BPF_REG_7] = 8, 87 [BPF_REG_8] = 9, 88 [BPF_REG_9] = 10, 89 /* BPF stack pointer */ 90 [BPF_REG_FP] = 13, 91 /* Register for blinding (shared with REG_SKB_DATA) */ 92 [BPF_REG_AX] = 12, 93 /* SKB data pointer */ 94 [REG_SKB_DATA] = 12, 95 /* Work registers for s390x backend */ 96 [REG_W0] = 0, 97 [REG_W1] = 1, 98 [REG_L] = 11, 99 [REG_15] = 15, 100 }; 101 102 static inline u32 reg(u32 dst_reg, u32 src_reg) 103 { 104 return reg2hex[dst_reg] << 4 | reg2hex[src_reg]; 105 } 106 107 static inline u32 reg_high(u32 reg) 108 { 109 return reg2hex[reg] << 4; 110 } 111 112 static inline void reg_set_seen(struct bpf_jit *jit, u32 b1) 113 { 114 u32 r1 = reg2hex[b1]; 115 116 if (!jit->seen_reg[r1] && r1 >= 6 && r1 <= 15) 117 jit->seen_reg[r1] = 1; 118 } 119 120 #define REG_SET_SEEN(b1) \ 121 ({ \ 122 reg_set_seen(jit, b1); \ 123 }) 124 125 #define REG_SEEN(b1) jit->seen_reg[reg2hex[(b1)]] 126 127 /* 128 * EMIT macros for code generation 129 */ 130 131 #define _EMIT2(op) \ 132 ({ \ 133 if (jit->prg_buf) \ 134 *(u16 *) (jit->prg_buf + jit->prg) = op; \ 135 jit->prg += 2; \ 136 }) 137 138 #define EMIT2(op, b1, b2) \ 139 ({ \ 140 _EMIT2(op | reg(b1, b2)); \ 141 REG_SET_SEEN(b1); \ 142 REG_SET_SEEN(b2); \ 143 }) 144 145 #define _EMIT4(op) \ 146 ({ \ 147 if (jit->prg_buf) \ 148 *(u32 *) (jit->prg_buf + jit->prg) = op; \ 149 jit->prg += 4; \ 150 }) 151 152 #define EMIT4(op, b1, b2) \ 153 ({ \ 154 _EMIT4(op | reg(b1, b2)); \ 155 REG_SET_SEEN(b1); \ 156 REG_SET_SEEN(b2); \ 157 }) 158 159 #define EMIT4_RRF(op, b1, b2, b3) \ 160 ({ \ 161 _EMIT4(op | reg_high(b3) << 8 | reg(b1, b2)); \ 162 REG_SET_SEEN(b1); \ 163 REG_SET_SEEN(b2); \ 164 REG_SET_SEEN(b3); \ 165 }) 166 167 #define _EMIT4_DISP(op, disp) \ 168 ({ \ 169 unsigned int __disp = (disp) & 0xfff; \ 170 _EMIT4(op | __disp); \ 171 }) 172 173 #define EMIT4_DISP(op, b1, b2, disp) \ 174 ({ \ 175 _EMIT4_DISP(op | reg_high(b1) << 16 | \ 176 reg_high(b2) << 8, disp); \ 177 REG_SET_SEEN(b1); \ 178 REG_SET_SEEN(b2); \ 179 }) 180 181 #define EMIT4_IMM(op, b1, imm) \ 182 ({ \ 183 unsigned int __imm = (imm) & 0xffff; \ 184 _EMIT4(op | reg_high(b1) << 16 | __imm); \ 185 REG_SET_SEEN(b1); \ 186 }) 187 188 #define EMIT4_PCREL(op, pcrel) \ 189 ({ \ 190 long __pcrel = ((pcrel) >> 1) & 0xffff; \ 191 _EMIT4(op | __pcrel); \ 192 }) 193 194 #define _EMIT6(op1, op2) \ 195 ({ \ 196 if (jit->prg_buf) { \ 197 *(u32 *) (jit->prg_buf + jit->prg) = op1; \ 198 *(u16 *) (jit->prg_buf + jit->prg + 4) = op2; \ 199 } \ 200 jit->prg += 6; \ 201 }) 202 203 #define _EMIT6_DISP(op1, op2, disp) \ 204 ({ \ 205 unsigned int __disp = (disp) & 0xfff; \ 206 _EMIT6(op1 | __disp, op2); \ 207 }) 208 209 #define _EMIT6_DISP_LH(op1, op2, disp) \ 210 ({ \ 211 u32 _disp = (u32) disp; \ 212 unsigned int __disp_h = _disp & 0xff000; \ 213 unsigned int __disp_l = _disp & 0x00fff; \ 214 _EMIT6(op1 | __disp_l, op2 | __disp_h >> 4); \ 215 }) 216 217 #define EMIT6_DISP_LH(op1, op2, b1, b2, b3, disp) \ 218 ({ \ 219 _EMIT6_DISP_LH(op1 | reg(b1, b2) << 16 | \ 220 reg_high(b3) << 8, op2, disp); \ 221 REG_SET_SEEN(b1); \ 222 REG_SET_SEEN(b2); \ 223 REG_SET_SEEN(b3); \ 224 }) 225 226 #define EMIT6_PCREL_LABEL(op1, op2, b1, b2, label, mask) \ 227 ({ \ 228 int rel = (jit->labels[label] - jit->prg) >> 1; \ 229 _EMIT6(op1 | reg(b1, b2) << 16 | (rel & 0xffff), \ 230 op2 | mask << 12); \ 231 REG_SET_SEEN(b1); \ 232 REG_SET_SEEN(b2); \ 233 }) 234 235 #define EMIT6_PCREL_IMM_LABEL(op1, op2, b1, imm, label, mask) \ 236 ({ \ 237 int rel = (jit->labels[label] - jit->prg) >> 1; \ 238 _EMIT6(op1 | (reg_high(b1) | mask) << 16 | \ 239 (rel & 0xffff), op2 | (imm & 0xff) << 8); \ 240 REG_SET_SEEN(b1); \ 241 BUILD_BUG_ON(((unsigned long) imm) > 0xff); \ 242 }) 243 244 #define EMIT6_PCREL(op1, op2, b1, b2, i, off, mask) \ 245 ({ \ 246 /* Branch instruction needs 6 bytes */ \ 247 int rel = (addrs[i + off + 1] - (addrs[i + 1] - 6)) / 2;\ 248 _EMIT6(op1 | reg(b1, b2) << 16 | (rel & 0xffff), op2 | mask); \ 249 REG_SET_SEEN(b1); \ 250 REG_SET_SEEN(b2); \ 251 }) 252 253 #define _EMIT6_IMM(op, imm) \ 254 ({ \ 255 unsigned int __imm = (imm); \ 256 _EMIT6(op | (__imm >> 16), __imm & 0xffff); \ 257 }) 258 259 #define EMIT6_IMM(op, b1, imm) \ 260 ({ \ 261 _EMIT6_IMM(op | reg_high(b1) << 16, imm); \ 262 REG_SET_SEEN(b1); \ 263 }) 264 265 #define EMIT_CONST_U32(val) \ 266 ({ \ 267 unsigned int ret; \ 268 ret = jit->lit - jit->base_ip; \ 269 jit->seen |= SEEN_LITERAL; \ 270 if (jit->prg_buf) \ 271 *(u32 *) (jit->prg_buf + jit->lit) = (u32) val; \ 272 jit->lit += 4; \ 273 ret; \ 274 }) 275 276 #define EMIT_CONST_U64(val) \ 277 ({ \ 278 unsigned int ret; \ 279 ret = jit->lit - jit->base_ip; \ 280 jit->seen |= SEEN_LITERAL; \ 281 if (jit->prg_buf) \ 282 *(u64 *) (jit->prg_buf + jit->lit) = (u64) val; \ 283 jit->lit += 8; \ 284 ret; \ 285 }) 286 287 #define EMIT_ZERO(b1) \ 288 ({ \ 289 /* llgfr %dst,%dst (zero extend to 64 bit) */ \ 290 EMIT4(0xb9160000, b1, b1); \ 291 REG_SET_SEEN(b1); \ 292 }) 293 294 /* 295 * Fill whole space with illegal instructions 296 */ 297 static void jit_fill_hole(void *area, unsigned int size) 298 { 299 memset(area, 0, size); 300 } 301 302 /* 303 * Save registers from "rs" (register start) to "re" (register end) on stack 304 */ 305 static void save_regs(struct bpf_jit *jit, u32 rs, u32 re) 306 { 307 u32 off = STK_OFF_R6 + (rs - 6) * 8; 308 309 if (rs == re) 310 /* stg %rs,off(%r15) */ 311 _EMIT6(0xe300f000 | rs << 20 | off, 0x0024); 312 else 313 /* stmg %rs,%re,off(%r15) */ 314 _EMIT6_DISP(0xeb00f000 | rs << 20 | re << 16, 0x0024, off); 315 } 316 317 /* 318 * Restore registers from "rs" (register start) to "re" (register end) on stack 319 */ 320 static void restore_regs(struct bpf_jit *jit, u32 rs, u32 re, u32 stack_depth) 321 { 322 u32 off = STK_OFF_R6 + (rs - 6) * 8; 323 324 if (jit->seen & SEEN_STACK) 325 off += STK_OFF + stack_depth; 326 327 if (rs == re) 328 /* lg %rs,off(%r15) */ 329 _EMIT6(0xe300f000 | rs << 20 | off, 0x0004); 330 else 331 /* lmg %rs,%re,off(%r15) */ 332 _EMIT6_DISP(0xeb00f000 | rs << 20 | re << 16, 0x0004, off); 333 } 334 335 /* 336 * Return first seen register (from start) 337 */ 338 static int get_start(struct bpf_jit *jit, int start) 339 { 340 int i; 341 342 for (i = start; i <= 15; i++) { 343 if (jit->seen_reg[i]) 344 return i; 345 } 346 return 0; 347 } 348 349 /* 350 * Return last seen register (from start) (gap >= 2) 351 */ 352 static int get_end(struct bpf_jit *jit, int start) 353 { 354 int i; 355 356 for (i = start; i < 15; i++) { 357 if (!jit->seen_reg[i] && !jit->seen_reg[i + 1]) 358 return i - 1; 359 } 360 return jit->seen_reg[15] ? 15 : 14; 361 } 362 363 #define REGS_SAVE 1 364 #define REGS_RESTORE 0 365 /* 366 * Save and restore clobbered registers (6-15) on stack. 367 * We save/restore registers in chunks with gap >= 2 registers. 368 */ 369 static void save_restore_regs(struct bpf_jit *jit, int op, u32 stack_depth) 370 { 371 372 int re = 6, rs; 373 374 do { 375 rs = get_start(jit, re); 376 if (!rs) 377 break; 378 re = get_end(jit, rs + 1); 379 if (op == REGS_SAVE) 380 save_regs(jit, rs, re); 381 else 382 restore_regs(jit, rs, re, stack_depth); 383 re++; 384 } while (re <= 15); 385 } 386 387 /* 388 * For SKB access %b1 contains the SKB pointer. For "bpf_jit.S" 389 * we store the SKB header length on the stack and the SKB data 390 * pointer in REG_SKB_DATA if BPF_REG_AX is not used. 391 */ 392 static void emit_load_skb_data_hlen(struct bpf_jit *jit) 393 { 394 /* Header length: llgf %w1,<len>(%b1) */ 395 EMIT6_DISP_LH(0xe3000000, 0x0016, REG_W1, REG_0, BPF_REG_1, 396 offsetof(struct sk_buff, len)); 397 /* s %w1,<data_len>(%b1) */ 398 EMIT4_DISP(0x5b000000, REG_W1, BPF_REG_1, 399 offsetof(struct sk_buff, data_len)); 400 /* stg %w1,ST_OFF_HLEN(%r0,%r15) */ 401 EMIT6_DISP_LH(0xe3000000, 0x0024, REG_W1, REG_0, REG_15, STK_OFF_HLEN); 402 if (!(jit->seen & SEEN_REG_AX)) 403 /* lg %skb_data,data_off(%b1) */ 404 EMIT6_DISP_LH(0xe3000000, 0x0004, REG_SKB_DATA, REG_0, 405 BPF_REG_1, offsetof(struct sk_buff, data)); 406 } 407 408 /* 409 * Emit function prologue 410 * 411 * Save registers and create stack frame if necessary. 412 * See stack frame layout desription in "bpf_jit.h"! 413 */ 414 static void bpf_jit_prologue(struct bpf_jit *jit, u32 stack_depth) 415 { 416 if (jit->seen & SEEN_TAIL_CALL) { 417 /* xc STK_OFF_TCCNT(4,%r15),STK_OFF_TCCNT(%r15) */ 418 _EMIT6(0xd703f000 | STK_OFF_TCCNT, 0xf000 | STK_OFF_TCCNT); 419 } else { 420 /* j tail_call_start: NOP if no tail calls are used */ 421 EMIT4_PCREL(0xa7f40000, 6); 422 _EMIT2(0); 423 } 424 /* Tail calls have to skip above initialization */ 425 jit->tail_call_start = jit->prg; 426 /* Save registers */ 427 save_restore_regs(jit, REGS_SAVE, stack_depth); 428 /* Setup literal pool */ 429 if (jit->seen & SEEN_LITERAL) { 430 /* basr %r13,0 */ 431 EMIT2(0x0d00, REG_L, REG_0); 432 jit->base_ip = jit->prg; 433 } 434 /* Setup stack and backchain */ 435 if (jit->seen & SEEN_STACK) { 436 if (jit->seen & SEEN_FUNC) 437 /* lgr %w1,%r15 (backchain) */ 438 EMIT4(0xb9040000, REG_W1, REG_15); 439 /* la %bfp,STK_160_UNUSED(%r15) (BPF frame pointer) */ 440 EMIT4_DISP(0x41000000, BPF_REG_FP, REG_15, STK_160_UNUSED); 441 /* aghi %r15,-STK_OFF */ 442 EMIT4_IMM(0xa70b0000, REG_15, -(STK_OFF + stack_depth)); 443 if (jit->seen & SEEN_FUNC) 444 /* stg %w1,152(%r15) (backchain) */ 445 EMIT6_DISP_LH(0xe3000000, 0x0024, REG_W1, REG_0, 446 REG_15, 152); 447 } 448 if (jit->seen & SEEN_SKB) { 449 emit_load_skb_data_hlen(jit); 450 /* stg %b1,ST_OFF_SKBP(%r0,%r15) */ 451 EMIT6_DISP_LH(0xe3000000, 0x0024, BPF_REG_1, REG_0, REG_15, 452 STK_OFF_SKBP); 453 } 454 } 455 456 /* 457 * Function epilogue 458 */ 459 static void bpf_jit_epilogue(struct bpf_jit *jit, u32 stack_depth) 460 { 461 /* Return 0 */ 462 if (jit->seen & SEEN_RET0) { 463 jit->ret0_ip = jit->prg; 464 /* lghi %b0,0 */ 465 EMIT4_IMM(0xa7090000, BPF_REG_0, 0); 466 } 467 jit->exit_ip = jit->prg; 468 /* Load exit code: lgr %r2,%b0 */ 469 EMIT4(0xb9040000, REG_2, BPF_REG_0); 470 /* Restore registers */ 471 save_restore_regs(jit, REGS_RESTORE, stack_depth); 472 /* br %r14 */ 473 _EMIT2(0x07fe); 474 } 475 476 /* 477 * Compile one eBPF instruction into s390x code 478 * 479 * NOTE: Use noinline because for gcov (-fprofile-arcs) gcc allocates a lot of 480 * stack space for the large switch statement. 481 */ 482 static noinline int bpf_jit_insn(struct bpf_jit *jit, struct bpf_prog *fp, int i) 483 { 484 struct bpf_insn *insn = &fp->insnsi[i]; 485 int jmp_off, last, insn_count = 1; 486 unsigned int func_addr, mask; 487 u32 dst_reg = insn->dst_reg; 488 u32 src_reg = insn->src_reg; 489 u32 *addrs = jit->addrs; 490 s32 imm = insn->imm; 491 s16 off = insn->off; 492 493 if (dst_reg == BPF_REG_AX || src_reg == BPF_REG_AX) 494 jit->seen |= SEEN_REG_AX; 495 switch (insn->code) { 496 /* 497 * BPF_MOV 498 */ 499 case BPF_ALU | BPF_MOV | BPF_X: /* dst = (u32) src */ 500 /* llgfr %dst,%src */ 501 EMIT4(0xb9160000, dst_reg, src_reg); 502 break; 503 case BPF_ALU64 | BPF_MOV | BPF_X: /* dst = src */ 504 /* lgr %dst,%src */ 505 EMIT4(0xb9040000, dst_reg, src_reg); 506 break; 507 case BPF_ALU | BPF_MOV | BPF_K: /* dst = (u32) imm */ 508 /* llilf %dst,imm */ 509 EMIT6_IMM(0xc00f0000, dst_reg, imm); 510 break; 511 case BPF_ALU64 | BPF_MOV | BPF_K: /* dst = imm */ 512 /* lgfi %dst,imm */ 513 EMIT6_IMM(0xc0010000, dst_reg, imm); 514 break; 515 /* 516 * BPF_LD 64 517 */ 518 case BPF_LD | BPF_IMM | BPF_DW: /* dst = (u64) imm */ 519 { 520 /* 16 byte instruction that uses two 'struct bpf_insn' */ 521 u64 imm64; 522 523 imm64 = (u64)(u32) insn[0].imm | ((u64)(u32) insn[1].imm) << 32; 524 /* lg %dst,<d(imm)>(%l) */ 525 EMIT6_DISP_LH(0xe3000000, 0x0004, dst_reg, REG_0, REG_L, 526 EMIT_CONST_U64(imm64)); 527 insn_count = 2; 528 break; 529 } 530 /* 531 * BPF_ADD 532 */ 533 case BPF_ALU | BPF_ADD | BPF_X: /* dst = (u32) dst + (u32) src */ 534 /* ar %dst,%src */ 535 EMIT2(0x1a00, dst_reg, src_reg); 536 EMIT_ZERO(dst_reg); 537 break; 538 case BPF_ALU64 | BPF_ADD | BPF_X: /* dst = dst + src */ 539 /* agr %dst,%src */ 540 EMIT4(0xb9080000, dst_reg, src_reg); 541 break; 542 case BPF_ALU | BPF_ADD | BPF_K: /* dst = (u32) dst + (u32) imm */ 543 if (!imm) 544 break; 545 /* alfi %dst,imm */ 546 EMIT6_IMM(0xc20b0000, dst_reg, imm); 547 EMIT_ZERO(dst_reg); 548 break; 549 case BPF_ALU64 | BPF_ADD | BPF_K: /* dst = dst + imm */ 550 if (!imm) 551 break; 552 /* agfi %dst,imm */ 553 EMIT6_IMM(0xc2080000, dst_reg, imm); 554 break; 555 /* 556 * BPF_SUB 557 */ 558 case BPF_ALU | BPF_SUB | BPF_X: /* dst = (u32) dst - (u32) src */ 559 /* sr %dst,%src */ 560 EMIT2(0x1b00, dst_reg, src_reg); 561 EMIT_ZERO(dst_reg); 562 break; 563 case BPF_ALU64 | BPF_SUB | BPF_X: /* dst = dst - src */ 564 /* sgr %dst,%src */ 565 EMIT4(0xb9090000, dst_reg, src_reg); 566 break; 567 case BPF_ALU | BPF_SUB | BPF_K: /* dst = (u32) dst - (u32) imm */ 568 if (!imm) 569 break; 570 /* alfi %dst,-imm */ 571 EMIT6_IMM(0xc20b0000, dst_reg, -imm); 572 EMIT_ZERO(dst_reg); 573 break; 574 case BPF_ALU64 | BPF_SUB | BPF_K: /* dst = dst - imm */ 575 if (!imm) 576 break; 577 /* agfi %dst,-imm */ 578 EMIT6_IMM(0xc2080000, dst_reg, -imm); 579 break; 580 /* 581 * BPF_MUL 582 */ 583 case BPF_ALU | BPF_MUL | BPF_X: /* dst = (u32) dst * (u32) src */ 584 /* msr %dst,%src */ 585 EMIT4(0xb2520000, dst_reg, src_reg); 586 EMIT_ZERO(dst_reg); 587 break; 588 case BPF_ALU64 | BPF_MUL | BPF_X: /* dst = dst * src */ 589 /* msgr %dst,%src */ 590 EMIT4(0xb90c0000, dst_reg, src_reg); 591 break; 592 case BPF_ALU | BPF_MUL | BPF_K: /* dst = (u32) dst * (u32) imm */ 593 if (imm == 1) 594 break; 595 /* msfi %r5,imm */ 596 EMIT6_IMM(0xc2010000, dst_reg, imm); 597 EMIT_ZERO(dst_reg); 598 break; 599 case BPF_ALU64 | BPF_MUL | BPF_K: /* dst = dst * imm */ 600 if (imm == 1) 601 break; 602 /* msgfi %dst,imm */ 603 EMIT6_IMM(0xc2000000, dst_reg, imm); 604 break; 605 /* 606 * BPF_DIV / BPF_MOD 607 */ 608 case BPF_ALU | BPF_DIV | BPF_X: /* dst = (u32) dst / (u32) src */ 609 case BPF_ALU | BPF_MOD | BPF_X: /* dst = (u32) dst % (u32) src */ 610 { 611 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0; 612 613 /* lhi %w0,0 */ 614 EMIT4_IMM(0xa7080000, REG_W0, 0); 615 /* lr %w1,%dst */ 616 EMIT2(0x1800, REG_W1, dst_reg); 617 /* dlr %w0,%src */ 618 EMIT4(0xb9970000, REG_W0, src_reg); 619 /* llgfr %dst,%rc */ 620 EMIT4(0xb9160000, dst_reg, rc_reg); 621 break; 622 } 623 case BPF_ALU64 | BPF_DIV | BPF_X: /* dst = dst / src */ 624 case BPF_ALU64 | BPF_MOD | BPF_X: /* dst = dst % src */ 625 { 626 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0; 627 628 /* lghi %w0,0 */ 629 EMIT4_IMM(0xa7090000, REG_W0, 0); 630 /* lgr %w1,%dst */ 631 EMIT4(0xb9040000, REG_W1, dst_reg); 632 /* dlgr %w0,%dst */ 633 EMIT4(0xb9870000, REG_W0, src_reg); 634 /* lgr %dst,%rc */ 635 EMIT4(0xb9040000, dst_reg, rc_reg); 636 break; 637 } 638 case BPF_ALU | BPF_DIV | BPF_K: /* dst = (u32) dst / (u32) imm */ 639 case BPF_ALU | BPF_MOD | BPF_K: /* dst = (u32) dst % (u32) imm */ 640 { 641 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0; 642 643 if (imm == 1) { 644 if (BPF_OP(insn->code) == BPF_MOD) 645 /* lhgi %dst,0 */ 646 EMIT4_IMM(0xa7090000, dst_reg, 0); 647 break; 648 } 649 /* lhi %w0,0 */ 650 EMIT4_IMM(0xa7080000, REG_W0, 0); 651 /* lr %w1,%dst */ 652 EMIT2(0x1800, REG_W1, dst_reg); 653 /* dl %w0,<d(imm)>(%l) */ 654 EMIT6_DISP_LH(0xe3000000, 0x0097, REG_W0, REG_0, REG_L, 655 EMIT_CONST_U32(imm)); 656 /* llgfr %dst,%rc */ 657 EMIT4(0xb9160000, dst_reg, rc_reg); 658 break; 659 } 660 case BPF_ALU64 | BPF_DIV | BPF_K: /* dst = dst / imm */ 661 case BPF_ALU64 | BPF_MOD | BPF_K: /* dst = dst % imm */ 662 { 663 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0; 664 665 if (imm == 1) { 666 if (BPF_OP(insn->code) == BPF_MOD) 667 /* lhgi %dst,0 */ 668 EMIT4_IMM(0xa7090000, dst_reg, 0); 669 break; 670 } 671 /* lghi %w0,0 */ 672 EMIT4_IMM(0xa7090000, REG_W0, 0); 673 /* lgr %w1,%dst */ 674 EMIT4(0xb9040000, REG_W1, dst_reg); 675 /* dlg %w0,<d(imm)>(%l) */ 676 EMIT6_DISP_LH(0xe3000000, 0x0087, REG_W0, REG_0, REG_L, 677 EMIT_CONST_U64(imm)); 678 /* lgr %dst,%rc */ 679 EMIT4(0xb9040000, dst_reg, rc_reg); 680 break; 681 } 682 /* 683 * BPF_AND 684 */ 685 case BPF_ALU | BPF_AND | BPF_X: /* dst = (u32) dst & (u32) src */ 686 /* nr %dst,%src */ 687 EMIT2(0x1400, dst_reg, src_reg); 688 EMIT_ZERO(dst_reg); 689 break; 690 case BPF_ALU64 | BPF_AND | BPF_X: /* dst = dst & src */ 691 /* ngr %dst,%src */ 692 EMIT4(0xb9800000, dst_reg, src_reg); 693 break; 694 case BPF_ALU | BPF_AND | BPF_K: /* dst = (u32) dst & (u32) imm */ 695 /* nilf %dst,imm */ 696 EMIT6_IMM(0xc00b0000, dst_reg, imm); 697 EMIT_ZERO(dst_reg); 698 break; 699 case BPF_ALU64 | BPF_AND | BPF_K: /* dst = dst & imm */ 700 /* ng %dst,<d(imm)>(%l) */ 701 EMIT6_DISP_LH(0xe3000000, 0x0080, dst_reg, REG_0, REG_L, 702 EMIT_CONST_U64(imm)); 703 break; 704 /* 705 * BPF_OR 706 */ 707 case BPF_ALU | BPF_OR | BPF_X: /* dst = (u32) dst | (u32) src */ 708 /* or %dst,%src */ 709 EMIT2(0x1600, dst_reg, src_reg); 710 EMIT_ZERO(dst_reg); 711 break; 712 case BPF_ALU64 | BPF_OR | BPF_X: /* dst = dst | src */ 713 /* ogr %dst,%src */ 714 EMIT4(0xb9810000, dst_reg, src_reg); 715 break; 716 case BPF_ALU | BPF_OR | BPF_K: /* dst = (u32) dst | (u32) imm */ 717 /* oilf %dst,imm */ 718 EMIT6_IMM(0xc00d0000, dst_reg, imm); 719 EMIT_ZERO(dst_reg); 720 break; 721 case BPF_ALU64 | BPF_OR | BPF_K: /* dst = dst | imm */ 722 /* og %dst,<d(imm)>(%l) */ 723 EMIT6_DISP_LH(0xe3000000, 0x0081, dst_reg, REG_0, REG_L, 724 EMIT_CONST_U64(imm)); 725 break; 726 /* 727 * BPF_XOR 728 */ 729 case BPF_ALU | BPF_XOR | BPF_X: /* dst = (u32) dst ^ (u32) src */ 730 /* xr %dst,%src */ 731 EMIT2(0x1700, dst_reg, src_reg); 732 EMIT_ZERO(dst_reg); 733 break; 734 case BPF_ALU64 | BPF_XOR | BPF_X: /* dst = dst ^ src */ 735 /* xgr %dst,%src */ 736 EMIT4(0xb9820000, dst_reg, src_reg); 737 break; 738 case BPF_ALU | BPF_XOR | BPF_K: /* dst = (u32) dst ^ (u32) imm */ 739 if (!imm) 740 break; 741 /* xilf %dst,imm */ 742 EMIT6_IMM(0xc0070000, dst_reg, imm); 743 EMIT_ZERO(dst_reg); 744 break; 745 case BPF_ALU64 | BPF_XOR | BPF_K: /* dst = dst ^ imm */ 746 /* xg %dst,<d(imm)>(%l) */ 747 EMIT6_DISP_LH(0xe3000000, 0x0082, dst_reg, REG_0, REG_L, 748 EMIT_CONST_U64(imm)); 749 break; 750 /* 751 * BPF_LSH 752 */ 753 case BPF_ALU | BPF_LSH | BPF_X: /* dst = (u32) dst << (u32) src */ 754 /* sll %dst,0(%src) */ 755 EMIT4_DISP(0x89000000, dst_reg, src_reg, 0); 756 EMIT_ZERO(dst_reg); 757 break; 758 case BPF_ALU64 | BPF_LSH | BPF_X: /* dst = dst << src */ 759 /* sllg %dst,%dst,0(%src) */ 760 EMIT6_DISP_LH(0xeb000000, 0x000d, dst_reg, dst_reg, src_reg, 0); 761 break; 762 case BPF_ALU | BPF_LSH | BPF_K: /* dst = (u32) dst << (u32) imm */ 763 if (imm == 0) 764 break; 765 /* sll %dst,imm(%r0) */ 766 EMIT4_DISP(0x89000000, dst_reg, REG_0, imm); 767 EMIT_ZERO(dst_reg); 768 break; 769 case BPF_ALU64 | BPF_LSH | BPF_K: /* dst = dst << imm */ 770 if (imm == 0) 771 break; 772 /* sllg %dst,%dst,imm(%r0) */ 773 EMIT6_DISP_LH(0xeb000000, 0x000d, dst_reg, dst_reg, REG_0, imm); 774 break; 775 /* 776 * BPF_RSH 777 */ 778 case BPF_ALU | BPF_RSH | BPF_X: /* dst = (u32) dst >> (u32) src */ 779 /* srl %dst,0(%src) */ 780 EMIT4_DISP(0x88000000, dst_reg, src_reg, 0); 781 EMIT_ZERO(dst_reg); 782 break; 783 case BPF_ALU64 | BPF_RSH | BPF_X: /* dst = dst >> src */ 784 /* srlg %dst,%dst,0(%src) */ 785 EMIT6_DISP_LH(0xeb000000, 0x000c, dst_reg, dst_reg, src_reg, 0); 786 break; 787 case BPF_ALU | BPF_RSH | BPF_K: /* dst = (u32) dst >> (u32) imm */ 788 if (imm == 0) 789 break; 790 /* srl %dst,imm(%r0) */ 791 EMIT4_DISP(0x88000000, dst_reg, REG_0, imm); 792 EMIT_ZERO(dst_reg); 793 break; 794 case BPF_ALU64 | BPF_RSH | BPF_K: /* dst = dst >> imm */ 795 if (imm == 0) 796 break; 797 /* srlg %dst,%dst,imm(%r0) */ 798 EMIT6_DISP_LH(0xeb000000, 0x000c, dst_reg, dst_reg, REG_0, imm); 799 break; 800 /* 801 * BPF_ARSH 802 */ 803 case BPF_ALU64 | BPF_ARSH | BPF_X: /* ((s64) dst) >>= src */ 804 /* srag %dst,%dst,0(%src) */ 805 EMIT6_DISP_LH(0xeb000000, 0x000a, dst_reg, dst_reg, src_reg, 0); 806 break; 807 case BPF_ALU64 | BPF_ARSH | BPF_K: /* ((s64) dst) >>= imm */ 808 if (imm == 0) 809 break; 810 /* srag %dst,%dst,imm(%r0) */ 811 EMIT6_DISP_LH(0xeb000000, 0x000a, dst_reg, dst_reg, REG_0, imm); 812 break; 813 /* 814 * BPF_NEG 815 */ 816 case BPF_ALU | BPF_NEG: /* dst = (u32) -dst */ 817 /* lcr %dst,%dst */ 818 EMIT2(0x1300, dst_reg, dst_reg); 819 EMIT_ZERO(dst_reg); 820 break; 821 case BPF_ALU64 | BPF_NEG: /* dst = -dst */ 822 /* lcgr %dst,%dst */ 823 EMIT4(0xb9130000, dst_reg, dst_reg); 824 break; 825 /* 826 * BPF_FROM_BE/LE 827 */ 828 case BPF_ALU | BPF_END | BPF_FROM_BE: 829 /* s390 is big endian, therefore only clear high order bytes */ 830 switch (imm) { 831 case 16: /* dst = (u16) cpu_to_be16(dst) */ 832 /* llghr %dst,%dst */ 833 EMIT4(0xb9850000, dst_reg, dst_reg); 834 break; 835 case 32: /* dst = (u32) cpu_to_be32(dst) */ 836 /* llgfr %dst,%dst */ 837 EMIT4(0xb9160000, dst_reg, dst_reg); 838 break; 839 case 64: /* dst = (u64) cpu_to_be64(dst) */ 840 break; 841 } 842 break; 843 case BPF_ALU | BPF_END | BPF_FROM_LE: 844 switch (imm) { 845 case 16: /* dst = (u16) cpu_to_le16(dst) */ 846 /* lrvr %dst,%dst */ 847 EMIT4(0xb91f0000, dst_reg, dst_reg); 848 /* srl %dst,16(%r0) */ 849 EMIT4_DISP(0x88000000, dst_reg, REG_0, 16); 850 /* llghr %dst,%dst */ 851 EMIT4(0xb9850000, dst_reg, dst_reg); 852 break; 853 case 32: /* dst = (u32) cpu_to_le32(dst) */ 854 /* lrvr %dst,%dst */ 855 EMIT4(0xb91f0000, dst_reg, dst_reg); 856 /* llgfr %dst,%dst */ 857 EMIT4(0xb9160000, dst_reg, dst_reg); 858 break; 859 case 64: /* dst = (u64) cpu_to_le64(dst) */ 860 /* lrvgr %dst,%dst */ 861 EMIT4(0xb90f0000, dst_reg, dst_reg); 862 break; 863 } 864 break; 865 /* 866 * BPF_ST(X) 867 */ 868 case BPF_STX | BPF_MEM | BPF_B: /* *(u8 *)(dst + off) = src_reg */ 869 /* stcy %src,off(%dst) */ 870 EMIT6_DISP_LH(0xe3000000, 0x0072, src_reg, dst_reg, REG_0, off); 871 jit->seen |= SEEN_MEM; 872 break; 873 case BPF_STX | BPF_MEM | BPF_H: /* (u16 *)(dst + off) = src */ 874 /* sthy %src,off(%dst) */ 875 EMIT6_DISP_LH(0xe3000000, 0x0070, src_reg, dst_reg, REG_0, off); 876 jit->seen |= SEEN_MEM; 877 break; 878 case BPF_STX | BPF_MEM | BPF_W: /* *(u32 *)(dst + off) = src */ 879 /* sty %src,off(%dst) */ 880 EMIT6_DISP_LH(0xe3000000, 0x0050, src_reg, dst_reg, REG_0, off); 881 jit->seen |= SEEN_MEM; 882 break; 883 case BPF_STX | BPF_MEM | BPF_DW: /* (u64 *)(dst + off) = src */ 884 /* stg %src,off(%dst) */ 885 EMIT6_DISP_LH(0xe3000000, 0x0024, src_reg, dst_reg, REG_0, off); 886 jit->seen |= SEEN_MEM; 887 break; 888 case BPF_ST | BPF_MEM | BPF_B: /* *(u8 *)(dst + off) = imm */ 889 /* lhi %w0,imm */ 890 EMIT4_IMM(0xa7080000, REG_W0, (u8) imm); 891 /* stcy %w0,off(dst) */ 892 EMIT6_DISP_LH(0xe3000000, 0x0072, REG_W0, dst_reg, REG_0, off); 893 jit->seen |= SEEN_MEM; 894 break; 895 case BPF_ST | BPF_MEM | BPF_H: /* (u16 *)(dst + off) = imm */ 896 /* lhi %w0,imm */ 897 EMIT4_IMM(0xa7080000, REG_W0, (u16) imm); 898 /* sthy %w0,off(dst) */ 899 EMIT6_DISP_LH(0xe3000000, 0x0070, REG_W0, dst_reg, REG_0, off); 900 jit->seen |= SEEN_MEM; 901 break; 902 case BPF_ST | BPF_MEM | BPF_W: /* *(u32 *)(dst + off) = imm */ 903 /* llilf %w0,imm */ 904 EMIT6_IMM(0xc00f0000, REG_W0, (u32) imm); 905 /* sty %w0,off(%dst) */ 906 EMIT6_DISP_LH(0xe3000000, 0x0050, REG_W0, dst_reg, REG_0, off); 907 jit->seen |= SEEN_MEM; 908 break; 909 case BPF_ST | BPF_MEM | BPF_DW: /* *(u64 *)(dst + off) = imm */ 910 /* lgfi %w0,imm */ 911 EMIT6_IMM(0xc0010000, REG_W0, imm); 912 /* stg %w0,off(%dst) */ 913 EMIT6_DISP_LH(0xe3000000, 0x0024, REG_W0, dst_reg, REG_0, off); 914 jit->seen |= SEEN_MEM; 915 break; 916 /* 917 * BPF_STX XADD (atomic_add) 918 */ 919 case BPF_STX | BPF_XADD | BPF_W: /* *(u32 *)(dst + off) += src */ 920 /* laal %w0,%src,off(%dst) */ 921 EMIT6_DISP_LH(0xeb000000, 0x00fa, REG_W0, src_reg, 922 dst_reg, off); 923 jit->seen |= SEEN_MEM; 924 break; 925 case BPF_STX | BPF_XADD | BPF_DW: /* *(u64 *)(dst + off) += src */ 926 /* laalg %w0,%src,off(%dst) */ 927 EMIT6_DISP_LH(0xeb000000, 0x00ea, REG_W0, src_reg, 928 dst_reg, off); 929 jit->seen |= SEEN_MEM; 930 break; 931 /* 932 * BPF_LDX 933 */ 934 case BPF_LDX | BPF_MEM | BPF_B: /* dst = *(u8 *)(ul) (src + off) */ 935 /* llgc %dst,0(off,%src) */ 936 EMIT6_DISP_LH(0xe3000000, 0x0090, dst_reg, src_reg, REG_0, off); 937 jit->seen |= SEEN_MEM; 938 break; 939 case BPF_LDX | BPF_MEM | BPF_H: /* dst = *(u16 *)(ul) (src + off) */ 940 /* llgh %dst,0(off,%src) */ 941 EMIT6_DISP_LH(0xe3000000, 0x0091, dst_reg, src_reg, REG_0, off); 942 jit->seen |= SEEN_MEM; 943 break; 944 case BPF_LDX | BPF_MEM | BPF_W: /* dst = *(u32 *)(ul) (src + off) */ 945 /* llgf %dst,off(%src) */ 946 jit->seen |= SEEN_MEM; 947 EMIT6_DISP_LH(0xe3000000, 0x0016, dst_reg, src_reg, REG_0, off); 948 break; 949 case BPF_LDX | BPF_MEM | BPF_DW: /* dst = *(u64 *)(ul) (src + off) */ 950 /* lg %dst,0(off,%src) */ 951 jit->seen |= SEEN_MEM; 952 EMIT6_DISP_LH(0xe3000000, 0x0004, dst_reg, src_reg, REG_0, off); 953 break; 954 /* 955 * BPF_JMP / CALL 956 */ 957 case BPF_JMP | BPF_CALL: 958 { 959 /* 960 * b0 = (__bpf_call_base + imm)(b1, b2, b3, b4, b5) 961 */ 962 const u64 func = (u64)__bpf_call_base + imm; 963 964 REG_SET_SEEN(BPF_REG_5); 965 jit->seen |= SEEN_FUNC; 966 /* lg %w1,<d(imm)>(%l) */ 967 EMIT6_DISP_LH(0xe3000000, 0x0004, REG_W1, REG_0, REG_L, 968 EMIT_CONST_U64(func)); 969 /* basr %r14,%w1 */ 970 EMIT2(0x0d00, REG_14, REG_W1); 971 /* lgr %b0,%r2: load return value into %b0 */ 972 EMIT4(0xb9040000, BPF_REG_0, REG_2); 973 if ((jit->seen & SEEN_SKB) && 974 bpf_helper_changes_pkt_data((void *)func)) { 975 /* lg %b1,ST_OFF_SKBP(%r15) */ 976 EMIT6_DISP_LH(0xe3000000, 0x0004, BPF_REG_1, REG_0, 977 REG_15, STK_OFF_SKBP); 978 emit_load_skb_data_hlen(jit); 979 } 980 break; 981 } 982 case BPF_JMP | BPF_TAIL_CALL: 983 /* 984 * Implicit input: 985 * B1: pointer to ctx 986 * B2: pointer to bpf_array 987 * B3: index in bpf_array 988 */ 989 jit->seen |= SEEN_TAIL_CALL; 990 991 /* 992 * if (index >= array->map.max_entries) 993 * goto out; 994 */ 995 996 /* llgf %w1,map.max_entries(%b2) */ 997 EMIT6_DISP_LH(0xe3000000, 0x0016, REG_W1, REG_0, BPF_REG_2, 998 offsetof(struct bpf_array, map.max_entries)); 999 /* clgrj %b3,%w1,0xa,label0: if %b3 >= %w1 goto out */ 1000 EMIT6_PCREL_LABEL(0xec000000, 0x0065, BPF_REG_3, 1001 REG_W1, 0, 0xa); 1002 1003 /* 1004 * if (tail_call_cnt++ > MAX_TAIL_CALL_CNT) 1005 * goto out; 1006 */ 1007 1008 if (jit->seen & SEEN_STACK) 1009 off = STK_OFF_TCCNT + STK_OFF + fp->aux->stack_depth; 1010 else 1011 off = STK_OFF_TCCNT; 1012 /* lhi %w0,1 */ 1013 EMIT4_IMM(0xa7080000, REG_W0, 1); 1014 /* laal %w1,%w0,off(%r15) */ 1015 EMIT6_DISP_LH(0xeb000000, 0x00fa, REG_W1, REG_W0, REG_15, off); 1016 /* clij %w1,MAX_TAIL_CALL_CNT,0x2,label0 */ 1017 EMIT6_PCREL_IMM_LABEL(0xec000000, 0x007f, REG_W1, 1018 MAX_TAIL_CALL_CNT, 0, 0x2); 1019 1020 /* 1021 * prog = array->ptrs[index]; 1022 * if (prog == NULL) 1023 * goto out; 1024 */ 1025 1026 /* sllg %r1,%b3,3: %r1 = index * 8 */ 1027 EMIT6_DISP_LH(0xeb000000, 0x000d, REG_1, BPF_REG_3, REG_0, 3); 1028 /* lg %r1,prog(%b2,%r1) */ 1029 EMIT6_DISP_LH(0xe3000000, 0x0004, REG_1, BPF_REG_2, 1030 REG_1, offsetof(struct bpf_array, ptrs)); 1031 /* clgij %r1,0,0x8,label0 */ 1032 EMIT6_PCREL_IMM_LABEL(0xec000000, 0x007d, REG_1, 0, 0, 0x8); 1033 1034 /* 1035 * Restore registers before calling function 1036 */ 1037 save_restore_regs(jit, REGS_RESTORE, fp->aux->stack_depth); 1038 1039 /* 1040 * goto *(prog->bpf_func + tail_call_start); 1041 */ 1042 1043 /* lg %r1,bpf_func(%r1) */ 1044 EMIT6_DISP_LH(0xe3000000, 0x0004, REG_1, REG_1, REG_0, 1045 offsetof(struct bpf_prog, bpf_func)); 1046 /* bc 0xf,tail_call_start(%r1) */ 1047 _EMIT4(0x47f01000 + jit->tail_call_start); 1048 /* out: */ 1049 jit->labels[0] = jit->prg; 1050 break; 1051 case BPF_JMP | BPF_EXIT: /* return b0 */ 1052 last = (i == fp->len - 1) ? 1 : 0; 1053 if (last && !(jit->seen & SEEN_RET0)) 1054 break; 1055 /* j <exit> */ 1056 EMIT4_PCREL(0xa7f40000, jit->exit_ip - jit->prg); 1057 break; 1058 /* 1059 * Branch relative (number of skipped instructions) to offset on 1060 * condition. 1061 * 1062 * Condition code to mask mapping: 1063 * 1064 * CC | Description | Mask 1065 * ------------------------------ 1066 * 0 | Operands equal | 8 1067 * 1 | First operand low | 4 1068 * 2 | First operand high | 2 1069 * 3 | Unused | 1 1070 * 1071 * For s390x relative branches: ip = ip + off_bytes 1072 * For BPF relative branches: insn = insn + off_insns + 1 1073 * 1074 * For example for s390x with offset 0 we jump to the branch 1075 * instruction itself (loop) and for BPF with offset 0 we 1076 * branch to the instruction behind the branch. 1077 */ 1078 case BPF_JMP | BPF_JA: /* if (true) */ 1079 mask = 0xf000; /* j */ 1080 goto branch_oc; 1081 case BPF_JMP | BPF_JSGT | BPF_K: /* ((s64) dst > (s64) imm) */ 1082 mask = 0x2000; /* jh */ 1083 goto branch_ks; 1084 case BPF_JMP | BPF_JSLT | BPF_K: /* ((s64) dst < (s64) imm) */ 1085 mask = 0x4000; /* jl */ 1086 goto branch_ks; 1087 case BPF_JMP | BPF_JSGE | BPF_K: /* ((s64) dst >= (s64) imm) */ 1088 mask = 0xa000; /* jhe */ 1089 goto branch_ks; 1090 case BPF_JMP | BPF_JSLE | BPF_K: /* ((s64) dst <= (s64) imm) */ 1091 mask = 0xc000; /* jle */ 1092 goto branch_ks; 1093 case BPF_JMP | BPF_JGT | BPF_K: /* (dst_reg > imm) */ 1094 mask = 0x2000; /* jh */ 1095 goto branch_ku; 1096 case BPF_JMP | BPF_JLT | BPF_K: /* (dst_reg < imm) */ 1097 mask = 0x4000; /* jl */ 1098 goto branch_ku; 1099 case BPF_JMP | BPF_JGE | BPF_K: /* (dst_reg >= imm) */ 1100 mask = 0xa000; /* jhe */ 1101 goto branch_ku; 1102 case BPF_JMP | BPF_JLE | BPF_K: /* (dst_reg <= imm) */ 1103 mask = 0xc000; /* jle */ 1104 goto branch_ku; 1105 case BPF_JMP | BPF_JNE | BPF_K: /* (dst_reg != imm) */ 1106 mask = 0x7000; /* jne */ 1107 goto branch_ku; 1108 case BPF_JMP | BPF_JEQ | BPF_K: /* (dst_reg == imm) */ 1109 mask = 0x8000; /* je */ 1110 goto branch_ku; 1111 case BPF_JMP | BPF_JSET | BPF_K: /* (dst_reg & imm) */ 1112 mask = 0x7000; /* jnz */ 1113 /* lgfi %w1,imm (load sign extend imm) */ 1114 EMIT6_IMM(0xc0010000, REG_W1, imm); 1115 /* ngr %w1,%dst */ 1116 EMIT4(0xb9800000, REG_W1, dst_reg); 1117 goto branch_oc; 1118 1119 case BPF_JMP | BPF_JSGT | BPF_X: /* ((s64) dst > (s64) src) */ 1120 mask = 0x2000; /* jh */ 1121 goto branch_xs; 1122 case BPF_JMP | BPF_JSLT | BPF_X: /* ((s64) dst < (s64) src) */ 1123 mask = 0x4000; /* jl */ 1124 goto branch_xs; 1125 case BPF_JMP | BPF_JSGE | BPF_X: /* ((s64) dst >= (s64) src) */ 1126 mask = 0xa000; /* jhe */ 1127 goto branch_xs; 1128 case BPF_JMP | BPF_JSLE | BPF_X: /* ((s64) dst <= (s64) src) */ 1129 mask = 0xc000; /* jle */ 1130 goto branch_xs; 1131 case BPF_JMP | BPF_JGT | BPF_X: /* (dst > src) */ 1132 mask = 0x2000; /* jh */ 1133 goto branch_xu; 1134 case BPF_JMP | BPF_JLT | BPF_X: /* (dst < src) */ 1135 mask = 0x4000; /* jl */ 1136 goto branch_xu; 1137 case BPF_JMP | BPF_JGE | BPF_X: /* (dst >= src) */ 1138 mask = 0xa000; /* jhe */ 1139 goto branch_xu; 1140 case BPF_JMP | BPF_JLE | BPF_X: /* (dst <= src) */ 1141 mask = 0xc000; /* jle */ 1142 goto branch_xu; 1143 case BPF_JMP | BPF_JNE | BPF_X: /* (dst != src) */ 1144 mask = 0x7000; /* jne */ 1145 goto branch_xu; 1146 case BPF_JMP | BPF_JEQ | BPF_X: /* (dst == src) */ 1147 mask = 0x8000; /* je */ 1148 goto branch_xu; 1149 case BPF_JMP | BPF_JSET | BPF_X: /* (dst & src) */ 1150 mask = 0x7000; /* jnz */ 1151 /* ngrk %w1,%dst,%src */ 1152 EMIT4_RRF(0xb9e40000, REG_W1, dst_reg, src_reg); 1153 goto branch_oc; 1154 branch_ks: 1155 /* lgfi %w1,imm (load sign extend imm) */ 1156 EMIT6_IMM(0xc0010000, REG_W1, imm); 1157 /* cgrj %dst,%w1,mask,off */ 1158 EMIT6_PCREL(0xec000000, 0x0064, dst_reg, REG_W1, i, off, mask); 1159 break; 1160 branch_ku: 1161 /* lgfi %w1,imm (load sign extend imm) */ 1162 EMIT6_IMM(0xc0010000, REG_W1, imm); 1163 /* clgrj %dst,%w1,mask,off */ 1164 EMIT6_PCREL(0xec000000, 0x0065, dst_reg, REG_W1, i, off, mask); 1165 break; 1166 branch_xs: 1167 /* cgrj %dst,%src,mask,off */ 1168 EMIT6_PCREL(0xec000000, 0x0064, dst_reg, src_reg, i, off, mask); 1169 break; 1170 branch_xu: 1171 /* clgrj %dst,%src,mask,off */ 1172 EMIT6_PCREL(0xec000000, 0x0065, dst_reg, src_reg, i, off, mask); 1173 break; 1174 branch_oc: 1175 /* brc mask,jmp_off (branch instruction needs 4 bytes) */ 1176 jmp_off = addrs[i + off + 1] - (addrs[i + 1] - 4); 1177 EMIT4_PCREL(0xa7040000 | mask << 8, jmp_off); 1178 break; 1179 /* 1180 * BPF_LD 1181 */ 1182 case BPF_LD | BPF_ABS | BPF_B: /* b0 = *(u8 *) (skb->data+imm) */ 1183 case BPF_LD | BPF_IND | BPF_B: /* b0 = *(u8 *) (skb->data+imm+src) */ 1184 if ((BPF_MODE(insn->code) == BPF_ABS) && (imm >= 0)) 1185 func_addr = __pa(sk_load_byte_pos); 1186 else 1187 func_addr = __pa(sk_load_byte); 1188 goto call_fn; 1189 case BPF_LD | BPF_ABS | BPF_H: /* b0 = *(u16 *) (skb->data+imm) */ 1190 case BPF_LD | BPF_IND | BPF_H: /* b0 = *(u16 *) (skb->data+imm+src) */ 1191 if ((BPF_MODE(insn->code) == BPF_ABS) && (imm >= 0)) 1192 func_addr = __pa(sk_load_half_pos); 1193 else 1194 func_addr = __pa(sk_load_half); 1195 goto call_fn; 1196 case BPF_LD | BPF_ABS | BPF_W: /* b0 = *(u32 *) (skb->data+imm) */ 1197 case BPF_LD | BPF_IND | BPF_W: /* b0 = *(u32 *) (skb->data+imm+src) */ 1198 if ((BPF_MODE(insn->code) == BPF_ABS) && (imm >= 0)) 1199 func_addr = __pa(sk_load_word_pos); 1200 else 1201 func_addr = __pa(sk_load_word); 1202 goto call_fn; 1203 call_fn: 1204 jit->seen |= SEEN_SKB | SEEN_RET0 | SEEN_FUNC; 1205 REG_SET_SEEN(REG_14); /* Return address of possible func call */ 1206 1207 /* 1208 * Implicit input: 1209 * BPF_REG_6 (R7) : skb pointer 1210 * REG_SKB_DATA (R12): skb data pointer (if no BPF_REG_AX) 1211 * 1212 * Calculated input: 1213 * BPF_REG_2 (R3) : offset of byte(s) to fetch in skb 1214 * BPF_REG_5 (R6) : return address 1215 * 1216 * Output: 1217 * BPF_REG_0 (R14): data read from skb 1218 * 1219 * Scratch registers (BPF_REG_1-5) 1220 */ 1221 1222 /* Call function: llilf %w1,func_addr */ 1223 EMIT6_IMM(0xc00f0000, REG_W1, func_addr); 1224 1225 /* Offset: lgfi %b2,imm */ 1226 EMIT6_IMM(0xc0010000, BPF_REG_2, imm); 1227 if (BPF_MODE(insn->code) == BPF_IND) 1228 /* agfr %b2,%src (%src is s32 here) */ 1229 EMIT4(0xb9180000, BPF_REG_2, src_reg); 1230 1231 /* Reload REG_SKB_DATA if BPF_REG_AX is used */ 1232 if (jit->seen & SEEN_REG_AX) 1233 /* lg %skb_data,data_off(%b6) */ 1234 EMIT6_DISP_LH(0xe3000000, 0x0004, REG_SKB_DATA, REG_0, 1235 BPF_REG_6, offsetof(struct sk_buff, data)); 1236 /* basr %b5,%w1 (%b5 is call saved) */ 1237 EMIT2(0x0d00, BPF_REG_5, REG_W1); 1238 1239 /* 1240 * Note: For fast access we jump directly after the 1241 * jnz instruction from bpf_jit.S 1242 */ 1243 /* jnz <ret0> */ 1244 EMIT4_PCREL(0xa7740000, jit->ret0_ip - jit->prg); 1245 break; 1246 default: /* too complex, give up */ 1247 pr_err("Unknown opcode %02x\n", insn->code); 1248 return -1; 1249 } 1250 return insn_count; 1251 } 1252 1253 /* 1254 * Compile eBPF program into s390x code 1255 */ 1256 static int bpf_jit_prog(struct bpf_jit *jit, struct bpf_prog *fp) 1257 { 1258 int i, insn_count; 1259 1260 jit->lit = jit->lit_start; 1261 jit->prg = 0; 1262 1263 bpf_jit_prologue(jit, fp->aux->stack_depth); 1264 for (i = 0; i < fp->len; i += insn_count) { 1265 insn_count = bpf_jit_insn(jit, fp, i); 1266 if (insn_count < 0) 1267 return -1; 1268 /* Next instruction address */ 1269 jit->addrs[i + insn_count] = jit->prg; 1270 } 1271 bpf_jit_epilogue(jit, fp->aux->stack_depth); 1272 1273 jit->lit_start = jit->prg; 1274 jit->size = jit->lit; 1275 jit->size_prg = jit->prg; 1276 return 0; 1277 } 1278 1279 /* 1280 * Compile eBPF program "fp" 1281 */ 1282 struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *fp) 1283 { 1284 struct bpf_prog *tmp, *orig_fp = fp; 1285 struct bpf_binary_header *header; 1286 bool tmp_blinded = false; 1287 struct bpf_jit jit; 1288 int pass; 1289 1290 if (!fp->jit_requested) 1291 return orig_fp; 1292 1293 tmp = bpf_jit_blind_constants(fp); 1294 /* 1295 * If blinding was requested and we failed during blinding, 1296 * we must fall back to the interpreter. 1297 */ 1298 if (IS_ERR(tmp)) 1299 return orig_fp; 1300 if (tmp != fp) { 1301 tmp_blinded = true; 1302 fp = tmp; 1303 } 1304 1305 memset(&jit, 0, sizeof(jit)); 1306 jit.addrs = kcalloc(fp->len + 1, sizeof(*jit.addrs), GFP_KERNEL); 1307 if (jit.addrs == NULL) { 1308 fp = orig_fp; 1309 goto out; 1310 } 1311 /* 1312 * Three initial passes: 1313 * - 1/2: Determine clobbered registers 1314 * - 3: Calculate program size and addrs arrray 1315 */ 1316 for (pass = 1; pass <= 3; pass++) { 1317 if (bpf_jit_prog(&jit, fp)) { 1318 fp = orig_fp; 1319 goto free_addrs; 1320 } 1321 } 1322 /* 1323 * Final pass: Allocate and generate program 1324 */ 1325 if (jit.size >= BPF_SIZE_MAX) { 1326 fp = orig_fp; 1327 goto free_addrs; 1328 } 1329 header = bpf_jit_binary_alloc(jit.size, &jit.prg_buf, 2, jit_fill_hole); 1330 if (!header) { 1331 fp = orig_fp; 1332 goto free_addrs; 1333 } 1334 if (bpf_jit_prog(&jit, fp)) { 1335 fp = orig_fp; 1336 goto free_addrs; 1337 } 1338 if (bpf_jit_enable > 1) { 1339 bpf_jit_dump(fp->len, jit.size, pass, jit.prg_buf); 1340 print_fn_code(jit.prg_buf, jit.size_prg); 1341 } 1342 bpf_jit_binary_lock_ro(header); 1343 fp->bpf_func = (void *) jit.prg_buf; 1344 fp->jited = 1; 1345 fp->jited_len = jit.size; 1346 free_addrs: 1347 kfree(jit.addrs); 1348 out: 1349 if (tmp_blinded) 1350 bpf_jit_prog_release_other(fp, fp == orig_fp ? 1351 tmp : orig_fp); 1352 return fp; 1353 } 1354