1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * BPF Jit compiler for s390. 4 * 5 * Minimum build requirements: 6 * 7 * - HAVE_MARCH_Z196_FEATURES: laal, laalg 8 * - HAVE_MARCH_Z10_FEATURES: msfi, cgrj, clgrj 9 * - HAVE_MARCH_Z9_109_FEATURES: alfi, llilf, clfi, oilf, nilf 10 * - PACK_STACK 11 * - 64BIT 12 * 13 * Copyright IBM Corp. 2012,2015 14 * 15 * Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com> 16 * Michael Holzheu <holzheu@linux.vnet.ibm.com> 17 */ 18 19 #define KMSG_COMPONENT "bpf_jit" 20 #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt 21 22 #include <linux/netdevice.h> 23 #include <linux/filter.h> 24 #include <linux/init.h> 25 #include <linux/bpf.h> 26 #include <asm/cacheflush.h> 27 #include <asm/dis.h> 28 #include <asm/facility.h> 29 #include <asm/nospec-branch.h> 30 #include <asm/set_memory.h> 31 #include "bpf_jit.h" 32 33 struct bpf_jit { 34 u32 seen; /* Flags to remember seen eBPF instructions */ 35 u32 seen_reg[16]; /* Array to remember which registers are used */ 36 u32 *addrs; /* Array with relative instruction addresses */ 37 u8 *prg_buf; /* Start of program */ 38 int size; /* Size of program and literal pool */ 39 int size_prg; /* Size of program */ 40 int prg; /* Current position in program */ 41 int lit_start; /* Start of literal pool */ 42 int lit; /* Current position in literal pool */ 43 int base_ip; /* Base address for literal pool */ 44 int ret0_ip; /* Address of return 0 */ 45 int exit_ip; /* Address of exit */ 46 int r1_thunk_ip; /* Address of expoline thunk for 'br %r1' */ 47 int r14_thunk_ip; /* Address of expoline thunk for 'br %r14' */ 48 int tail_call_start; /* Tail call start offset */ 49 int labels[1]; /* Labels for local jumps */ 50 }; 51 52 #define BPF_SIZE_MAX 0xffff /* Max size for program (16 bit branches) */ 53 54 #define SEEN_MEM (1 << 0) /* use mem[] for temporary storage */ 55 #define SEEN_RET0 (1 << 1) /* ret0_ip points to a valid return 0 */ 56 #define SEEN_LITERAL (1 << 2) /* code uses literals */ 57 #define SEEN_FUNC (1 << 3) /* calls C functions */ 58 #define SEEN_TAIL_CALL (1 << 4) /* code uses tail calls */ 59 #define SEEN_REG_AX (1 << 5) /* code uses constant blinding */ 60 #define SEEN_STACK (SEEN_FUNC | SEEN_MEM) 61 62 /* 63 * s390 registers 64 */ 65 #define REG_W0 (MAX_BPF_JIT_REG + 0) /* Work register 1 (even) */ 66 #define REG_W1 (MAX_BPF_JIT_REG + 1) /* Work register 2 (odd) */ 67 #define REG_L (MAX_BPF_JIT_REG + 2) /* Literal pool register */ 68 #define REG_15 (MAX_BPF_JIT_REG + 3) /* Register 15 */ 69 #define REG_0 REG_W0 /* Register 0 */ 70 #define REG_1 REG_W1 /* Register 1 */ 71 #define REG_2 BPF_REG_1 /* Register 2 */ 72 #define REG_14 BPF_REG_0 /* Register 14 */ 73 74 /* 75 * Mapping of BPF registers to s390 registers 76 */ 77 static const int reg2hex[] = { 78 /* Return code */ 79 [BPF_REG_0] = 14, 80 /* Function parameters */ 81 [BPF_REG_1] = 2, 82 [BPF_REG_2] = 3, 83 [BPF_REG_3] = 4, 84 [BPF_REG_4] = 5, 85 [BPF_REG_5] = 6, 86 /* Call saved registers */ 87 [BPF_REG_6] = 7, 88 [BPF_REG_7] = 8, 89 [BPF_REG_8] = 9, 90 [BPF_REG_9] = 10, 91 /* BPF stack pointer */ 92 [BPF_REG_FP] = 13, 93 /* Register for blinding */ 94 [BPF_REG_AX] = 12, 95 /* Work registers for s390x backend */ 96 [REG_W0] = 0, 97 [REG_W1] = 1, 98 [REG_L] = 11, 99 [REG_15] = 15, 100 }; 101 102 static inline u32 reg(u32 dst_reg, u32 src_reg) 103 { 104 return reg2hex[dst_reg] << 4 | reg2hex[src_reg]; 105 } 106 107 static inline u32 reg_high(u32 reg) 108 { 109 return reg2hex[reg] << 4; 110 } 111 112 static inline void reg_set_seen(struct bpf_jit *jit, u32 b1) 113 { 114 u32 r1 = reg2hex[b1]; 115 116 if (!jit->seen_reg[r1] && r1 >= 6 && r1 <= 15) 117 jit->seen_reg[r1] = 1; 118 } 119 120 #define REG_SET_SEEN(b1) \ 121 ({ \ 122 reg_set_seen(jit, b1); \ 123 }) 124 125 #define REG_SEEN(b1) jit->seen_reg[reg2hex[(b1)]] 126 127 /* 128 * EMIT macros for code generation 129 */ 130 131 #define _EMIT2(op) \ 132 ({ \ 133 if (jit->prg_buf) \ 134 *(u16 *) (jit->prg_buf + jit->prg) = op; \ 135 jit->prg += 2; \ 136 }) 137 138 #define EMIT2(op, b1, b2) \ 139 ({ \ 140 _EMIT2(op | reg(b1, b2)); \ 141 REG_SET_SEEN(b1); \ 142 REG_SET_SEEN(b2); \ 143 }) 144 145 #define _EMIT4(op) \ 146 ({ \ 147 if (jit->prg_buf) \ 148 *(u32 *) (jit->prg_buf + jit->prg) = op; \ 149 jit->prg += 4; \ 150 }) 151 152 #define EMIT4(op, b1, b2) \ 153 ({ \ 154 _EMIT4(op | reg(b1, b2)); \ 155 REG_SET_SEEN(b1); \ 156 REG_SET_SEEN(b2); \ 157 }) 158 159 #define EMIT4_RRF(op, b1, b2, b3) \ 160 ({ \ 161 _EMIT4(op | reg_high(b3) << 8 | reg(b1, b2)); \ 162 REG_SET_SEEN(b1); \ 163 REG_SET_SEEN(b2); \ 164 REG_SET_SEEN(b3); \ 165 }) 166 167 #define _EMIT4_DISP(op, disp) \ 168 ({ \ 169 unsigned int __disp = (disp) & 0xfff; \ 170 _EMIT4(op | __disp); \ 171 }) 172 173 #define EMIT4_DISP(op, b1, b2, disp) \ 174 ({ \ 175 _EMIT4_DISP(op | reg_high(b1) << 16 | \ 176 reg_high(b2) << 8, disp); \ 177 REG_SET_SEEN(b1); \ 178 REG_SET_SEEN(b2); \ 179 }) 180 181 #define EMIT4_IMM(op, b1, imm) \ 182 ({ \ 183 unsigned int __imm = (imm) & 0xffff; \ 184 _EMIT4(op | reg_high(b1) << 16 | __imm); \ 185 REG_SET_SEEN(b1); \ 186 }) 187 188 #define EMIT4_PCREL(op, pcrel) \ 189 ({ \ 190 long __pcrel = ((pcrel) >> 1) & 0xffff; \ 191 _EMIT4(op | __pcrel); \ 192 }) 193 194 #define _EMIT6(op1, op2) \ 195 ({ \ 196 if (jit->prg_buf) { \ 197 *(u32 *) (jit->prg_buf + jit->prg) = op1; \ 198 *(u16 *) (jit->prg_buf + jit->prg + 4) = op2; \ 199 } \ 200 jit->prg += 6; \ 201 }) 202 203 #define _EMIT6_DISP(op1, op2, disp) \ 204 ({ \ 205 unsigned int __disp = (disp) & 0xfff; \ 206 _EMIT6(op1 | __disp, op2); \ 207 }) 208 209 #define _EMIT6_DISP_LH(op1, op2, disp) \ 210 ({ \ 211 u32 _disp = (u32) disp; \ 212 unsigned int __disp_h = _disp & 0xff000; \ 213 unsigned int __disp_l = _disp & 0x00fff; \ 214 _EMIT6(op1 | __disp_l, op2 | __disp_h >> 4); \ 215 }) 216 217 #define EMIT6_DISP_LH(op1, op2, b1, b2, b3, disp) \ 218 ({ \ 219 _EMIT6_DISP_LH(op1 | reg(b1, b2) << 16 | \ 220 reg_high(b3) << 8, op2, disp); \ 221 REG_SET_SEEN(b1); \ 222 REG_SET_SEEN(b2); \ 223 REG_SET_SEEN(b3); \ 224 }) 225 226 #define EMIT6_PCREL_LABEL(op1, op2, b1, b2, label, mask) \ 227 ({ \ 228 int rel = (jit->labels[label] - jit->prg) >> 1; \ 229 _EMIT6(op1 | reg(b1, b2) << 16 | (rel & 0xffff), \ 230 op2 | mask << 12); \ 231 REG_SET_SEEN(b1); \ 232 REG_SET_SEEN(b2); \ 233 }) 234 235 #define EMIT6_PCREL_IMM_LABEL(op1, op2, b1, imm, label, mask) \ 236 ({ \ 237 int rel = (jit->labels[label] - jit->prg) >> 1; \ 238 _EMIT6(op1 | (reg_high(b1) | mask) << 16 | \ 239 (rel & 0xffff), op2 | (imm & 0xff) << 8); \ 240 REG_SET_SEEN(b1); \ 241 BUILD_BUG_ON(((unsigned long) imm) > 0xff); \ 242 }) 243 244 #define EMIT6_PCREL(op1, op2, b1, b2, i, off, mask) \ 245 ({ \ 246 /* Branch instruction needs 6 bytes */ \ 247 int rel = (addrs[i + off + 1] - (addrs[i + 1] - 6)) / 2;\ 248 _EMIT6(op1 | reg(b1, b2) << 16 | (rel & 0xffff), op2 | mask); \ 249 REG_SET_SEEN(b1); \ 250 REG_SET_SEEN(b2); \ 251 }) 252 253 #define EMIT6_PCREL_RILB(op, b, target) \ 254 ({ \ 255 int rel = (target - jit->prg) / 2; \ 256 _EMIT6(op | reg_high(b) << 16 | rel >> 16, rel & 0xffff); \ 257 REG_SET_SEEN(b); \ 258 }) 259 260 #define EMIT6_PCREL_RIL(op, target) \ 261 ({ \ 262 int rel = (target - jit->prg) / 2; \ 263 _EMIT6(op | rel >> 16, rel & 0xffff); \ 264 }) 265 266 #define _EMIT6_IMM(op, imm) \ 267 ({ \ 268 unsigned int __imm = (imm); \ 269 _EMIT6(op | (__imm >> 16), __imm & 0xffff); \ 270 }) 271 272 #define EMIT6_IMM(op, b1, imm) \ 273 ({ \ 274 _EMIT6_IMM(op | reg_high(b1) << 16, imm); \ 275 REG_SET_SEEN(b1); \ 276 }) 277 278 #define EMIT_CONST_U32(val) \ 279 ({ \ 280 unsigned int ret; \ 281 ret = jit->lit - jit->base_ip; \ 282 jit->seen |= SEEN_LITERAL; \ 283 if (jit->prg_buf) \ 284 *(u32 *) (jit->prg_buf + jit->lit) = (u32) val; \ 285 jit->lit += 4; \ 286 ret; \ 287 }) 288 289 #define EMIT_CONST_U64(val) \ 290 ({ \ 291 unsigned int ret; \ 292 ret = jit->lit - jit->base_ip; \ 293 jit->seen |= SEEN_LITERAL; \ 294 if (jit->prg_buf) \ 295 *(u64 *) (jit->prg_buf + jit->lit) = (u64) val; \ 296 jit->lit += 8; \ 297 ret; \ 298 }) 299 300 #define EMIT_ZERO(b1) \ 301 ({ \ 302 /* llgfr %dst,%dst (zero extend to 64 bit) */ \ 303 EMIT4(0xb9160000, b1, b1); \ 304 REG_SET_SEEN(b1); \ 305 }) 306 307 /* 308 * Fill whole space with illegal instructions 309 */ 310 static void jit_fill_hole(void *area, unsigned int size) 311 { 312 memset(area, 0, size); 313 } 314 315 /* 316 * Save registers from "rs" (register start) to "re" (register end) on stack 317 */ 318 static void save_regs(struct bpf_jit *jit, u32 rs, u32 re) 319 { 320 u32 off = STK_OFF_R6 + (rs - 6) * 8; 321 322 if (rs == re) 323 /* stg %rs,off(%r15) */ 324 _EMIT6(0xe300f000 | rs << 20 | off, 0x0024); 325 else 326 /* stmg %rs,%re,off(%r15) */ 327 _EMIT6_DISP(0xeb00f000 | rs << 20 | re << 16, 0x0024, off); 328 } 329 330 /* 331 * Restore registers from "rs" (register start) to "re" (register end) on stack 332 */ 333 static void restore_regs(struct bpf_jit *jit, u32 rs, u32 re, u32 stack_depth) 334 { 335 u32 off = STK_OFF_R6 + (rs - 6) * 8; 336 337 if (jit->seen & SEEN_STACK) 338 off += STK_OFF + stack_depth; 339 340 if (rs == re) 341 /* lg %rs,off(%r15) */ 342 _EMIT6(0xe300f000 | rs << 20 | off, 0x0004); 343 else 344 /* lmg %rs,%re,off(%r15) */ 345 _EMIT6_DISP(0xeb00f000 | rs << 20 | re << 16, 0x0004, off); 346 } 347 348 /* 349 * Return first seen register (from start) 350 */ 351 static int get_start(struct bpf_jit *jit, int start) 352 { 353 int i; 354 355 for (i = start; i <= 15; i++) { 356 if (jit->seen_reg[i]) 357 return i; 358 } 359 return 0; 360 } 361 362 /* 363 * Return last seen register (from start) (gap >= 2) 364 */ 365 static int get_end(struct bpf_jit *jit, int start) 366 { 367 int i; 368 369 for (i = start; i < 15; i++) { 370 if (!jit->seen_reg[i] && !jit->seen_reg[i + 1]) 371 return i - 1; 372 } 373 return jit->seen_reg[15] ? 15 : 14; 374 } 375 376 #define REGS_SAVE 1 377 #define REGS_RESTORE 0 378 /* 379 * Save and restore clobbered registers (6-15) on stack. 380 * We save/restore registers in chunks with gap >= 2 registers. 381 */ 382 static void save_restore_regs(struct bpf_jit *jit, int op, u32 stack_depth) 383 { 384 385 int re = 6, rs; 386 387 do { 388 rs = get_start(jit, re); 389 if (!rs) 390 break; 391 re = get_end(jit, rs + 1); 392 if (op == REGS_SAVE) 393 save_regs(jit, rs, re); 394 else 395 restore_regs(jit, rs, re, stack_depth); 396 re++; 397 } while (re <= 15); 398 } 399 400 /* 401 * Emit function prologue 402 * 403 * Save registers and create stack frame if necessary. 404 * See stack frame layout desription in "bpf_jit.h"! 405 */ 406 static void bpf_jit_prologue(struct bpf_jit *jit, u32 stack_depth) 407 { 408 if (jit->seen & SEEN_TAIL_CALL) { 409 /* xc STK_OFF_TCCNT(4,%r15),STK_OFF_TCCNT(%r15) */ 410 _EMIT6(0xd703f000 | STK_OFF_TCCNT, 0xf000 | STK_OFF_TCCNT); 411 } else { 412 /* j tail_call_start: NOP if no tail calls are used */ 413 EMIT4_PCREL(0xa7f40000, 6); 414 _EMIT2(0); 415 } 416 /* Tail calls have to skip above initialization */ 417 jit->tail_call_start = jit->prg; 418 /* Save registers */ 419 save_restore_regs(jit, REGS_SAVE, stack_depth); 420 /* Setup literal pool */ 421 if (jit->seen & SEEN_LITERAL) { 422 /* basr %r13,0 */ 423 EMIT2(0x0d00, REG_L, REG_0); 424 jit->base_ip = jit->prg; 425 } 426 /* Setup stack and backchain */ 427 if (jit->seen & SEEN_STACK) { 428 if (jit->seen & SEEN_FUNC) 429 /* lgr %w1,%r15 (backchain) */ 430 EMIT4(0xb9040000, REG_W1, REG_15); 431 /* la %bfp,STK_160_UNUSED(%r15) (BPF frame pointer) */ 432 EMIT4_DISP(0x41000000, BPF_REG_FP, REG_15, STK_160_UNUSED); 433 /* aghi %r15,-STK_OFF */ 434 EMIT4_IMM(0xa70b0000, REG_15, -(STK_OFF + stack_depth)); 435 if (jit->seen & SEEN_FUNC) 436 /* stg %w1,152(%r15) (backchain) */ 437 EMIT6_DISP_LH(0xe3000000, 0x0024, REG_W1, REG_0, 438 REG_15, 152); 439 } 440 } 441 442 /* 443 * Function epilogue 444 */ 445 static void bpf_jit_epilogue(struct bpf_jit *jit, u32 stack_depth) 446 { 447 /* Return 0 */ 448 if (jit->seen & SEEN_RET0) { 449 jit->ret0_ip = jit->prg; 450 /* lghi %b0,0 */ 451 EMIT4_IMM(0xa7090000, BPF_REG_0, 0); 452 } 453 jit->exit_ip = jit->prg; 454 /* Load exit code: lgr %r2,%b0 */ 455 EMIT4(0xb9040000, REG_2, BPF_REG_0); 456 /* Restore registers */ 457 save_restore_regs(jit, REGS_RESTORE, stack_depth); 458 if (IS_ENABLED(CC_USING_EXPOLINE) && !nospec_disable) { 459 jit->r14_thunk_ip = jit->prg; 460 /* Generate __s390_indirect_jump_r14 thunk */ 461 if (test_facility(35)) { 462 /* exrl %r0,.+10 */ 463 EMIT6_PCREL_RIL(0xc6000000, jit->prg + 10); 464 } else { 465 /* larl %r1,.+14 */ 466 EMIT6_PCREL_RILB(0xc0000000, REG_1, jit->prg + 14); 467 /* ex 0,0(%r1) */ 468 EMIT4_DISP(0x44000000, REG_0, REG_1, 0); 469 } 470 /* j . */ 471 EMIT4_PCREL(0xa7f40000, 0); 472 } 473 /* br %r14 */ 474 _EMIT2(0x07fe); 475 476 if (IS_ENABLED(CC_USING_EXPOLINE) && !nospec_disable && 477 (jit->seen & SEEN_FUNC)) { 478 jit->r1_thunk_ip = jit->prg; 479 /* Generate __s390_indirect_jump_r1 thunk */ 480 if (test_facility(35)) { 481 /* exrl %r0,.+10 */ 482 EMIT6_PCREL_RIL(0xc6000000, jit->prg + 10); 483 /* j . */ 484 EMIT4_PCREL(0xa7f40000, 0); 485 /* br %r1 */ 486 _EMIT2(0x07f1); 487 } else { 488 /* larl %r1,.+14 */ 489 EMIT6_PCREL_RILB(0xc0000000, REG_1, jit->prg + 14); 490 /* ex 0,S390_lowcore.br_r1_tampoline */ 491 EMIT4_DISP(0x44000000, REG_0, REG_0, 492 offsetof(struct lowcore, br_r1_trampoline)); 493 /* j . */ 494 EMIT4_PCREL(0xa7f40000, 0); 495 } 496 } 497 } 498 499 /* 500 * Compile one eBPF instruction into s390x code 501 * 502 * NOTE: Use noinline because for gcov (-fprofile-arcs) gcc allocates a lot of 503 * stack space for the large switch statement. 504 */ 505 static noinline int bpf_jit_insn(struct bpf_jit *jit, struct bpf_prog *fp, int i) 506 { 507 struct bpf_insn *insn = &fp->insnsi[i]; 508 int jmp_off, last, insn_count = 1; 509 u32 dst_reg = insn->dst_reg; 510 u32 src_reg = insn->src_reg; 511 u32 *addrs = jit->addrs; 512 s32 imm = insn->imm; 513 s16 off = insn->off; 514 unsigned int mask; 515 516 if (dst_reg == BPF_REG_AX || src_reg == BPF_REG_AX) 517 jit->seen |= SEEN_REG_AX; 518 switch (insn->code) { 519 /* 520 * BPF_MOV 521 */ 522 case BPF_ALU | BPF_MOV | BPF_X: /* dst = (u32) src */ 523 /* llgfr %dst,%src */ 524 EMIT4(0xb9160000, dst_reg, src_reg); 525 break; 526 case BPF_ALU64 | BPF_MOV | BPF_X: /* dst = src */ 527 /* lgr %dst,%src */ 528 EMIT4(0xb9040000, dst_reg, src_reg); 529 break; 530 case BPF_ALU | BPF_MOV | BPF_K: /* dst = (u32) imm */ 531 /* llilf %dst,imm */ 532 EMIT6_IMM(0xc00f0000, dst_reg, imm); 533 break; 534 case BPF_ALU64 | BPF_MOV | BPF_K: /* dst = imm */ 535 /* lgfi %dst,imm */ 536 EMIT6_IMM(0xc0010000, dst_reg, imm); 537 break; 538 /* 539 * BPF_LD 64 540 */ 541 case BPF_LD | BPF_IMM | BPF_DW: /* dst = (u64) imm */ 542 { 543 /* 16 byte instruction that uses two 'struct bpf_insn' */ 544 u64 imm64; 545 546 imm64 = (u64)(u32) insn[0].imm | ((u64)(u32) insn[1].imm) << 32; 547 /* lg %dst,<d(imm)>(%l) */ 548 EMIT6_DISP_LH(0xe3000000, 0x0004, dst_reg, REG_0, REG_L, 549 EMIT_CONST_U64(imm64)); 550 insn_count = 2; 551 break; 552 } 553 /* 554 * BPF_ADD 555 */ 556 case BPF_ALU | BPF_ADD | BPF_X: /* dst = (u32) dst + (u32) src */ 557 /* ar %dst,%src */ 558 EMIT2(0x1a00, dst_reg, src_reg); 559 EMIT_ZERO(dst_reg); 560 break; 561 case BPF_ALU64 | BPF_ADD | BPF_X: /* dst = dst + src */ 562 /* agr %dst,%src */ 563 EMIT4(0xb9080000, dst_reg, src_reg); 564 break; 565 case BPF_ALU | BPF_ADD | BPF_K: /* dst = (u32) dst + (u32) imm */ 566 if (!imm) 567 break; 568 /* alfi %dst,imm */ 569 EMIT6_IMM(0xc20b0000, dst_reg, imm); 570 EMIT_ZERO(dst_reg); 571 break; 572 case BPF_ALU64 | BPF_ADD | BPF_K: /* dst = dst + imm */ 573 if (!imm) 574 break; 575 /* agfi %dst,imm */ 576 EMIT6_IMM(0xc2080000, dst_reg, imm); 577 break; 578 /* 579 * BPF_SUB 580 */ 581 case BPF_ALU | BPF_SUB | BPF_X: /* dst = (u32) dst - (u32) src */ 582 /* sr %dst,%src */ 583 EMIT2(0x1b00, dst_reg, src_reg); 584 EMIT_ZERO(dst_reg); 585 break; 586 case BPF_ALU64 | BPF_SUB | BPF_X: /* dst = dst - src */ 587 /* sgr %dst,%src */ 588 EMIT4(0xb9090000, dst_reg, src_reg); 589 break; 590 case BPF_ALU | BPF_SUB | BPF_K: /* dst = (u32) dst - (u32) imm */ 591 if (!imm) 592 break; 593 /* alfi %dst,-imm */ 594 EMIT6_IMM(0xc20b0000, dst_reg, -imm); 595 EMIT_ZERO(dst_reg); 596 break; 597 case BPF_ALU64 | BPF_SUB | BPF_K: /* dst = dst - imm */ 598 if (!imm) 599 break; 600 /* agfi %dst,-imm */ 601 EMIT6_IMM(0xc2080000, dst_reg, -imm); 602 break; 603 /* 604 * BPF_MUL 605 */ 606 case BPF_ALU | BPF_MUL | BPF_X: /* dst = (u32) dst * (u32) src */ 607 /* msr %dst,%src */ 608 EMIT4(0xb2520000, dst_reg, src_reg); 609 EMIT_ZERO(dst_reg); 610 break; 611 case BPF_ALU64 | BPF_MUL | BPF_X: /* dst = dst * src */ 612 /* msgr %dst,%src */ 613 EMIT4(0xb90c0000, dst_reg, src_reg); 614 break; 615 case BPF_ALU | BPF_MUL | BPF_K: /* dst = (u32) dst * (u32) imm */ 616 if (imm == 1) 617 break; 618 /* msfi %r5,imm */ 619 EMIT6_IMM(0xc2010000, dst_reg, imm); 620 EMIT_ZERO(dst_reg); 621 break; 622 case BPF_ALU64 | BPF_MUL | BPF_K: /* dst = dst * imm */ 623 if (imm == 1) 624 break; 625 /* msgfi %dst,imm */ 626 EMIT6_IMM(0xc2000000, dst_reg, imm); 627 break; 628 /* 629 * BPF_DIV / BPF_MOD 630 */ 631 case BPF_ALU | BPF_DIV | BPF_X: /* dst = (u32) dst / (u32) src */ 632 case BPF_ALU | BPF_MOD | BPF_X: /* dst = (u32) dst % (u32) src */ 633 { 634 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0; 635 636 /* lhi %w0,0 */ 637 EMIT4_IMM(0xa7080000, REG_W0, 0); 638 /* lr %w1,%dst */ 639 EMIT2(0x1800, REG_W1, dst_reg); 640 /* dlr %w0,%src */ 641 EMIT4(0xb9970000, REG_W0, src_reg); 642 /* llgfr %dst,%rc */ 643 EMIT4(0xb9160000, dst_reg, rc_reg); 644 break; 645 } 646 case BPF_ALU64 | BPF_DIV | BPF_X: /* dst = dst / src */ 647 case BPF_ALU64 | BPF_MOD | BPF_X: /* dst = dst % src */ 648 { 649 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0; 650 651 /* lghi %w0,0 */ 652 EMIT4_IMM(0xa7090000, REG_W0, 0); 653 /* lgr %w1,%dst */ 654 EMIT4(0xb9040000, REG_W1, dst_reg); 655 /* dlgr %w0,%dst */ 656 EMIT4(0xb9870000, REG_W0, src_reg); 657 /* lgr %dst,%rc */ 658 EMIT4(0xb9040000, dst_reg, rc_reg); 659 break; 660 } 661 case BPF_ALU | BPF_DIV | BPF_K: /* dst = (u32) dst / (u32) imm */ 662 case BPF_ALU | BPF_MOD | BPF_K: /* dst = (u32) dst % (u32) imm */ 663 { 664 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0; 665 666 if (imm == 1) { 667 if (BPF_OP(insn->code) == BPF_MOD) 668 /* lhgi %dst,0 */ 669 EMIT4_IMM(0xa7090000, dst_reg, 0); 670 break; 671 } 672 /* lhi %w0,0 */ 673 EMIT4_IMM(0xa7080000, REG_W0, 0); 674 /* lr %w1,%dst */ 675 EMIT2(0x1800, REG_W1, dst_reg); 676 /* dl %w0,<d(imm)>(%l) */ 677 EMIT6_DISP_LH(0xe3000000, 0x0097, REG_W0, REG_0, REG_L, 678 EMIT_CONST_U32(imm)); 679 /* llgfr %dst,%rc */ 680 EMIT4(0xb9160000, dst_reg, rc_reg); 681 break; 682 } 683 case BPF_ALU64 | BPF_DIV | BPF_K: /* dst = dst / imm */ 684 case BPF_ALU64 | BPF_MOD | BPF_K: /* dst = dst % imm */ 685 { 686 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0; 687 688 if (imm == 1) { 689 if (BPF_OP(insn->code) == BPF_MOD) 690 /* lhgi %dst,0 */ 691 EMIT4_IMM(0xa7090000, dst_reg, 0); 692 break; 693 } 694 /* lghi %w0,0 */ 695 EMIT4_IMM(0xa7090000, REG_W0, 0); 696 /* lgr %w1,%dst */ 697 EMIT4(0xb9040000, REG_W1, dst_reg); 698 /* dlg %w0,<d(imm)>(%l) */ 699 EMIT6_DISP_LH(0xe3000000, 0x0087, REG_W0, REG_0, REG_L, 700 EMIT_CONST_U64(imm)); 701 /* lgr %dst,%rc */ 702 EMIT4(0xb9040000, dst_reg, rc_reg); 703 break; 704 } 705 /* 706 * BPF_AND 707 */ 708 case BPF_ALU | BPF_AND | BPF_X: /* dst = (u32) dst & (u32) src */ 709 /* nr %dst,%src */ 710 EMIT2(0x1400, dst_reg, src_reg); 711 EMIT_ZERO(dst_reg); 712 break; 713 case BPF_ALU64 | BPF_AND | BPF_X: /* dst = dst & src */ 714 /* ngr %dst,%src */ 715 EMIT4(0xb9800000, dst_reg, src_reg); 716 break; 717 case BPF_ALU | BPF_AND | BPF_K: /* dst = (u32) dst & (u32) imm */ 718 /* nilf %dst,imm */ 719 EMIT6_IMM(0xc00b0000, dst_reg, imm); 720 EMIT_ZERO(dst_reg); 721 break; 722 case BPF_ALU64 | BPF_AND | BPF_K: /* dst = dst & imm */ 723 /* ng %dst,<d(imm)>(%l) */ 724 EMIT6_DISP_LH(0xe3000000, 0x0080, dst_reg, REG_0, REG_L, 725 EMIT_CONST_U64(imm)); 726 break; 727 /* 728 * BPF_OR 729 */ 730 case BPF_ALU | BPF_OR | BPF_X: /* dst = (u32) dst | (u32) src */ 731 /* or %dst,%src */ 732 EMIT2(0x1600, dst_reg, src_reg); 733 EMIT_ZERO(dst_reg); 734 break; 735 case BPF_ALU64 | BPF_OR | BPF_X: /* dst = dst | src */ 736 /* ogr %dst,%src */ 737 EMIT4(0xb9810000, dst_reg, src_reg); 738 break; 739 case BPF_ALU | BPF_OR | BPF_K: /* dst = (u32) dst | (u32) imm */ 740 /* oilf %dst,imm */ 741 EMIT6_IMM(0xc00d0000, dst_reg, imm); 742 EMIT_ZERO(dst_reg); 743 break; 744 case BPF_ALU64 | BPF_OR | BPF_K: /* dst = dst | imm */ 745 /* og %dst,<d(imm)>(%l) */ 746 EMIT6_DISP_LH(0xe3000000, 0x0081, dst_reg, REG_0, REG_L, 747 EMIT_CONST_U64(imm)); 748 break; 749 /* 750 * BPF_XOR 751 */ 752 case BPF_ALU | BPF_XOR | BPF_X: /* dst = (u32) dst ^ (u32) src */ 753 /* xr %dst,%src */ 754 EMIT2(0x1700, dst_reg, src_reg); 755 EMIT_ZERO(dst_reg); 756 break; 757 case BPF_ALU64 | BPF_XOR | BPF_X: /* dst = dst ^ src */ 758 /* xgr %dst,%src */ 759 EMIT4(0xb9820000, dst_reg, src_reg); 760 break; 761 case BPF_ALU | BPF_XOR | BPF_K: /* dst = (u32) dst ^ (u32) imm */ 762 if (!imm) 763 break; 764 /* xilf %dst,imm */ 765 EMIT6_IMM(0xc0070000, dst_reg, imm); 766 EMIT_ZERO(dst_reg); 767 break; 768 case BPF_ALU64 | BPF_XOR | BPF_K: /* dst = dst ^ imm */ 769 /* xg %dst,<d(imm)>(%l) */ 770 EMIT6_DISP_LH(0xe3000000, 0x0082, dst_reg, REG_0, REG_L, 771 EMIT_CONST_U64(imm)); 772 break; 773 /* 774 * BPF_LSH 775 */ 776 case BPF_ALU | BPF_LSH | BPF_X: /* dst = (u32) dst << (u32) src */ 777 /* sll %dst,0(%src) */ 778 EMIT4_DISP(0x89000000, dst_reg, src_reg, 0); 779 EMIT_ZERO(dst_reg); 780 break; 781 case BPF_ALU64 | BPF_LSH | BPF_X: /* dst = dst << src */ 782 /* sllg %dst,%dst,0(%src) */ 783 EMIT6_DISP_LH(0xeb000000, 0x000d, dst_reg, dst_reg, src_reg, 0); 784 break; 785 case BPF_ALU | BPF_LSH | BPF_K: /* dst = (u32) dst << (u32) imm */ 786 if (imm == 0) 787 break; 788 /* sll %dst,imm(%r0) */ 789 EMIT4_DISP(0x89000000, dst_reg, REG_0, imm); 790 EMIT_ZERO(dst_reg); 791 break; 792 case BPF_ALU64 | BPF_LSH | BPF_K: /* dst = dst << imm */ 793 if (imm == 0) 794 break; 795 /* sllg %dst,%dst,imm(%r0) */ 796 EMIT6_DISP_LH(0xeb000000, 0x000d, dst_reg, dst_reg, REG_0, imm); 797 break; 798 /* 799 * BPF_RSH 800 */ 801 case BPF_ALU | BPF_RSH | BPF_X: /* dst = (u32) dst >> (u32) src */ 802 /* srl %dst,0(%src) */ 803 EMIT4_DISP(0x88000000, dst_reg, src_reg, 0); 804 EMIT_ZERO(dst_reg); 805 break; 806 case BPF_ALU64 | BPF_RSH | BPF_X: /* dst = dst >> src */ 807 /* srlg %dst,%dst,0(%src) */ 808 EMIT6_DISP_LH(0xeb000000, 0x000c, dst_reg, dst_reg, src_reg, 0); 809 break; 810 case BPF_ALU | BPF_RSH | BPF_K: /* dst = (u32) dst >> (u32) imm */ 811 if (imm == 0) 812 break; 813 /* srl %dst,imm(%r0) */ 814 EMIT4_DISP(0x88000000, dst_reg, REG_0, imm); 815 EMIT_ZERO(dst_reg); 816 break; 817 case BPF_ALU64 | BPF_RSH | BPF_K: /* dst = dst >> imm */ 818 if (imm == 0) 819 break; 820 /* srlg %dst,%dst,imm(%r0) */ 821 EMIT6_DISP_LH(0xeb000000, 0x000c, dst_reg, dst_reg, REG_0, imm); 822 break; 823 /* 824 * BPF_ARSH 825 */ 826 case BPF_ALU64 | BPF_ARSH | BPF_X: /* ((s64) dst) >>= src */ 827 /* srag %dst,%dst,0(%src) */ 828 EMIT6_DISP_LH(0xeb000000, 0x000a, dst_reg, dst_reg, src_reg, 0); 829 break; 830 case BPF_ALU64 | BPF_ARSH | BPF_K: /* ((s64) dst) >>= imm */ 831 if (imm == 0) 832 break; 833 /* srag %dst,%dst,imm(%r0) */ 834 EMIT6_DISP_LH(0xeb000000, 0x000a, dst_reg, dst_reg, REG_0, imm); 835 break; 836 /* 837 * BPF_NEG 838 */ 839 case BPF_ALU | BPF_NEG: /* dst = (u32) -dst */ 840 /* lcr %dst,%dst */ 841 EMIT2(0x1300, dst_reg, dst_reg); 842 EMIT_ZERO(dst_reg); 843 break; 844 case BPF_ALU64 | BPF_NEG: /* dst = -dst */ 845 /* lcgr %dst,%dst */ 846 EMIT4(0xb9130000, dst_reg, dst_reg); 847 break; 848 /* 849 * BPF_FROM_BE/LE 850 */ 851 case BPF_ALU | BPF_END | BPF_FROM_BE: 852 /* s390 is big endian, therefore only clear high order bytes */ 853 switch (imm) { 854 case 16: /* dst = (u16) cpu_to_be16(dst) */ 855 /* llghr %dst,%dst */ 856 EMIT4(0xb9850000, dst_reg, dst_reg); 857 break; 858 case 32: /* dst = (u32) cpu_to_be32(dst) */ 859 /* llgfr %dst,%dst */ 860 EMIT4(0xb9160000, dst_reg, dst_reg); 861 break; 862 case 64: /* dst = (u64) cpu_to_be64(dst) */ 863 break; 864 } 865 break; 866 case BPF_ALU | BPF_END | BPF_FROM_LE: 867 switch (imm) { 868 case 16: /* dst = (u16) cpu_to_le16(dst) */ 869 /* lrvr %dst,%dst */ 870 EMIT4(0xb91f0000, dst_reg, dst_reg); 871 /* srl %dst,16(%r0) */ 872 EMIT4_DISP(0x88000000, dst_reg, REG_0, 16); 873 /* llghr %dst,%dst */ 874 EMIT4(0xb9850000, dst_reg, dst_reg); 875 break; 876 case 32: /* dst = (u32) cpu_to_le32(dst) */ 877 /* lrvr %dst,%dst */ 878 EMIT4(0xb91f0000, dst_reg, dst_reg); 879 /* llgfr %dst,%dst */ 880 EMIT4(0xb9160000, dst_reg, dst_reg); 881 break; 882 case 64: /* dst = (u64) cpu_to_le64(dst) */ 883 /* lrvgr %dst,%dst */ 884 EMIT4(0xb90f0000, dst_reg, dst_reg); 885 break; 886 } 887 break; 888 /* 889 * BPF_ST(X) 890 */ 891 case BPF_STX | BPF_MEM | BPF_B: /* *(u8 *)(dst + off) = src_reg */ 892 /* stcy %src,off(%dst) */ 893 EMIT6_DISP_LH(0xe3000000, 0x0072, src_reg, dst_reg, REG_0, off); 894 jit->seen |= SEEN_MEM; 895 break; 896 case BPF_STX | BPF_MEM | BPF_H: /* (u16 *)(dst + off) = src */ 897 /* sthy %src,off(%dst) */ 898 EMIT6_DISP_LH(0xe3000000, 0x0070, src_reg, dst_reg, REG_0, off); 899 jit->seen |= SEEN_MEM; 900 break; 901 case BPF_STX | BPF_MEM | BPF_W: /* *(u32 *)(dst + off) = src */ 902 /* sty %src,off(%dst) */ 903 EMIT6_DISP_LH(0xe3000000, 0x0050, src_reg, dst_reg, REG_0, off); 904 jit->seen |= SEEN_MEM; 905 break; 906 case BPF_STX | BPF_MEM | BPF_DW: /* (u64 *)(dst + off) = src */ 907 /* stg %src,off(%dst) */ 908 EMIT6_DISP_LH(0xe3000000, 0x0024, src_reg, dst_reg, REG_0, off); 909 jit->seen |= SEEN_MEM; 910 break; 911 case BPF_ST | BPF_MEM | BPF_B: /* *(u8 *)(dst + off) = imm */ 912 /* lhi %w0,imm */ 913 EMIT4_IMM(0xa7080000, REG_W0, (u8) imm); 914 /* stcy %w0,off(dst) */ 915 EMIT6_DISP_LH(0xe3000000, 0x0072, REG_W0, dst_reg, REG_0, off); 916 jit->seen |= SEEN_MEM; 917 break; 918 case BPF_ST | BPF_MEM | BPF_H: /* (u16 *)(dst + off) = imm */ 919 /* lhi %w0,imm */ 920 EMIT4_IMM(0xa7080000, REG_W0, (u16) imm); 921 /* sthy %w0,off(dst) */ 922 EMIT6_DISP_LH(0xe3000000, 0x0070, REG_W0, dst_reg, REG_0, off); 923 jit->seen |= SEEN_MEM; 924 break; 925 case BPF_ST | BPF_MEM | BPF_W: /* *(u32 *)(dst + off) = imm */ 926 /* llilf %w0,imm */ 927 EMIT6_IMM(0xc00f0000, REG_W0, (u32) imm); 928 /* sty %w0,off(%dst) */ 929 EMIT6_DISP_LH(0xe3000000, 0x0050, REG_W0, dst_reg, REG_0, off); 930 jit->seen |= SEEN_MEM; 931 break; 932 case BPF_ST | BPF_MEM | BPF_DW: /* *(u64 *)(dst + off) = imm */ 933 /* lgfi %w0,imm */ 934 EMIT6_IMM(0xc0010000, REG_W0, imm); 935 /* stg %w0,off(%dst) */ 936 EMIT6_DISP_LH(0xe3000000, 0x0024, REG_W0, dst_reg, REG_0, off); 937 jit->seen |= SEEN_MEM; 938 break; 939 /* 940 * BPF_STX XADD (atomic_add) 941 */ 942 case BPF_STX | BPF_XADD | BPF_W: /* *(u32 *)(dst + off) += src */ 943 /* laal %w0,%src,off(%dst) */ 944 EMIT6_DISP_LH(0xeb000000, 0x00fa, REG_W0, src_reg, 945 dst_reg, off); 946 jit->seen |= SEEN_MEM; 947 break; 948 case BPF_STX | BPF_XADD | BPF_DW: /* *(u64 *)(dst + off) += src */ 949 /* laalg %w0,%src,off(%dst) */ 950 EMIT6_DISP_LH(0xeb000000, 0x00ea, REG_W0, src_reg, 951 dst_reg, off); 952 jit->seen |= SEEN_MEM; 953 break; 954 /* 955 * BPF_LDX 956 */ 957 case BPF_LDX | BPF_MEM | BPF_B: /* dst = *(u8 *)(ul) (src + off) */ 958 /* llgc %dst,0(off,%src) */ 959 EMIT6_DISP_LH(0xe3000000, 0x0090, dst_reg, src_reg, REG_0, off); 960 jit->seen |= SEEN_MEM; 961 break; 962 case BPF_LDX | BPF_MEM | BPF_H: /* dst = *(u16 *)(ul) (src + off) */ 963 /* llgh %dst,0(off,%src) */ 964 EMIT6_DISP_LH(0xe3000000, 0x0091, dst_reg, src_reg, REG_0, off); 965 jit->seen |= SEEN_MEM; 966 break; 967 case BPF_LDX | BPF_MEM | BPF_W: /* dst = *(u32 *)(ul) (src + off) */ 968 /* llgf %dst,off(%src) */ 969 jit->seen |= SEEN_MEM; 970 EMIT6_DISP_LH(0xe3000000, 0x0016, dst_reg, src_reg, REG_0, off); 971 break; 972 case BPF_LDX | BPF_MEM | BPF_DW: /* dst = *(u64 *)(ul) (src + off) */ 973 /* lg %dst,0(off,%src) */ 974 jit->seen |= SEEN_MEM; 975 EMIT6_DISP_LH(0xe3000000, 0x0004, dst_reg, src_reg, REG_0, off); 976 break; 977 /* 978 * BPF_JMP / CALL 979 */ 980 case BPF_JMP | BPF_CALL: 981 { 982 /* 983 * b0 = (__bpf_call_base + imm)(b1, b2, b3, b4, b5) 984 */ 985 const u64 func = (u64)__bpf_call_base + imm; 986 987 REG_SET_SEEN(BPF_REG_5); 988 jit->seen |= SEEN_FUNC; 989 /* lg %w1,<d(imm)>(%l) */ 990 EMIT6_DISP_LH(0xe3000000, 0x0004, REG_W1, REG_0, REG_L, 991 EMIT_CONST_U64(func)); 992 if (IS_ENABLED(CC_USING_EXPOLINE) && !nospec_disable) { 993 /* brasl %r14,__s390_indirect_jump_r1 */ 994 EMIT6_PCREL_RILB(0xc0050000, REG_14, jit->r1_thunk_ip); 995 } else { 996 /* basr %r14,%w1 */ 997 EMIT2(0x0d00, REG_14, REG_W1); 998 } 999 /* lgr %b0,%r2: load return value into %b0 */ 1000 EMIT4(0xb9040000, BPF_REG_0, REG_2); 1001 break; 1002 } 1003 case BPF_JMP | BPF_TAIL_CALL: 1004 /* 1005 * Implicit input: 1006 * B1: pointer to ctx 1007 * B2: pointer to bpf_array 1008 * B3: index in bpf_array 1009 */ 1010 jit->seen |= SEEN_TAIL_CALL; 1011 1012 /* 1013 * if (index >= array->map.max_entries) 1014 * goto out; 1015 */ 1016 1017 /* llgf %w1,map.max_entries(%b2) */ 1018 EMIT6_DISP_LH(0xe3000000, 0x0016, REG_W1, REG_0, BPF_REG_2, 1019 offsetof(struct bpf_array, map.max_entries)); 1020 /* clgrj %b3,%w1,0xa,label0: if %b3 >= %w1 goto out */ 1021 EMIT6_PCREL_LABEL(0xec000000, 0x0065, BPF_REG_3, 1022 REG_W1, 0, 0xa); 1023 1024 /* 1025 * if (tail_call_cnt++ > MAX_TAIL_CALL_CNT) 1026 * goto out; 1027 */ 1028 1029 if (jit->seen & SEEN_STACK) 1030 off = STK_OFF_TCCNT + STK_OFF + fp->aux->stack_depth; 1031 else 1032 off = STK_OFF_TCCNT; 1033 /* lhi %w0,1 */ 1034 EMIT4_IMM(0xa7080000, REG_W0, 1); 1035 /* laal %w1,%w0,off(%r15) */ 1036 EMIT6_DISP_LH(0xeb000000, 0x00fa, REG_W1, REG_W0, REG_15, off); 1037 /* clij %w1,MAX_TAIL_CALL_CNT,0x2,label0 */ 1038 EMIT6_PCREL_IMM_LABEL(0xec000000, 0x007f, REG_W1, 1039 MAX_TAIL_CALL_CNT, 0, 0x2); 1040 1041 /* 1042 * prog = array->ptrs[index]; 1043 * if (prog == NULL) 1044 * goto out; 1045 */ 1046 1047 /* sllg %r1,%b3,3: %r1 = index * 8 */ 1048 EMIT6_DISP_LH(0xeb000000, 0x000d, REG_1, BPF_REG_3, REG_0, 3); 1049 /* lg %r1,prog(%b2,%r1) */ 1050 EMIT6_DISP_LH(0xe3000000, 0x0004, REG_1, BPF_REG_2, 1051 REG_1, offsetof(struct bpf_array, ptrs)); 1052 /* clgij %r1,0,0x8,label0 */ 1053 EMIT6_PCREL_IMM_LABEL(0xec000000, 0x007d, REG_1, 0, 0, 0x8); 1054 1055 /* 1056 * Restore registers before calling function 1057 */ 1058 save_restore_regs(jit, REGS_RESTORE, fp->aux->stack_depth); 1059 1060 /* 1061 * goto *(prog->bpf_func + tail_call_start); 1062 */ 1063 1064 /* lg %r1,bpf_func(%r1) */ 1065 EMIT6_DISP_LH(0xe3000000, 0x0004, REG_1, REG_1, REG_0, 1066 offsetof(struct bpf_prog, bpf_func)); 1067 /* bc 0xf,tail_call_start(%r1) */ 1068 _EMIT4(0x47f01000 + jit->tail_call_start); 1069 /* out: */ 1070 jit->labels[0] = jit->prg; 1071 break; 1072 case BPF_JMP | BPF_EXIT: /* return b0 */ 1073 last = (i == fp->len - 1) ? 1 : 0; 1074 if (last && !(jit->seen & SEEN_RET0)) 1075 break; 1076 /* j <exit> */ 1077 EMIT4_PCREL(0xa7f40000, jit->exit_ip - jit->prg); 1078 break; 1079 /* 1080 * Branch relative (number of skipped instructions) to offset on 1081 * condition. 1082 * 1083 * Condition code to mask mapping: 1084 * 1085 * CC | Description | Mask 1086 * ------------------------------ 1087 * 0 | Operands equal | 8 1088 * 1 | First operand low | 4 1089 * 2 | First operand high | 2 1090 * 3 | Unused | 1 1091 * 1092 * For s390x relative branches: ip = ip + off_bytes 1093 * For BPF relative branches: insn = insn + off_insns + 1 1094 * 1095 * For example for s390x with offset 0 we jump to the branch 1096 * instruction itself (loop) and for BPF with offset 0 we 1097 * branch to the instruction behind the branch. 1098 */ 1099 case BPF_JMP | BPF_JA: /* if (true) */ 1100 mask = 0xf000; /* j */ 1101 goto branch_oc; 1102 case BPF_JMP | BPF_JSGT | BPF_K: /* ((s64) dst > (s64) imm) */ 1103 mask = 0x2000; /* jh */ 1104 goto branch_ks; 1105 case BPF_JMP | BPF_JSLT | BPF_K: /* ((s64) dst < (s64) imm) */ 1106 mask = 0x4000; /* jl */ 1107 goto branch_ks; 1108 case BPF_JMP | BPF_JSGE | BPF_K: /* ((s64) dst >= (s64) imm) */ 1109 mask = 0xa000; /* jhe */ 1110 goto branch_ks; 1111 case BPF_JMP | BPF_JSLE | BPF_K: /* ((s64) dst <= (s64) imm) */ 1112 mask = 0xc000; /* jle */ 1113 goto branch_ks; 1114 case BPF_JMP | BPF_JGT | BPF_K: /* (dst_reg > imm) */ 1115 mask = 0x2000; /* jh */ 1116 goto branch_ku; 1117 case BPF_JMP | BPF_JLT | BPF_K: /* (dst_reg < imm) */ 1118 mask = 0x4000; /* jl */ 1119 goto branch_ku; 1120 case BPF_JMP | BPF_JGE | BPF_K: /* (dst_reg >= imm) */ 1121 mask = 0xa000; /* jhe */ 1122 goto branch_ku; 1123 case BPF_JMP | BPF_JLE | BPF_K: /* (dst_reg <= imm) */ 1124 mask = 0xc000; /* jle */ 1125 goto branch_ku; 1126 case BPF_JMP | BPF_JNE | BPF_K: /* (dst_reg != imm) */ 1127 mask = 0x7000; /* jne */ 1128 goto branch_ku; 1129 case BPF_JMP | BPF_JEQ | BPF_K: /* (dst_reg == imm) */ 1130 mask = 0x8000; /* je */ 1131 goto branch_ku; 1132 case BPF_JMP | BPF_JSET | BPF_K: /* (dst_reg & imm) */ 1133 mask = 0x7000; /* jnz */ 1134 /* lgfi %w1,imm (load sign extend imm) */ 1135 EMIT6_IMM(0xc0010000, REG_W1, imm); 1136 /* ngr %w1,%dst */ 1137 EMIT4(0xb9800000, REG_W1, dst_reg); 1138 goto branch_oc; 1139 1140 case BPF_JMP | BPF_JSGT | BPF_X: /* ((s64) dst > (s64) src) */ 1141 mask = 0x2000; /* jh */ 1142 goto branch_xs; 1143 case BPF_JMP | BPF_JSLT | BPF_X: /* ((s64) dst < (s64) src) */ 1144 mask = 0x4000; /* jl */ 1145 goto branch_xs; 1146 case BPF_JMP | BPF_JSGE | BPF_X: /* ((s64) dst >= (s64) src) */ 1147 mask = 0xa000; /* jhe */ 1148 goto branch_xs; 1149 case BPF_JMP | BPF_JSLE | BPF_X: /* ((s64) dst <= (s64) src) */ 1150 mask = 0xc000; /* jle */ 1151 goto branch_xs; 1152 case BPF_JMP | BPF_JGT | BPF_X: /* (dst > src) */ 1153 mask = 0x2000; /* jh */ 1154 goto branch_xu; 1155 case BPF_JMP | BPF_JLT | BPF_X: /* (dst < src) */ 1156 mask = 0x4000; /* jl */ 1157 goto branch_xu; 1158 case BPF_JMP | BPF_JGE | BPF_X: /* (dst >= src) */ 1159 mask = 0xa000; /* jhe */ 1160 goto branch_xu; 1161 case BPF_JMP | BPF_JLE | BPF_X: /* (dst <= src) */ 1162 mask = 0xc000; /* jle */ 1163 goto branch_xu; 1164 case BPF_JMP | BPF_JNE | BPF_X: /* (dst != src) */ 1165 mask = 0x7000; /* jne */ 1166 goto branch_xu; 1167 case BPF_JMP | BPF_JEQ | BPF_X: /* (dst == src) */ 1168 mask = 0x8000; /* je */ 1169 goto branch_xu; 1170 case BPF_JMP | BPF_JSET | BPF_X: /* (dst & src) */ 1171 mask = 0x7000; /* jnz */ 1172 /* ngrk %w1,%dst,%src */ 1173 EMIT4_RRF(0xb9e40000, REG_W1, dst_reg, src_reg); 1174 goto branch_oc; 1175 branch_ks: 1176 /* lgfi %w1,imm (load sign extend imm) */ 1177 EMIT6_IMM(0xc0010000, REG_W1, imm); 1178 /* cgrj %dst,%w1,mask,off */ 1179 EMIT6_PCREL(0xec000000, 0x0064, dst_reg, REG_W1, i, off, mask); 1180 break; 1181 branch_ku: 1182 /* lgfi %w1,imm (load sign extend imm) */ 1183 EMIT6_IMM(0xc0010000, REG_W1, imm); 1184 /* clgrj %dst,%w1,mask,off */ 1185 EMIT6_PCREL(0xec000000, 0x0065, dst_reg, REG_W1, i, off, mask); 1186 break; 1187 branch_xs: 1188 /* cgrj %dst,%src,mask,off */ 1189 EMIT6_PCREL(0xec000000, 0x0064, dst_reg, src_reg, i, off, mask); 1190 break; 1191 branch_xu: 1192 /* clgrj %dst,%src,mask,off */ 1193 EMIT6_PCREL(0xec000000, 0x0065, dst_reg, src_reg, i, off, mask); 1194 break; 1195 branch_oc: 1196 /* brc mask,jmp_off (branch instruction needs 4 bytes) */ 1197 jmp_off = addrs[i + off + 1] - (addrs[i + 1] - 4); 1198 EMIT4_PCREL(0xa7040000 | mask << 8, jmp_off); 1199 break; 1200 default: /* too complex, give up */ 1201 pr_err("Unknown opcode %02x\n", insn->code); 1202 return -1; 1203 } 1204 return insn_count; 1205 } 1206 1207 /* 1208 * Compile eBPF program into s390x code 1209 */ 1210 static int bpf_jit_prog(struct bpf_jit *jit, struct bpf_prog *fp) 1211 { 1212 int i, insn_count; 1213 1214 jit->lit = jit->lit_start; 1215 jit->prg = 0; 1216 1217 bpf_jit_prologue(jit, fp->aux->stack_depth); 1218 for (i = 0; i < fp->len; i += insn_count) { 1219 insn_count = bpf_jit_insn(jit, fp, i); 1220 if (insn_count < 0) 1221 return -1; 1222 /* Next instruction address */ 1223 jit->addrs[i + insn_count] = jit->prg; 1224 } 1225 bpf_jit_epilogue(jit, fp->aux->stack_depth); 1226 1227 jit->lit_start = jit->prg; 1228 jit->size = jit->lit; 1229 jit->size_prg = jit->prg; 1230 return 0; 1231 } 1232 1233 /* 1234 * Compile eBPF program "fp" 1235 */ 1236 struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *fp) 1237 { 1238 struct bpf_prog *tmp, *orig_fp = fp; 1239 struct bpf_binary_header *header; 1240 bool tmp_blinded = false; 1241 struct bpf_jit jit; 1242 int pass; 1243 1244 if (!fp->jit_requested) 1245 return orig_fp; 1246 1247 tmp = bpf_jit_blind_constants(fp); 1248 /* 1249 * If blinding was requested and we failed during blinding, 1250 * we must fall back to the interpreter. 1251 */ 1252 if (IS_ERR(tmp)) 1253 return orig_fp; 1254 if (tmp != fp) { 1255 tmp_blinded = true; 1256 fp = tmp; 1257 } 1258 1259 memset(&jit, 0, sizeof(jit)); 1260 jit.addrs = kcalloc(fp->len + 1, sizeof(*jit.addrs), GFP_KERNEL); 1261 if (jit.addrs == NULL) { 1262 fp = orig_fp; 1263 goto out; 1264 } 1265 /* 1266 * Three initial passes: 1267 * - 1/2: Determine clobbered registers 1268 * - 3: Calculate program size and addrs arrray 1269 */ 1270 for (pass = 1; pass <= 3; pass++) { 1271 if (bpf_jit_prog(&jit, fp)) { 1272 fp = orig_fp; 1273 goto free_addrs; 1274 } 1275 } 1276 /* 1277 * Final pass: Allocate and generate program 1278 */ 1279 if (jit.size >= BPF_SIZE_MAX) { 1280 fp = orig_fp; 1281 goto free_addrs; 1282 } 1283 header = bpf_jit_binary_alloc(jit.size, &jit.prg_buf, 2, jit_fill_hole); 1284 if (!header) { 1285 fp = orig_fp; 1286 goto free_addrs; 1287 } 1288 if (bpf_jit_prog(&jit, fp)) { 1289 fp = orig_fp; 1290 goto free_addrs; 1291 } 1292 if (bpf_jit_enable > 1) { 1293 bpf_jit_dump(fp->len, jit.size, pass, jit.prg_buf); 1294 print_fn_code(jit.prg_buf, jit.size_prg); 1295 } 1296 bpf_jit_binary_lock_ro(header); 1297 fp->bpf_func = (void *) jit.prg_buf; 1298 fp->jited = 1; 1299 fp->jited_len = jit.size; 1300 free_addrs: 1301 kfree(jit.addrs); 1302 out: 1303 if (tmp_blinded) 1304 bpf_jit_prog_release_other(fp, fp == orig_fp ? 1305 tmp : orig_fp); 1306 return fp; 1307 } 1308