1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * BPF Jit compiler for s390. 4 * 5 * Minimum build requirements: 6 * 7 * - HAVE_MARCH_Z196_FEATURES: laal, laalg 8 * - HAVE_MARCH_Z10_FEATURES: msfi, cgrj, clgrj 9 * - HAVE_MARCH_Z9_109_FEATURES: alfi, llilf, clfi, oilf, nilf 10 * - PACK_STACK 11 * - 64BIT 12 * 13 * Copyright IBM Corp. 2012,2015 14 * 15 * Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com> 16 * Michael Holzheu <holzheu@linux.vnet.ibm.com> 17 */ 18 19 #define KMSG_COMPONENT "bpf_jit" 20 #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt 21 22 #include <linux/netdevice.h> 23 #include <linux/filter.h> 24 #include <linux/init.h> 25 #include <linux/bpf.h> 26 #include <linux/mm.h> 27 #include <linux/kernel.h> 28 #include <asm/cacheflush.h> 29 #include <asm/dis.h> 30 #include <asm/facility.h> 31 #include <asm/nospec-branch.h> 32 #include <asm/set_memory.h> 33 #include "bpf_jit.h" 34 35 struct bpf_jit { 36 u32 seen; /* Flags to remember seen eBPF instructions */ 37 u32 seen_reg[16]; /* Array to remember which registers are used */ 38 u32 *addrs; /* Array with relative instruction addresses */ 39 u8 *prg_buf; /* Start of program */ 40 int size; /* Size of program and literal pool */ 41 int size_prg; /* Size of program */ 42 int prg; /* Current position in program */ 43 int lit32_start; /* Start of 32-bit literal pool */ 44 int lit32; /* Current position in 32-bit literal pool */ 45 int lit64_start; /* Start of 64-bit literal pool */ 46 int lit64; /* Current position in 64-bit literal pool */ 47 int base_ip; /* Base address for literal pool */ 48 int exit_ip; /* Address of exit */ 49 int r1_thunk_ip; /* Address of expoline thunk for 'br %r1' */ 50 int r14_thunk_ip; /* Address of expoline thunk for 'br %r14' */ 51 int tail_call_start; /* Tail call start offset */ 52 int labels[1]; /* Labels for local jumps */ 53 }; 54 55 #define SEEN_MEM BIT(0) /* use mem[] for temporary storage */ 56 #define SEEN_LITERAL BIT(1) /* code uses literals */ 57 #define SEEN_FUNC BIT(2) /* calls C functions */ 58 #define SEEN_TAIL_CALL BIT(3) /* code uses tail calls */ 59 #define SEEN_STACK (SEEN_FUNC | SEEN_MEM) 60 61 /* 62 * s390 registers 63 */ 64 #define REG_W0 (MAX_BPF_JIT_REG + 0) /* Work register 1 (even) */ 65 #define REG_W1 (MAX_BPF_JIT_REG + 1) /* Work register 2 (odd) */ 66 #define REG_L (MAX_BPF_JIT_REG + 2) /* Literal pool register */ 67 #define REG_15 (MAX_BPF_JIT_REG + 3) /* Register 15 */ 68 #define REG_0 REG_W0 /* Register 0 */ 69 #define REG_1 REG_W1 /* Register 1 */ 70 #define REG_2 BPF_REG_1 /* Register 2 */ 71 #define REG_14 BPF_REG_0 /* Register 14 */ 72 73 /* 74 * Mapping of BPF registers to s390 registers 75 */ 76 static const int reg2hex[] = { 77 /* Return code */ 78 [BPF_REG_0] = 14, 79 /* Function parameters */ 80 [BPF_REG_1] = 2, 81 [BPF_REG_2] = 3, 82 [BPF_REG_3] = 4, 83 [BPF_REG_4] = 5, 84 [BPF_REG_5] = 6, 85 /* Call saved registers */ 86 [BPF_REG_6] = 7, 87 [BPF_REG_7] = 8, 88 [BPF_REG_8] = 9, 89 [BPF_REG_9] = 10, 90 /* BPF stack pointer */ 91 [BPF_REG_FP] = 13, 92 /* Register for blinding */ 93 [BPF_REG_AX] = 12, 94 /* Work registers for s390x backend */ 95 [REG_W0] = 0, 96 [REG_W1] = 1, 97 [REG_L] = 11, 98 [REG_15] = 15, 99 }; 100 101 static inline u32 reg(u32 dst_reg, u32 src_reg) 102 { 103 return reg2hex[dst_reg] << 4 | reg2hex[src_reg]; 104 } 105 106 static inline u32 reg_high(u32 reg) 107 { 108 return reg2hex[reg] << 4; 109 } 110 111 static inline void reg_set_seen(struct bpf_jit *jit, u32 b1) 112 { 113 u32 r1 = reg2hex[b1]; 114 115 if (!jit->seen_reg[r1] && r1 >= 6 && r1 <= 15) 116 jit->seen_reg[r1] = 1; 117 } 118 119 #define REG_SET_SEEN(b1) \ 120 ({ \ 121 reg_set_seen(jit, b1); \ 122 }) 123 124 #define REG_SEEN(b1) jit->seen_reg[reg2hex[(b1)]] 125 126 /* 127 * EMIT macros for code generation 128 */ 129 130 #define _EMIT2(op) \ 131 ({ \ 132 if (jit->prg_buf) \ 133 *(u16 *) (jit->prg_buf + jit->prg) = (op); \ 134 jit->prg += 2; \ 135 }) 136 137 #define EMIT2(op, b1, b2) \ 138 ({ \ 139 _EMIT2((op) | reg(b1, b2)); \ 140 REG_SET_SEEN(b1); \ 141 REG_SET_SEEN(b2); \ 142 }) 143 144 #define _EMIT4(op) \ 145 ({ \ 146 if (jit->prg_buf) \ 147 *(u32 *) (jit->prg_buf + jit->prg) = (op); \ 148 jit->prg += 4; \ 149 }) 150 151 #define EMIT4(op, b1, b2) \ 152 ({ \ 153 _EMIT4((op) | reg(b1, b2)); \ 154 REG_SET_SEEN(b1); \ 155 REG_SET_SEEN(b2); \ 156 }) 157 158 #define EMIT4_RRF(op, b1, b2, b3) \ 159 ({ \ 160 _EMIT4((op) | reg_high(b3) << 8 | reg(b1, b2)); \ 161 REG_SET_SEEN(b1); \ 162 REG_SET_SEEN(b2); \ 163 REG_SET_SEEN(b3); \ 164 }) 165 166 #define _EMIT4_DISP(op, disp) \ 167 ({ \ 168 unsigned int __disp = (disp) & 0xfff; \ 169 _EMIT4((op) | __disp); \ 170 }) 171 172 #define EMIT4_DISP(op, b1, b2, disp) \ 173 ({ \ 174 _EMIT4_DISP((op) | reg_high(b1) << 16 | \ 175 reg_high(b2) << 8, (disp)); \ 176 REG_SET_SEEN(b1); \ 177 REG_SET_SEEN(b2); \ 178 }) 179 180 #define EMIT4_IMM(op, b1, imm) \ 181 ({ \ 182 unsigned int __imm = (imm) & 0xffff; \ 183 _EMIT4((op) | reg_high(b1) << 16 | __imm); \ 184 REG_SET_SEEN(b1); \ 185 }) 186 187 #define EMIT4_PCREL(op, pcrel) \ 188 ({ \ 189 long __pcrel = ((pcrel) >> 1) & 0xffff; \ 190 _EMIT4((op) | __pcrel); \ 191 }) 192 193 #define EMIT4_PCREL_RIC(op, mask, target) \ 194 ({ \ 195 int __rel = ((target) - jit->prg) / 2; \ 196 _EMIT4((op) | (mask) << 20 | (__rel & 0xffff)); \ 197 }) 198 199 #define _EMIT6(op1, op2) \ 200 ({ \ 201 if (jit->prg_buf) { \ 202 *(u32 *) (jit->prg_buf + jit->prg) = (op1); \ 203 *(u16 *) (jit->prg_buf + jit->prg + 4) = (op2); \ 204 } \ 205 jit->prg += 6; \ 206 }) 207 208 #define _EMIT6_DISP(op1, op2, disp) \ 209 ({ \ 210 unsigned int __disp = (disp) & 0xfff; \ 211 _EMIT6((op1) | __disp, op2); \ 212 }) 213 214 #define _EMIT6_DISP_LH(op1, op2, disp) \ 215 ({ \ 216 u32 _disp = (u32) (disp); \ 217 unsigned int __disp_h = _disp & 0xff000; \ 218 unsigned int __disp_l = _disp & 0x00fff; \ 219 _EMIT6((op1) | __disp_l, (op2) | __disp_h >> 4); \ 220 }) 221 222 #define EMIT6_DISP_LH(op1, op2, b1, b2, b3, disp) \ 223 ({ \ 224 _EMIT6_DISP_LH((op1) | reg(b1, b2) << 16 | \ 225 reg_high(b3) << 8, op2, disp); \ 226 REG_SET_SEEN(b1); \ 227 REG_SET_SEEN(b2); \ 228 REG_SET_SEEN(b3); \ 229 }) 230 231 #define EMIT6_PCREL_LABEL(op1, op2, b1, b2, label, mask) \ 232 ({ \ 233 int rel = (jit->labels[label] - jit->prg) >> 1; \ 234 _EMIT6((op1) | reg(b1, b2) << 16 | (rel & 0xffff), \ 235 (op2) | (mask) << 12); \ 236 REG_SET_SEEN(b1); \ 237 REG_SET_SEEN(b2); \ 238 }) 239 240 #define EMIT6_PCREL_IMM_LABEL(op1, op2, b1, imm, label, mask) \ 241 ({ \ 242 int rel = (jit->labels[label] - jit->prg) >> 1; \ 243 _EMIT6((op1) | (reg_high(b1) | (mask)) << 16 | \ 244 (rel & 0xffff), (op2) | ((imm) & 0xff) << 8); \ 245 REG_SET_SEEN(b1); \ 246 BUILD_BUG_ON(((unsigned long) (imm)) > 0xff); \ 247 }) 248 249 #define EMIT6_PCREL(op1, op2, b1, b2, i, off, mask) \ 250 ({ \ 251 /* Branch instruction needs 6 bytes */ \ 252 int rel = (addrs[(i) + (off) + 1] - (addrs[(i) + 1] - 6)) / 2;\ 253 _EMIT6((op1) | reg(b1, b2) << 16 | (rel & 0xffff), (op2) | (mask));\ 254 REG_SET_SEEN(b1); \ 255 REG_SET_SEEN(b2); \ 256 }) 257 258 #define EMIT6_PCREL_RILB(op, b, target) \ 259 ({ \ 260 unsigned int rel = (int)((target) - jit->prg) / 2; \ 261 _EMIT6((op) | reg_high(b) << 16 | rel >> 16, rel & 0xffff);\ 262 REG_SET_SEEN(b); \ 263 }) 264 265 #define EMIT6_PCREL_RIL(op, target) \ 266 ({ \ 267 unsigned int rel = (int)((target) - jit->prg) / 2; \ 268 _EMIT6((op) | rel >> 16, rel & 0xffff); \ 269 }) 270 271 #define EMIT6_PCREL_RILC(op, mask, target) \ 272 ({ \ 273 EMIT6_PCREL_RIL((op) | (mask) << 20, (target)); \ 274 }) 275 276 #define _EMIT6_IMM(op, imm) \ 277 ({ \ 278 unsigned int __imm = (imm); \ 279 _EMIT6((op) | (__imm >> 16), __imm & 0xffff); \ 280 }) 281 282 #define EMIT6_IMM(op, b1, imm) \ 283 ({ \ 284 _EMIT6_IMM((op) | reg_high(b1) << 16, imm); \ 285 REG_SET_SEEN(b1); \ 286 }) 287 288 #define _EMIT_CONST_U32(val) \ 289 ({ \ 290 unsigned int ret; \ 291 ret = jit->lit32; \ 292 if (jit->prg_buf) \ 293 *(u32 *)(jit->prg_buf + jit->lit32) = (u32)(val);\ 294 jit->lit32 += 4; \ 295 ret; \ 296 }) 297 298 #define EMIT_CONST_U32(val) \ 299 ({ \ 300 jit->seen |= SEEN_LITERAL; \ 301 _EMIT_CONST_U32(val) - jit->base_ip; \ 302 }) 303 304 #define _EMIT_CONST_U64(val) \ 305 ({ \ 306 unsigned int ret; \ 307 ret = jit->lit64; \ 308 if (jit->prg_buf) \ 309 *(u64 *)(jit->prg_buf + jit->lit64) = (u64)(val);\ 310 jit->lit64 += 8; \ 311 ret; \ 312 }) 313 314 #define EMIT_CONST_U64(val) \ 315 ({ \ 316 jit->seen |= SEEN_LITERAL; \ 317 _EMIT_CONST_U64(val) - jit->base_ip; \ 318 }) 319 320 #define EMIT_ZERO(b1) \ 321 ({ \ 322 if (!fp->aux->verifier_zext) { \ 323 /* llgfr %dst,%dst (zero extend to 64 bit) */ \ 324 EMIT4(0xb9160000, b1, b1); \ 325 REG_SET_SEEN(b1); \ 326 } \ 327 }) 328 329 /* 330 * Return whether this is the first pass. The first pass is special, since we 331 * don't know any sizes yet, and thus must be conservative. 332 */ 333 static bool is_first_pass(struct bpf_jit *jit) 334 { 335 return jit->size == 0; 336 } 337 338 /* 339 * Return whether this is the code generation pass. The code generation pass is 340 * special, since we should change as little as possible. 341 */ 342 static bool is_codegen_pass(struct bpf_jit *jit) 343 { 344 return jit->prg_buf; 345 } 346 347 /* 348 * Return whether "rel" can be encoded as a short PC-relative offset 349 */ 350 static bool is_valid_rel(int rel) 351 { 352 return rel >= -65536 && rel <= 65534; 353 } 354 355 /* 356 * Return whether "off" can be reached using a short PC-relative offset 357 */ 358 static bool can_use_rel(struct bpf_jit *jit, int off) 359 { 360 return is_valid_rel(off - jit->prg); 361 } 362 363 /* 364 * Return whether given displacement can be encoded using 365 * Long-Displacement Facility 366 */ 367 static bool is_valid_ldisp(int disp) 368 { 369 return disp >= -524288 && disp <= 524287; 370 } 371 372 /* 373 * Return whether the next 32-bit literal pool entry can be referenced using 374 * Long-Displacement Facility 375 */ 376 static bool can_use_ldisp_for_lit32(struct bpf_jit *jit) 377 { 378 return is_valid_ldisp(jit->lit32 - jit->base_ip); 379 } 380 381 /* 382 * Return whether the next 64-bit literal pool entry can be referenced using 383 * Long-Displacement Facility 384 */ 385 static bool can_use_ldisp_for_lit64(struct bpf_jit *jit) 386 { 387 return is_valid_ldisp(jit->lit64 - jit->base_ip); 388 } 389 390 /* 391 * Fill whole space with illegal instructions 392 */ 393 static void jit_fill_hole(void *area, unsigned int size) 394 { 395 memset(area, 0, size); 396 } 397 398 /* 399 * Save registers from "rs" (register start) to "re" (register end) on stack 400 */ 401 static void save_regs(struct bpf_jit *jit, u32 rs, u32 re) 402 { 403 u32 off = STK_OFF_R6 + (rs - 6) * 8; 404 405 if (rs == re) 406 /* stg %rs,off(%r15) */ 407 _EMIT6(0xe300f000 | rs << 20 | off, 0x0024); 408 else 409 /* stmg %rs,%re,off(%r15) */ 410 _EMIT6_DISP(0xeb00f000 | rs << 20 | re << 16, 0x0024, off); 411 } 412 413 /* 414 * Restore registers from "rs" (register start) to "re" (register end) on stack 415 */ 416 static void restore_regs(struct bpf_jit *jit, u32 rs, u32 re, u32 stack_depth) 417 { 418 u32 off = STK_OFF_R6 + (rs - 6) * 8; 419 420 if (jit->seen & SEEN_STACK) 421 off += STK_OFF + stack_depth; 422 423 if (rs == re) 424 /* lg %rs,off(%r15) */ 425 _EMIT6(0xe300f000 | rs << 20 | off, 0x0004); 426 else 427 /* lmg %rs,%re,off(%r15) */ 428 _EMIT6_DISP(0xeb00f000 | rs << 20 | re << 16, 0x0004, off); 429 } 430 431 /* 432 * Return first seen register (from start) 433 */ 434 static int get_start(struct bpf_jit *jit, int start) 435 { 436 int i; 437 438 for (i = start; i <= 15; i++) { 439 if (jit->seen_reg[i]) 440 return i; 441 } 442 return 0; 443 } 444 445 /* 446 * Return last seen register (from start) (gap >= 2) 447 */ 448 static int get_end(struct bpf_jit *jit, int start) 449 { 450 int i; 451 452 for (i = start; i < 15; i++) { 453 if (!jit->seen_reg[i] && !jit->seen_reg[i + 1]) 454 return i - 1; 455 } 456 return jit->seen_reg[15] ? 15 : 14; 457 } 458 459 #define REGS_SAVE 1 460 #define REGS_RESTORE 0 461 /* 462 * Save and restore clobbered registers (6-15) on stack. 463 * We save/restore registers in chunks with gap >= 2 registers. 464 */ 465 static void save_restore_regs(struct bpf_jit *jit, int op, u32 stack_depth) 466 { 467 const int last = 15, save_restore_size = 6; 468 int re = 6, rs; 469 470 if (is_first_pass(jit)) { 471 /* 472 * We don't know yet which registers are used. Reserve space 473 * conservatively. 474 */ 475 jit->prg += (last - re + 1) * save_restore_size; 476 return; 477 } 478 479 do { 480 rs = get_start(jit, re); 481 if (!rs) 482 break; 483 re = get_end(jit, rs + 1); 484 if (op == REGS_SAVE) 485 save_regs(jit, rs, re); 486 else 487 restore_regs(jit, rs, re, stack_depth); 488 re++; 489 } while (re <= last); 490 } 491 492 static void bpf_skip(struct bpf_jit *jit, int size) 493 { 494 if (size >= 6 && !is_valid_rel(size)) { 495 /* brcl 0xf,size */ 496 EMIT6_PCREL_RIL(0xc0f4000000, size); 497 size -= 6; 498 } else if (size >= 4 && is_valid_rel(size)) { 499 /* brc 0xf,size */ 500 EMIT4_PCREL(0xa7f40000, size); 501 size -= 4; 502 } 503 while (size >= 2) { 504 /* bcr 0,%0 */ 505 _EMIT2(0x0700); 506 size -= 2; 507 } 508 } 509 510 /* 511 * Emit function prologue 512 * 513 * Save registers and create stack frame if necessary. 514 * See stack frame layout desription in "bpf_jit.h"! 515 */ 516 static void bpf_jit_prologue(struct bpf_jit *jit, u32 stack_depth) 517 { 518 if (jit->seen & SEEN_TAIL_CALL) { 519 /* xc STK_OFF_TCCNT(4,%r15),STK_OFF_TCCNT(%r15) */ 520 _EMIT6(0xd703f000 | STK_OFF_TCCNT, 0xf000 | STK_OFF_TCCNT); 521 } else { 522 /* 523 * There are no tail calls. Insert nops in order to have 524 * tail_call_start at a predictable offset. 525 */ 526 bpf_skip(jit, 6); 527 } 528 /* Tail calls have to skip above initialization */ 529 jit->tail_call_start = jit->prg; 530 /* Save registers */ 531 save_restore_regs(jit, REGS_SAVE, stack_depth); 532 /* Setup literal pool */ 533 if (is_first_pass(jit) || (jit->seen & SEEN_LITERAL)) { 534 if (!is_first_pass(jit) && 535 is_valid_ldisp(jit->size - (jit->prg + 2))) { 536 /* basr %l,0 */ 537 EMIT2(0x0d00, REG_L, REG_0); 538 jit->base_ip = jit->prg; 539 } else { 540 /* larl %l,lit32_start */ 541 EMIT6_PCREL_RILB(0xc0000000, REG_L, jit->lit32_start); 542 jit->base_ip = jit->lit32_start; 543 } 544 } 545 /* Setup stack and backchain */ 546 if (is_first_pass(jit) || (jit->seen & SEEN_STACK)) { 547 if (is_first_pass(jit) || (jit->seen & SEEN_FUNC)) 548 /* lgr %w1,%r15 (backchain) */ 549 EMIT4(0xb9040000, REG_W1, REG_15); 550 /* la %bfp,STK_160_UNUSED(%r15) (BPF frame pointer) */ 551 EMIT4_DISP(0x41000000, BPF_REG_FP, REG_15, STK_160_UNUSED); 552 /* aghi %r15,-STK_OFF */ 553 EMIT4_IMM(0xa70b0000, REG_15, -(STK_OFF + stack_depth)); 554 if (is_first_pass(jit) || (jit->seen & SEEN_FUNC)) 555 /* stg %w1,152(%r15) (backchain) */ 556 EMIT6_DISP_LH(0xe3000000, 0x0024, REG_W1, REG_0, 557 REG_15, 152); 558 } 559 } 560 561 /* 562 * Function epilogue 563 */ 564 static void bpf_jit_epilogue(struct bpf_jit *jit, u32 stack_depth) 565 { 566 jit->exit_ip = jit->prg; 567 /* Load exit code: lgr %r2,%b0 */ 568 EMIT4(0xb9040000, REG_2, BPF_REG_0); 569 /* Restore registers */ 570 save_restore_regs(jit, REGS_RESTORE, stack_depth); 571 if (__is_defined(CC_USING_EXPOLINE) && !nospec_disable) { 572 jit->r14_thunk_ip = jit->prg; 573 /* Generate __s390_indirect_jump_r14 thunk */ 574 if (test_facility(35)) { 575 /* exrl %r0,.+10 */ 576 EMIT6_PCREL_RIL(0xc6000000, jit->prg + 10); 577 } else { 578 /* larl %r1,.+14 */ 579 EMIT6_PCREL_RILB(0xc0000000, REG_1, jit->prg + 14); 580 /* ex 0,0(%r1) */ 581 EMIT4_DISP(0x44000000, REG_0, REG_1, 0); 582 } 583 /* j . */ 584 EMIT4_PCREL(0xa7f40000, 0); 585 } 586 /* br %r14 */ 587 _EMIT2(0x07fe); 588 589 if (__is_defined(CC_USING_EXPOLINE) && !nospec_disable && 590 (is_first_pass(jit) || (jit->seen & SEEN_FUNC))) { 591 jit->r1_thunk_ip = jit->prg; 592 /* Generate __s390_indirect_jump_r1 thunk */ 593 if (test_facility(35)) { 594 /* exrl %r0,.+10 */ 595 EMIT6_PCREL_RIL(0xc6000000, jit->prg + 10); 596 /* j . */ 597 EMIT4_PCREL(0xa7f40000, 0); 598 /* br %r1 */ 599 _EMIT2(0x07f1); 600 } else { 601 /* ex 0,S390_lowcore.br_r1_tampoline */ 602 EMIT4_DISP(0x44000000, REG_0, REG_0, 603 offsetof(struct lowcore, br_r1_trampoline)); 604 /* j . */ 605 EMIT4_PCREL(0xa7f40000, 0); 606 } 607 } 608 } 609 610 /* 611 * Compile one eBPF instruction into s390x code 612 * 613 * NOTE: Use noinline because for gcov (-fprofile-arcs) gcc allocates a lot of 614 * stack space for the large switch statement. 615 */ 616 static noinline int bpf_jit_insn(struct bpf_jit *jit, struct bpf_prog *fp, 617 int i, bool extra_pass, u32 stack_depth) 618 { 619 struct bpf_insn *insn = &fp->insnsi[i]; 620 u32 dst_reg = insn->dst_reg; 621 u32 src_reg = insn->src_reg; 622 int last, insn_count = 1; 623 u32 *addrs = jit->addrs; 624 s32 imm = insn->imm; 625 s16 off = insn->off; 626 unsigned int mask; 627 628 switch (insn->code) { 629 /* 630 * BPF_MOV 631 */ 632 case BPF_ALU | BPF_MOV | BPF_X: /* dst = (u32) src */ 633 /* llgfr %dst,%src */ 634 EMIT4(0xb9160000, dst_reg, src_reg); 635 if (insn_is_zext(&insn[1])) 636 insn_count = 2; 637 break; 638 case BPF_ALU64 | BPF_MOV | BPF_X: /* dst = src */ 639 /* lgr %dst,%src */ 640 EMIT4(0xb9040000, dst_reg, src_reg); 641 break; 642 case BPF_ALU | BPF_MOV | BPF_K: /* dst = (u32) imm */ 643 /* llilf %dst,imm */ 644 EMIT6_IMM(0xc00f0000, dst_reg, imm); 645 if (insn_is_zext(&insn[1])) 646 insn_count = 2; 647 break; 648 case BPF_ALU64 | BPF_MOV | BPF_K: /* dst = imm */ 649 /* lgfi %dst,imm */ 650 EMIT6_IMM(0xc0010000, dst_reg, imm); 651 break; 652 /* 653 * BPF_LD 64 654 */ 655 case BPF_LD | BPF_IMM | BPF_DW: /* dst = (u64) imm */ 656 { 657 /* 16 byte instruction that uses two 'struct bpf_insn' */ 658 u64 imm64; 659 660 imm64 = (u64)(u32) insn[0].imm | ((u64)(u32) insn[1].imm) << 32; 661 /* lgrl %dst,imm */ 662 EMIT6_PCREL_RILB(0xc4080000, dst_reg, _EMIT_CONST_U64(imm64)); 663 insn_count = 2; 664 break; 665 } 666 /* 667 * BPF_ADD 668 */ 669 case BPF_ALU | BPF_ADD | BPF_X: /* dst = (u32) dst + (u32) src */ 670 /* ar %dst,%src */ 671 EMIT2(0x1a00, dst_reg, src_reg); 672 EMIT_ZERO(dst_reg); 673 break; 674 case BPF_ALU64 | BPF_ADD | BPF_X: /* dst = dst + src */ 675 /* agr %dst,%src */ 676 EMIT4(0xb9080000, dst_reg, src_reg); 677 break; 678 case BPF_ALU | BPF_ADD | BPF_K: /* dst = (u32) dst + (u32) imm */ 679 if (!imm) 680 break; 681 /* alfi %dst,imm */ 682 EMIT6_IMM(0xc20b0000, dst_reg, imm); 683 EMIT_ZERO(dst_reg); 684 break; 685 case BPF_ALU64 | BPF_ADD | BPF_K: /* dst = dst + imm */ 686 if (!imm) 687 break; 688 /* agfi %dst,imm */ 689 EMIT6_IMM(0xc2080000, dst_reg, imm); 690 break; 691 /* 692 * BPF_SUB 693 */ 694 case BPF_ALU | BPF_SUB | BPF_X: /* dst = (u32) dst - (u32) src */ 695 /* sr %dst,%src */ 696 EMIT2(0x1b00, dst_reg, src_reg); 697 EMIT_ZERO(dst_reg); 698 break; 699 case BPF_ALU64 | BPF_SUB | BPF_X: /* dst = dst - src */ 700 /* sgr %dst,%src */ 701 EMIT4(0xb9090000, dst_reg, src_reg); 702 break; 703 case BPF_ALU | BPF_SUB | BPF_K: /* dst = (u32) dst - (u32) imm */ 704 if (!imm) 705 break; 706 /* alfi %dst,-imm */ 707 EMIT6_IMM(0xc20b0000, dst_reg, -imm); 708 EMIT_ZERO(dst_reg); 709 break; 710 case BPF_ALU64 | BPF_SUB | BPF_K: /* dst = dst - imm */ 711 if (!imm) 712 break; 713 /* agfi %dst,-imm */ 714 EMIT6_IMM(0xc2080000, dst_reg, -imm); 715 break; 716 /* 717 * BPF_MUL 718 */ 719 case BPF_ALU | BPF_MUL | BPF_X: /* dst = (u32) dst * (u32) src */ 720 /* msr %dst,%src */ 721 EMIT4(0xb2520000, dst_reg, src_reg); 722 EMIT_ZERO(dst_reg); 723 break; 724 case BPF_ALU64 | BPF_MUL | BPF_X: /* dst = dst * src */ 725 /* msgr %dst,%src */ 726 EMIT4(0xb90c0000, dst_reg, src_reg); 727 break; 728 case BPF_ALU | BPF_MUL | BPF_K: /* dst = (u32) dst * (u32) imm */ 729 if (imm == 1) 730 break; 731 /* msfi %r5,imm */ 732 EMIT6_IMM(0xc2010000, dst_reg, imm); 733 EMIT_ZERO(dst_reg); 734 break; 735 case BPF_ALU64 | BPF_MUL | BPF_K: /* dst = dst * imm */ 736 if (imm == 1) 737 break; 738 /* msgfi %dst,imm */ 739 EMIT6_IMM(0xc2000000, dst_reg, imm); 740 break; 741 /* 742 * BPF_DIV / BPF_MOD 743 */ 744 case BPF_ALU | BPF_DIV | BPF_X: /* dst = (u32) dst / (u32) src */ 745 case BPF_ALU | BPF_MOD | BPF_X: /* dst = (u32) dst % (u32) src */ 746 { 747 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0; 748 749 /* lhi %w0,0 */ 750 EMIT4_IMM(0xa7080000, REG_W0, 0); 751 /* lr %w1,%dst */ 752 EMIT2(0x1800, REG_W1, dst_reg); 753 /* dlr %w0,%src */ 754 EMIT4(0xb9970000, REG_W0, src_reg); 755 /* llgfr %dst,%rc */ 756 EMIT4(0xb9160000, dst_reg, rc_reg); 757 if (insn_is_zext(&insn[1])) 758 insn_count = 2; 759 break; 760 } 761 case BPF_ALU64 | BPF_DIV | BPF_X: /* dst = dst / src */ 762 case BPF_ALU64 | BPF_MOD | BPF_X: /* dst = dst % src */ 763 { 764 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0; 765 766 /* lghi %w0,0 */ 767 EMIT4_IMM(0xa7090000, REG_W0, 0); 768 /* lgr %w1,%dst */ 769 EMIT4(0xb9040000, REG_W1, dst_reg); 770 /* dlgr %w0,%dst */ 771 EMIT4(0xb9870000, REG_W0, src_reg); 772 /* lgr %dst,%rc */ 773 EMIT4(0xb9040000, dst_reg, rc_reg); 774 break; 775 } 776 case BPF_ALU | BPF_DIV | BPF_K: /* dst = (u32) dst / (u32) imm */ 777 case BPF_ALU | BPF_MOD | BPF_K: /* dst = (u32) dst % (u32) imm */ 778 { 779 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0; 780 781 if (imm == 1) { 782 if (BPF_OP(insn->code) == BPF_MOD) 783 /* lhgi %dst,0 */ 784 EMIT4_IMM(0xa7090000, dst_reg, 0); 785 break; 786 } 787 /* lhi %w0,0 */ 788 EMIT4_IMM(0xa7080000, REG_W0, 0); 789 /* lr %w1,%dst */ 790 EMIT2(0x1800, REG_W1, dst_reg); 791 if (!is_first_pass(jit) && can_use_ldisp_for_lit32(jit)) { 792 /* dl %w0,<d(imm)>(%l) */ 793 EMIT6_DISP_LH(0xe3000000, 0x0097, REG_W0, REG_0, REG_L, 794 EMIT_CONST_U32(imm)); 795 } else { 796 /* lgfrl %dst,imm */ 797 EMIT6_PCREL_RILB(0xc40c0000, dst_reg, 798 _EMIT_CONST_U32(imm)); 799 jit->seen |= SEEN_LITERAL; 800 /* dlr %w0,%dst */ 801 EMIT4(0xb9970000, REG_W0, dst_reg); 802 } 803 /* llgfr %dst,%rc */ 804 EMIT4(0xb9160000, dst_reg, rc_reg); 805 if (insn_is_zext(&insn[1])) 806 insn_count = 2; 807 break; 808 } 809 case BPF_ALU64 | BPF_DIV | BPF_K: /* dst = dst / imm */ 810 case BPF_ALU64 | BPF_MOD | BPF_K: /* dst = dst % imm */ 811 { 812 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0; 813 814 if (imm == 1) { 815 if (BPF_OP(insn->code) == BPF_MOD) 816 /* lhgi %dst,0 */ 817 EMIT4_IMM(0xa7090000, dst_reg, 0); 818 break; 819 } 820 /* lghi %w0,0 */ 821 EMIT4_IMM(0xa7090000, REG_W0, 0); 822 /* lgr %w1,%dst */ 823 EMIT4(0xb9040000, REG_W1, dst_reg); 824 if (!is_first_pass(jit) && can_use_ldisp_for_lit64(jit)) { 825 /* dlg %w0,<d(imm)>(%l) */ 826 EMIT6_DISP_LH(0xe3000000, 0x0087, REG_W0, REG_0, REG_L, 827 EMIT_CONST_U64(imm)); 828 } else { 829 /* lgrl %dst,imm */ 830 EMIT6_PCREL_RILB(0xc4080000, dst_reg, 831 _EMIT_CONST_U64(imm)); 832 jit->seen |= SEEN_LITERAL; 833 /* dlgr %w0,%dst */ 834 EMIT4(0xb9870000, REG_W0, dst_reg); 835 } 836 /* lgr %dst,%rc */ 837 EMIT4(0xb9040000, dst_reg, rc_reg); 838 break; 839 } 840 /* 841 * BPF_AND 842 */ 843 case BPF_ALU | BPF_AND | BPF_X: /* dst = (u32) dst & (u32) src */ 844 /* nr %dst,%src */ 845 EMIT2(0x1400, dst_reg, src_reg); 846 EMIT_ZERO(dst_reg); 847 break; 848 case BPF_ALU64 | BPF_AND | BPF_X: /* dst = dst & src */ 849 /* ngr %dst,%src */ 850 EMIT4(0xb9800000, dst_reg, src_reg); 851 break; 852 case BPF_ALU | BPF_AND | BPF_K: /* dst = (u32) dst & (u32) imm */ 853 /* nilf %dst,imm */ 854 EMIT6_IMM(0xc00b0000, dst_reg, imm); 855 EMIT_ZERO(dst_reg); 856 break; 857 case BPF_ALU64 | BPF_AND | BPF_K: /* dst = dst & imm */ 858 if (!is_first_pass(jit) && can_use_ldisp_for_lit64(jit)) { 859 /* ng %dst,<d(imm)>(%l) */ 860 EMIT6_DISP_LH(0xe3000000, 0x0080, 861 dst_reg, REG_0, REG_L, 862 EMIT_CONST_U64(imm)); 863 } else { 864 /* lgrl %w0,imm */ 865 EMIT6_PCREL_RILB(0xc4080000, REG_W0, 866 _EMIT_CONST_U64(imm)); 867 jit->seen |= SEEN_LITERAL; 868 /* ngr %dst,%w0 */ 869 EMIT4(0xb9800000, dst_reg, REG_W0); 870 } 871 break; 872 /* 873 * BPF_OR 874 */ 875 case BPF_ALU | BPF_OR | BPF_X: /* dst = (u32) dst | (u32) src */ 876 /* or %dst,%src */ 877 EMIT2(0x1600, dst_reg, src_reg); 878 EMIT_ZERO(dst_reg); 879 break; 880 case BPF_ALU64 | BPF_OR | BPF_X: /* dst = dst | src */ 881 /* ogr %dst,%src */ 882 EMIT4(0xb9810000, dst_reg, src_reg); 883 break; 884 case BPF_ALU | BPF_OR | BPF_K: /* dst = (u32) dst | (u32) imm */ 885 /* oilf %dst,imm */ 886 EMIT6_IMM(0xc00d0000, dst_reg, imm); 887 EMIT_ZERO(dst_reg); 888 break; 889 case BPF_ALU64 | BPF_OR | BPF_K: /* dst = dst | imm */ 890 if (!is_first_pass(jit) && can_use_ldisp_for_lit64(jit)) { 891 /* og %dst,<d(imm)>(%l) */ 892 EMIT6_DISP_LH(0xe3000000, 0x0081, 893 dst_reg, REG_0, REG_L, 894 EMIT_CONST_U64(imm)); 895 } else { 896 /* lgrl %w0,imm */ 897 EMIT6_PCREL_RILB(0xc4080000, REG_W0, 898 _EMIT_CONST_U64(imm)); 899 jit->seen |= SEEN_LITERAL; 900 /* ogr %dst,%w0 */ 901 EMIT4(0xb9810000, dst_reg, REG_W0); 902 } 903 break; 904 /* 905 * BPF_XOR 906 */ 907 case BPF_ALU | BPF_XOR | BPF_X: /* dst = (u32) dst ^ (u32) src */ 908 /* xr %dst,%src */ 909 EMIT2(0x1700, dst_reg, src_reg); 910 EMIT_ZERO(dst_reg); 911 break; 912 case BPF_ALU64 | BPF_XOR | BPF_X: /* dst = dst ^ src */ 913 /* xgr %dst,%src */ 914 EMIT4(0xb9820000, dst_reg, src_reg); 915 break; 916 case BPF_ALU | BPF_XOR | BPF_K: /* dst = (u32) dst ^ (u32) imm */ 917 if (!imm) 918 break; 919 /* xilf %dst,imm */ 920 EMIT6_IMM(0xc0070000, dst_reg, imm); 921 EMIT_ZERO(dst_reg); 922 break; 923 case BPF_ALU64 | BPF_XOR | BPF_K: /* dst = dst ^ imm */ 924 if (!is_first_pass(jit) && can_use_ldisp_for_lit64(jit)) { 925 /* xg %dst,<d(imm)>(%l) */ 926 EMIT6_DISP_LH(0xe3000000, 0x0082, 927 dst_reg, REG_0, REG_L, 928 EMIT_CONST_U64(imm)); 929 } else { 930 /* lgrl %w0,imm */ 931 EMIT6_PCREL_RILB(0xc4080000, REG_W0, 932 _EMIT_CONST_U64(imm)); 933 jit->seen |= SEEN_LITERAL; 934 /* xgr %dst,%w0 */ 935 EMIT4(0xb9820000, dst_reg, REG_W0); 936 } 937 break; 938 /* 939 * BPF_LSH 940 */ 941 case BPF_ALU | BPF_LSH | BPF_X: /* dst = (u32) dst << (u32) src */ 942 /* sll %dst,0(%src) */ 943 EMIT4_DISP(0x89000000, dst_reg, src_reg, 0); 944 EMIT_ZERO(dst_reg); 945 break; 946 case BPF_ALU64 | BPF_LSH | BPF_X: /* dst = dst << src */ 947 /* sllg %dst,%dst,0(%src) */ 948 EMIT6_DISP_LH(0xeb000000, 0x000d, dst_reg, dst_reg, src_reg, 0); 949 break; 950 case BPF_ALU | BPF_LSH | BPF_K: /* dst = (u32) dst << (u32) imm */ 951 if (imm == 0) 952 break; 953 /* sll %dst,imm(%r0) */ 954 EMIT4_DISP(0x89000000, dst_reg, REG_0, imm); 955 EMIT_ZERO(dst_reg); 956 break; 957 case BPF_ALU64 | BPF_LSH | BPF_K: /* dst = dst << imm */ 958 if (imm == 0) 959 break; 960 /* sllg %dst,%dst,imm(%r0) */ 961 EMIT6_DISP_LH(0xeb000000, 0x000d, dst_reg, dst_reg, REG_0, imm); 962 break; 963 /* 964 * BPF_RSH 965 */ 966 case BPF_ALU | BPF_RSH | BPF_X: /* dst = (u32) dst >> (u32) src */ 967 /* srl %dst,0(%src) */ 968 EMIT4_DISP(0x88000000, dst_reg, src_reg, 0); 969 EMIT_ZERO(dst_reg); 970 break; 971 case BPF_ALU64 | BPF_RSH | BPF_X: /* dst = dst >> src */ 972 /* srlg %dst,%dst,0(%src) */ 973 EMIT6_DISP_LH(0xeb000000, 0x000c, dst_reg, dst_reg, src_reg, 0); 974 break; 975 case BPF_ALU | BPF_RSH | BPF_K: /* dst = (u32) dst >> (u32) imm */ 976 if (imm == 0) 977 break; 978 /* srl %dst,imm(%r0) */ 979 EMIT4_DISP(0x88000000, dst_reg, REG_0, imm); 980 EMIT_ZERO(dst_reg); 981 break; 982 case BPF_ALU64 | BPF_RSH | BPF_K: /* dst = dst >> imm */ 983 if (imm == 0) 984 break; 985 /* srlg %dst,%dst,imm(%r0) */ 986 EMIT6_DISP_LH(0xeb000000, 0x000c, dst_reg, dst_reg, REG_0, imm); 987 break; 988 /* 989 * BPF_ARSH 990 */ 991 case BPF_ALU | BPF_ARSH | BPF_X: /* ((s32) dst) >>= src */ 992 /* sra %dst,%dst,0(%src) */ 993 EMIT4_DISP(0x8a000000, dst_reg, src_reg, 0); 994 EMIT_ZERO(dst_reg); 995 break; 996 case BPF_ALU64 | BPF_ARSH | BPF_X: /* ((s64) dst) >>= src */ 997 /* srag %dst,%dst,0(%src) */ 998 EMIT6_DISP_LH(0xeb000000, 0x000a, dst_reg, dst_reg, src_reg, 0); 999 break; 1000 case BPF_ALU | BPF_ARSH | BPF_K: /* ((s32) dst >> imm */ 1001 if (imm == 0) 1002 break; 1003 /* sra %dst,imm(%r0) */ 1004 EMIT4_DISP(0x8a000000, dst_reg, REG_0, imm); 1005 EMIT_ZERO(dst_reg); 1006 break; 1007 case BPF_ALU64 | BPF_ARSH | BPF_K: /* ((s64) dst) >>= imm */ 1008 if (imm == 0) 1009 break; 1010 /* srag %dst,%dst,imm(%r0) */ 1011 EMIT6_DISP_LH(0xeb000000, 0x000a, dst_reg, dst_reg, REG_0, imm); 1012 break; 1013 /* 1014 * BPF_NEG 1015 */ 1016 case BPF_ALU | BPF_NEG: /* dst = (u32) -dst */ 1017 /* lcr %dst,%dst */ 1018 EMIT2(0x1300, dst_reg, dst_reg); 1019 EMIT_ZERO(dst_reg); 1020 break; 1021 case BPF_ALU64 | BPF_NEG: /* dst = -dst */ 1022 /* lcgr %dst,%dst */ 1023 EMIT4(0xb9030000, dst_reg, dst_reg); 1024 break; 1025 /* 1026 * BPF_FROM_BE/LE 1027 */ 1028 case BPF_ALU | BPF_END | BPF_FROM_BE: 1029 /* s390 is big endian, therefore only clear high order bytes */ 1030 switch (imm) { 1031 case 16: /* dst = (u16) cpu_to_be16(dst) */ 1032 /* llghr %dst,%dst */ 1033 EMIT4(0xb9850000, dst_reg, dst_reg); 1034 if (insn_is_zext(&insn[1])) 1035 insn_count = 2; 1036 break; 1037 case 32: /* dst = (u32) cpu_to_be32(dst) */ 1038 if (!fp->aux->verifier_zext) 1039 /* llgfr %dst,%dst */ 1040 EMIT4(0xb9160000, dst_reg, dst_reg); 1041 break; 1042 case 64: /* dst = (u64) cpu_to_be64(dst) */ 1043 break; 1044 } 1045 break; 1046 case BPF_ALU | BPF_END | BPF_FROM_LE: 1047 switch (imm) { 1048 case 16: /* dst = (u16) cpu_to_le16(dst) */ 1049 /* lrvr %dst,%dst */ 1050 EMIT4(0xb91f0000, dst_reg, dst_reg); 1051 /* srl %dst,16(%r0) */ 1052 EMIT4_DISP(0x88000000, dst_reg, REG_0, 16); 1053 /* llghr %dst,%dst */ 1054 EMIT4(0xb9850000, dst_reg, dst_reg); 1055 if (insn_is_zext(&insn[1])) 1056 insn_count = 2; 1057 break; 1058 case 32: /* dst = (u32) cpu_to_le32(dst) */ 1059 /* lrvr %dst,%dst */ 1060 EMIT4(0xb91f0000, dst_reg, dst_reg); 1061 if (!fp->aux->verifier_zext) 1062 /* llgfr %dst,%dst */ 1063 EMIT4(0xb9160000, dst_reg, dst_reg); 1064 break; 1065 case 64: /* dst = (u64) cpu_to_le64(dst) */ 1066 /* lrvgr %dst,%dst */ 1067 EMIT4(0xb90f0000, dst_reg, dst_reg); 1068 break; 1069 } 1070 break; 1071 /* 1072 * BPF_ST(X) 1073 */ 1074 case BPF_STX | BPF_MEM | BPF_B: /* *(u8 *)(dst + off) = src_reg */ 1075 /* stcy %src,off(%dst) */ 1076 EMIT6_DISP_LH(0xe3000000, 0x0072, src_reg, dst_reg, REG_0, off); 1077 jit->seen |= SEEN_MEM; 1078 break; 1079 case BPF_STX | BPF_MEM | BPF_H: /* (u16 *)(dst + off) = src */ 1080 /* sthy %src,off(%dst) */ 1081 EMIT6_DISP_LH(0xe3000000, 0x0070, src_reg, dst_reg, REG_0, off); 1082 jit->seen |= SEEN_MEM; 1083 break; 1084 case BPF_STX | BPF_MEM | BPF_W: /* *(u32 *)(dst + off) = src */ 1085 /* sty %src,off(%dst) */ 1086 EMIT6_DISP_LH(0xe3000000, 0x0050, src_reg, dst_reg, REG_0, off); 1087 jit->seen |= SEEN_MEM; 1088 break; 1089 case BPF_STX | BPF_MEM | BPF_DW: /* (u64 *)(dst + off) = src */ 1090 /* stg %src,off(%dst) */ 1091 EMIT6_DISP_LH(0xe3000000, 0x0024, src_reg, dst_reg, REG_0, off); 1092 jit->seen |= SEEN_MEM; 1093 break; 1094 case BPF_ST | BPF_MEM | BPF_B: /* *(u8 *)(dst + off) = imm */ 1095 /* lhi %w0,imm */ 1096 EMIT4_IMM(0xa7080000, REG_W0, (u8) imm); 1097 /* stcy %w0,off(dst) */ 1098 EMIT6_DISP_LH(0xe3000000, 0x0072, REG_W0, dst_reg, REG_0, off); 1099 jit->seen |= SEEN_MEM; 1100 break; 1101 case BPF_ST | BPF_MEM | BPF_H: /* (u16 *)(dst + off) = imm */ 1102 /* lhi %w0,imm */ 1103 EMIT4_IMM(0xa7080000, REG_W0, (u16) imm); 1104 /* sthy %w0,off(dst) */ 1105 EMIT6_DISP_LH(0xe3000000, 0x0070, REG_W0, dst_reg, REG_0, off); 1106 jit->seen |= SEEN_MEM; 1107 break; 1108 case BPF_ST | BPF_MEM | BPF_W: /* *(u32 *)(dst + off) = imm */ 1109 /* llilf %w0,imm */ 1110 EMIT6_IMM(0xc00f0000, REG_W0, (u32) imm); 1111 /* sty %w0,off(%dst) */ 1112 EMIT6_DISP_LH(0xe3000000, 0x0050, REG_W0, dst_reg, REG_0, off); 1113 jit->seen |= SEEN_MEM; 1114 break; 1115 case BPF_ST | BPF_MEM | BPF_DW: /* *(u64 *)(dst + off) = imm */ 1116 /* lgfi %w0,imm */ 1117 EMIT6_IMM(0xc0010000, REG_W0, imm); 1118 /* stg %w0,off(%dst) */ 1119 EMIT6_DISP_LH(0xe3000000, 0x0024, REG_W0, dst_reg, REG_0, off); 1120 jit->seen |= SEEN_MEM; 1121 break; 1122 /* 1123 * BPF_STX XADD (atomic_add) 1124 */ 1125 case BPF_STX | BPF_XADD | BPF_W: /* *(u32 *)(dst + off) += src */ 1126 /* laal %w0,%src,off(%dst) */ 1127 EMIT6_DISP_LH(0xeb000000, 0x00fa, REG_W0, src_reg, 1128 dst_reg, off); 1129 jit->seen |= SEEN_MEM; 1130 break; 1131 case BPF_STX | BPF_XADD | BPF_DW: /* *(u64 *)(dst + off) += src */ 1132 /* laalg %w0,%src,off(%dst) */ 1133 EMIT6_DISP_LH(0xeb000000, 0x00ea, REG_W0, src_reg, 1134 dst_reg, off); 1135 jit->seen |= SEEN_MEM; 1136 break; 1137 /* 1138 * BPF_LDX 1139 */ 1140 case BPF_LDX | BPF_MEM | BPF_B: /* dst = *(u8 *)(ul) (src + off) */ 1141 /* llgc %dst,0(off,%src) */ 1142 EMIT6_DISP_LH(0xe3000000, 0x0090, dst_reg, src_reg, REG_0, off); 1143 jit->seen |= SEEN_MEM; 1144 if (insn_is_zext(&insn[1])) 1145 insn_count = 2; 1146 break; 1147 case BPF_LDX | BPF_MEM | BPF_H: /* dst = *(u16 *)(ul) (src + off) */ 1148 /* llgh %dst,0(off,%src) */ 1149 EMIT6_DISP_LH(0xe3000000, 0x0091, dst_reg, src_reg, REG_0, off); 1150 jit->seen |= SEEN_MEM; 1151 if (insn_is_zext(&insn[1])) 1152 insn_count = 2; 1153 break; 1154 case BPF_LDX | BPF_MEM | BPF_W: /* dst = *(u32 *)(ul) (src + off) */ 1155 /* llgf %dst,off(%src) */ 1156 jit->seen |= SEEN_MEM; 1157 EMIT6_DISP_LH(0xe3000000, 0x0016, dst_reg, src_reg, REG_0, off); 1158 if (insn_is_zext(&insn[1])) 1159 insn_count = 2; 1160 break; 1161 case BPF_LDX | BPF_MEM | BPF_DW: /* dst = *(u64 *)(ul) (src + off) */ 1162 /* lg %dst,0(off,%src) */ 1163 jit->seen |= SEEN_MEM; 1164 EMIT6_DISP_LH(0xe3000000, 0x0004, dst_reg, src_reg, REG_0, off); 1165 break; 1166 /* 1167 * BPF_JMP / CALL 1168 */ 1169 case BPF_JMP | BPF_CALL: 1170 { 1171 u64 func; 1172 bool func_addr_fixed; 1173 int ret; 1174 1175 ret = bpf_jit_get_func_addr(fp, insn, extra_pass, 1176 &func, &func_addr_fixed); 1177 if (ret < 0) 1178 return -1; 1179 1180 REG_SET_SEEN(BPF_REG_5); 1181 jit->seen |= SEEN_FUNC; 1182 /* lgrl %w1,func */ 1183 EMIT6_PCREL_RILB(0xc4080000, REG_W1, _EMIT_CONST_U64(func)); 1184 if (__is_defined(CC_USING_EXPOLINE) && !nospec_disable) { 1185 /* brasl %r14,__s390_indirect_jump_r1 */ 1186 EMIT6_PCREL_RILB(0xc0050000, REG_14, jit->r1_thunk_ip); 1187 } else { 1188 /* basr %r14,%w1 */ 1189 EMIT2(0x0d00, REG_14, REG_W1); 1190 } 1191 /* lgr %b0,%r2: load return value into %b0 */ 1192 EMIT4(0xb9040000, BPF_REG_0, REG_2); 1193 break; 1194 } 1195 case BPF_JMP | BPF_TAIL_CALL: 1196 /* 1197 * Implicit input: 1198 * B1: pointer to ctx 1199 * B2: pointer to bpf_array 1200 * B3: index in bpf_array 1201 */ 1202 jit->seen |= SEEN_TAIL_CALL; 1203 1204 /* 1205 * if (index >= array->map.max_entries) 1206 * goto out; 1207 */ 1208 1209 /* llgf %w1,map.max_entries(%b2) */ 1210 EMIT6_DISP_LH(0xe3000000, 0x0016, REG_W1, REG_0, BPF_REG_2, 1211 offsetof(struct bpf_array, map.max_entries)); 1212 /* if ((u32)%b3 >= (u32)%w1) goto out; */ 1213 if (!is_first_pass(jit) && can_use_rel(jit, jit->labels[0])) { 1214 /* clrj %b3,%w1,0xa,label0 */ 1215 EMIT6_PCREL_LABEL(0xec000000, 0x0077, BPF_REG_3, 1216 REG_W1, 0, 0xa); 1217 } else { 1218 /* clr %b3,%w1 */ 1219 EMIT2(0x1500, BPF_REG_3, REG_W1); 1220 /* brcl 0xa,label0 */ 1221 EMIT6_PCREL_RILC(0xc0040000, 0xa, jit->labels[0]); 1222 } 1223 1224 /* 1225 * if (tail_call_cnt++ > MAX_TAIL_CALL_CNT) 1226 * goto out; 1227 */ 1228 1229 if (jit->seen & SEEN_STACK) 1230 off = STK_OFF_TCCNT + STK_OFF + stack_depth; 1231 else 1232 off = STK_OFF_TCCNT; 1233 /* lhi %w0,1 */ 1234 EMIT4_IMM(0xa7080000, REG_W0, 1); 1235 /* laal %w1,%w0,off(%r15) */ 1236 EMIT6_DISP_LH(0xeb000000, 0x00fa, REG_W1, REG_W0, REG_15, off); 1237 if (!is_first_pass(jit) && can_use_rel(jit, jit->labels[0])) { 1238 /* clij %w1,MAX_TAIL_CALL_CNT,0x2,label0 */ 1239 EMIT6_PCREL_IMM_LABEL(0xec000000, 0x007f, REG_W1, 1240 MAX_TAIL_CALL_CNT, 0, 0x2); 1241 } else { 1242 /* clfi %w1,MAX_TAIL_CALL_CNT */ 1243 EMIT6_IMM(0xc20f0000, REG_W1, MAX_TAIL_CALL_CNT); 1244 /* brcl 0x2,label0 */ 1245 EMIT6_PCREL_RILC(0xc0040000, 0x2, jit->labels[0]); 1246 } 1247 1248 /* 1249 * prog = array->ptrs[index]; 1250 * if (prog == NULL) 1251 * goto out; 1252 */ 1253 1254 /* llgfr %r1,%b3: %r1 = (u32) index */ 1255 EMIT4(0xb9160000, REG_1, BPF_REG_3); 1256 /* sllg %r1,%r1,3: %r1 *= 8 */ 1257 EMIT6_DISP_LH(0xeb000000, 0x000d, REG_1, REG_1, REG_0, 3); 1258 /* ltg %r1,prog(%b2,%r1) */ 1259 EMIT6_DISP_LH(0xe3000000, 0x0002, REG_1, BPF_REG_2, 1260 REG_1, offsetof(struct bpf_array, ptrs)); 1261 if (!is_first_pass(jit) && can_use_rel(jit, jit->labels[0])) { 1262 /* brc 0x8,label0 */ 1263 EMIT4_PCREL_RIC(0xa7040000, 0x8, jit->labels[0]); 1264 } else { 1265 /* brcl 0x8,label0 */ 1266 EMIT6_PCREL_RILC(0xc0040000, 0x8, jit->labels[0]); 1267 } 1268 1269 /* 1270 * Restore registers before calling function 1271 */ 1272 save_restore_regs(jit, REGS_RESTORE, stack_depth); 1273 1274 /* 1275 * goto *(prog->bpf_func + tail_call_start); 1276 */ 1277 1278 /* lg %r1,bpf_func(%r1) */ 1279 EMIT6_DISP_LH(0xe3000000, 0x0004, REG_1, REG_1, REG_0, 1280 offsetof(struct bpf_prog, bpf_func)); 1281 /* bc 0xf,tail_call_start(%r1) */ 1282 _EMIT4(0x47f01000 + jit->tail_call_start); 1283 /* out: */ 1284 jit->labels[0] = jit->prg; 1285 break; 1286 case BPF_JMP | BPF_EXIT: /* return b0 */ 1287 last = (i == fp->len - 1) ? 1 : 0; 1288 if (last) 1289 break; 1290 if (!is_first_pass(jit) && can_use_rel(jit, jit->exit_ip)) 1291 /* brc 0xf, <exit> */ 1292 EMIT4_PCREL_RIC(0xa7040000, 0xf, jit->exit_ip); 1293 else 1294 /* brcl 0xf, <exit> */ 1295 EMIT6_PCREL_RILC(0xc0040000, 0xf, jit->exit_ip); 1296 break; 1297 /* 1298 * Branch relative (number of skipped instructions) to offset on 1299 * condition. 1300 * 1301 * Condition code to mask mapping: 1302 * 1303 * CC | Description | Mask 1304 * ------------------------------ 1305 * 0 | Operands equal | 8 1306 * 1 | First operand low | 4 1307 * 2 | First operand high | 2 1308 * 3 | Unused | 1 1309 * 1310 * For s390x relative branches: ip = ip + off_bytes 1311 * For BPF relative branches: insn = insn + off_insns + 1 1312 * 1313 * For example for s390x with offset 0 we jump to the branch 1314 * instruction itself (loop) and for BPF with offset 0 we 1315 * branch to the instruction behind the branch. 1316 */ 1317 case BPF_JMP | BPF_JA: /* if (true) */ 1318 mask = 0xf000; /* j */ 1319 goto branch_oc; 1320 case BPF_JMP | BPF_JSGT | BPF_K: /* ((s64) dst > (s64) imm) */ 1321 case BPF_JMP32 | BPF_JSGT | BPF_K: /* ((s32) dst > (s32) imm) */ 1322 mask = 0x2000; /* jh */ 1323 goto branch_ks; 1324 case BPF_JMP | BPF_JSLT | BPF_K: /* ((s64) dst < (s64) imm) */ 1325 case BPF_JMP32 | BPF_JSLT | BPF_K: /* ((s32) dst < (s32) imm) */ 1326 mask = 0x4000; /* jl */ 1327 goto branch_ks; 1328 case BPF_JMP | BPF_JSGE | BPF_K: /* ((s64) dst >= (s64) imm) */ 1329 case BPF_JMP32 | BPF_JSGE | BPF_K: /* ((s32) dst >= (s32) imm) */ 1330 mask = 0xa000; /* jhe */ 1331 goto branch_ks; 1332 case BPF_JMP | BPF_JSLE | BPF_K: /* ((s64) dst <= (s64) imm) */ 1333 case BPF_JMP32 | BPF_JSLE | BPF_K: /* ((s32) dst <= (s32) imm) */ 1334 mask = 0xc000; /* jle */ 1335 goto branch_ks; 1336 case BPF_JMP | BPF_JGT | BPF_K: /* (dst_reg > imm) */ 1337 case BPF_JMP32 | BPF_JGT | BPF_K: /* ((u32) dst_reg > (u32) imm) */ 1338 mask = 0x2000; /* jh */ 1339 goto branch_ku; 1340 case BPF_JMP | BPF_JLT | BPF_K: /* (dst_reg < imm) */ 1341 case BPF_JMP32 | BPF_JLT | BPF_K: /* ((u32) dst_reg < (u32) imm) */ 1342 mask = 0x4000; /* jl */ 1343 goto branch_ku; 1344 case BPF_JMP | BPF_JGE | BPF_K: /* (dst_reg >= imm) */ 1345 case BPF_JMP32 | BPF_JGE | BPF_K: /* ((u32) dst_reg >= (u32) imm) */ 1346 mask = 0xa000; /* jhe */ 1347 goto branch_ku; 1348 case BPF_JMP | BPF_JLE | BPF_K: /* (dst_reg <= imm) */ 1349 case BPF_JMP32 | BPF_JLE | BPF_K: /* ((u32) dst_reg <= (u32) imm) */ 1350 mask = 0xc000; /* jle */ 1351 goto branch_ku; 1352 case BPF_JMP | BPF_JNE | BPF_K: /* (dst_reg != imm) */ 1353 case BPF_JMP32 | BPF_JNE | BPF_K: /* ((u32) dst_reg != (u32) imm) */ 1354 mask = 0x7000; /* jne */ 1355 goto branch_ku; 1356 case BPF_JMP | BPF_JEQ | BPF_K: /* (dst_reg == imm) */ 1357 case BPF_JMP32 | BPF_JEQ | BPF_K: /* ((u32) dst_reg == (u32) imm) */ 1358 mask = 0x8000; /* je */ 1359 goto branch_ku; 1360 case BPF_JMP | BPF_JSET | BPF_K: /* (dst_reg & imm) */ 1361 case BPF_JMP32 | BPF_JSET | BPF_K: /* ((u32) dst_reg & (u32) imm) */ 1362 mask = 0x7000; /* jnz */ 1363 if (BPF_CLASS(insn->code) == BPF_JMP32) { 1364 /* llilf %w1,imm (load zero extend imm) */ 1365 EMIT6_IMM(0xc00f0000, REG_W1, imm); 1366 /* nr %w1,%dst */ 1367 EMIT2(0x1400, REG_W1, dst_reg); 1368 } else { 1369 /* lgfi %w1,imm (load sign extend imm) */ 1370 EMIT6_IMM(0xc0010000, REG_W1, imm); 1371 /* ngr %w1,%dst */ 1372 EMIT4(0xb9800000, REG_W1, dst_reg); 1373 } 1374 goto branch_oc; 1375 1376 case BPF_JMP | BPF_JSGT | BPF_X: /* ((s64) dst > (s64) src) */ 1377 case BPF_JMP32 | BPF_JSGT | BPF_X: /* ((s32) dst > (s32) src) */ 1378 mask = 0x2000; /* jh */ 1379 goto branch_xs; 1380 case BPF_JMP | BPF_JSLT | BPF_X: /* ((s64) dst < (s64) src) */ 1381 case BPF_JMP32 | BPF_JSLT | BPF_X: /* ((s32) dst < (s32) src) */ 1382 mask = 0x4000; /* jl */ 1383 goto branch_xs; 1384 case BPF_JMP | BPF_JSGE | BPF_X: /* ((s64) dst >= (s64) src) */ 1385 case BPF_JMP32 | BPF_JSGE | BPF_X: /* ((s32) dst >= (s32) src) */ 1386 mask = 0xa000; /* jhe */ 1387 goto branch_xs; 1388 case BPF_JMP | BPF_JSLE | BPF_X: /* ((s64) dst <= (s64) src) */ 1389 case BPF_JMP32 | BPF_JSLE | BPF_X: /* ((s32) dst <= (s32) src) */ 1390 mask = 0xc000; /* jle */ 1391 goto branch_xs; 1392 case BPF_JMP | BPF_JGT | BPF_X: /* (dst > src) */ 1393 case BPF_JMP32 | BPF_JGT | BPF_X: /* ((u32) dst > (u32) src) */ 1394 mask = 0x2000; /* jh */ 1395 goto branch_xu; 1396 case BPF_JMP | BPF_JLT | BPF_X: /* (dst < src) */ 1397 case BPF_JMP32 | BPF_JLT | BPF_X: /* ((u32) dst < (u32) src) */ 1398 mask = 0x4000; /* jl */ 1399 goto branch_xu; 1400 case BPF_JMP | BPF_JGE | BPF_X: /* (dst >= src) */ 1401 case BPF_JMP32 | BPF_JGE | BPF_X: /* ((u32) dst >= (u32) src) */ 1402 mask = 0xa000; /* jhe */ 1403 goto branch_xu; 1404 case BPF_JMP | BPF_JLE | BPF_X: /* (dst <= src) */ 1405 case BPF_JMP32 | BPF_JLE | BPF_X: /* ((u32) dst <= (u32) src) */ 1406 mask = 0xc000; /* jle */ 1407 goto branch_xu; 1408 case BPF_JMP | BPF_JNE | BPF_X: /* (dst != src) */ 1409 case BPF_JMP32 | BPF_JNE | BPF_X: /* ((u32) dst != (u32) src) */ 1410 mask = 0x7000; /* jne */ 1411 goto branch_xu; 1412 case BPF_JMP | BPF_JEQ | BPF_X: /* (dst == src) */ 1413 case BPF_JMP32 | BPF_JEQ | BPF_X: /* ((u32) dst == (u32) src) */ 1414 mask = 0x8000; /* je */ 1415 goto branch_xu; 1416 case BPF_JMP | BPF_JSET | BPF_X: /* (dst & src) */ 1417 case BPF_JMP32 | BPF_JSET | BPF_X: /* ((u32) dst & (u32) src) */ 1418 { 1419 bool is_jmp32 = BPF_CLASS(insn->code) == BPF_JMP32; 1420 1421 mask = 0x7000; /* jnz */ 1422 /* nrk or ngrk %w1,%dst,%src */ 1423 EMIT4_RRF((is_jmp32 ? 0xb9f40000 : 0xb9e40000), 1424 REG_W1, dst_reg, src_reg); 1425 goto branch_oc; 1426 branch_ks: 1427 is_jmp32 = BPF_CLASS(insn->code) == BPF_JMP32; 1428 /* cfi or cgfi %dst,imm */ 1429 EMIT6_IMM(is_jmp32 ? 0xc20d0000 : 0xc20c0000, 1430 dst_reg, imm); 1431 if (!is_first_pass(jit) && 1432 can_use_rel(jit, addrs[i + off + 1])) { 1433 /* brc mask,off */ 1434 EMIT4_PCREL_RIC(0xa7040000, 1435 mask >> 12, addrs[i + off + 1]); 1436 } else { 1437 /* brcl mask,off */ 1438 EMIT6_PCREL_RILC(0xc0040000, 1439 mask >> 12, addrs[i + off + 1]); 1440 } 1441 break; 1442 branch_ku: 1443 /* lgfi %w1,imm (load sign extend imm) */ 1444 src_reg = REG_1; 1445 EMIT6_IMM(0xc0010000, src_reg, imm); 1446 goto branch_xu; 1447 branch_xs: 1448 is_jmp32 = BPF_CLASS(insn->code) == BPF_JMP32; 1449 if (!is_first_pass(jit) && 1450 can_use_rel(jit, addrs[i + off + 1])) { 1451 /* crj or cgrj %dst,%src,mask,off */ 1452 EMIT6_PCREL(0xec000000, (is_jmp32 ? 0x0076 : 0x0064), 1453 dst_reg, src_reg, i, off, mask); 1454 } else { 1455 /* cr or cgr %dst,%src */ 1456 if (is_jmp32) 1457 EMIT2(0x1900, dst_reg, src_reg); 1458 else 1459 EMIT4(0xb9200000, dst_reg, src_reg); 1460 /* brcl mask,off */ 1461 EMIT6_PCREL_RILC(0xc0040000, 1462 mask >> 12, addrs[i + off + 1]); 1463 } 1464 break; 1465 branch_xu: 1466 is_jmp32 = BPF_CLASS(insn->code) == BPF_JMP32; 1467 if (!is_first_pass(jit) && 1468 can_use_rel(jit, addrs[i + off + 1])) { 1469 /* clrj or clgrj %dst,%src,mask,off */ 1470 EMIT6_PCREL(0xec000000, (is_jmp32 ? 0x0077 : 0x0065), 1471 dst_reg, src_reg, i, off, mask); 1472 } else { 1473 /* clr or clgr %dst,%src */ 1474 if (is_jmp32) 1475 EMIT2(0x1500, dst_reg, src_reg); 1476 else 1477 EMIT4(0xb9210000, dst_reg, src_reg); 1478 /* brcl mask,off */ 1479 EMIT6_PCREL_RILC(0xc0040000, 1480 mask >> 12, addrs[i + off + 1]); 1481 } 1482 break; 1483 branch_oc: 1484 if (!is_first_pass(jit) && 1485 can_use_rel(jit, addrs[i + off + 1])) { 1486 /* brc mask,off */ 1487 EMIT4_PCREL_RIC(0xa7040000, 1488 mask >> 12, addrs[i + off + 1]); 1489 } else { 1490 /* brcl mask,off */ 1491 EMIT6_PCREL_RILC(0xc0040000, 1492 mask >> 12, addrs[i + off + 1]); 1493 } 1494 break; 1495 } 1496 default: /* too complex, give up */ 1497 pr_err("Unknown opcode %02x\n", insn->code); 1498 return -1; 1499 } 1500 return insn_count; 1501 } 1502 1503 /* 1504 * Return whether new i-th instruction address does not violate any invariant 1505 */ 1506 static bool bpf_is_new_addr_sane(struct bpf_jit *jit, int i) 1507 { 1508 /* On the first pass anything goes */ 1509 if (is_first_pass(jit)) 1510 return true; 1511 1512 /* The codegen pass must not change anything */ 1513 if (is_codegen_pass(jit)) 1514 return jit->addrs[i] == jit->prg; 1515 1516 /* Passes in between must not increase code size */ 1517 return jit->addrs[i] >= jit->prg; 1518 } 1519 1520 /* 1521 * Update the address of i-th instruction 1522 */ 1523 static int bpf_set_addr(struct bpf_jit *jit, int i) 1524 { 1525 int delta; 1526 1527 if (is_codegen_pass(jit)) { 1528 delta = jit->prg - jit->addrs[i]; 1529 if (delta < 0) 1530 bpf_skip(jit, -delta); 1531 } 1532 if (WARN_ON_ONCE(!bpf_is_new_addr_sane(jit, i))) 1533 return -1; 1534 jit->addrs[i] = jit->prg; 1535 return 0; 1536 } 1537 1538 /* 1539 * Compile eBPF program into s390x code 1540 */ 1541 static int bpf_jit_prog(struct bpf_jit *jit, struct bpf_prog *fp, 1542 bool extra_pass, u32 stack_depth) 1543 { 1544 int i, insn_count, lit32_size, lit64_size; 1545 1546 jit->lit32 = jit->lit32_start; 1547 jit->lit64 = jit->lit64_start; 1548 jit->prg = 0; 1549 1550 bpf_jit_prologue(jit, stack_depth); 1551 if (bpf_set_addr(jit, 0) < 0) 1552 return -1; 1553 for (i = 0; i < fp->len; i += insn_count) { 1554 insn_count = bpf_jit_insn(jit, fp, i, extra_pass, stack_depth); 1555 if (insn_count < 0) 1556 return -1; 1557 /* Next instruction address */ 1558 if (bpf_set_addr(jit, i + insn_count) < 0) 1559 return -1; 1560 } 1561 bpf_jit_epilogue(jit, stack_depth); 1562 1563 lit32_size = jit->lit32 - jit->lit32_start; 1564 lit64_size = jit->lit64 - jit->lit64_start; 1565 jit->lit32_start = jit->prg; 1566 if (lit32_size) 1567 jit->lit32_start = ALIGN(jit->lit32_start, 4); 1568 jit->lit64_start = jit->lit32_start + lit32_size; 1569 if (lit64_size) 1570 jit->lit64_start = ALIGN(jit->lit64_start, 8); 1571 jit->size = jit->lit64_start + lit64_size; 1572 jit->size_prg = jit->prg; 1573 return 0; 1574 } 1575 1576 bool bpf_jit_needs_zext(void) 1577 { 1578 return true; 1579 } 1580 1581 struct s390_jit_data { 1582 struct bpf_binary_header *header; 1583 struct bpf_jit ctx; 1584 int pass; 1585 }; 1586 1587 /* 1588 * Compile eBPF program "fp" 1589 */ 1590 struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *fp) 1591 { 1592 u32 stack_depth = round_up(fp->aux->stack_depth, 8); 1593 struct bpf_prog *tmp, *orig_fp = fp; 1594 struct bpf_binary_header *header; 1595 struct s390_jit_data *jit_data; 1596 bool tmp_blinded = false; 1597 bool extra_pass = false; 1598 struct bpf_jit jit; 1599 int pass; 1600 1601 if (!fp->jit_requested) 1602 return orig_fp; 1603 1604 tmp = bpf_jit_blind_constants(fp); 1605 /* 1606 * If blinding was requested and we failed during blinding, 1607 * we must fall back to the interpreter. 1608 */ 1609 if (IS_ERR(tmp)) 1610 return orig_fp; 1611 if (tmp != fp) { 1612 tmp_blinded = true; 1613 fp = tmp; 1614 } 1615 1616 jit_data = fp->aux->jit_data; 1617 if (!jit_data) { 1618 jit_data = kzalloc(sizeof(*jit_data), GFP_KERNEL); 1619 if (!jit_data) { 1620 fp = orig_fp; 1621 goto out; 1622 } 1623 fp->aux->jit_data = jit_data; 1624 } 1625 if (jit_data->ctx.addrs) { 1626 jit = jit_data->ctx; 1627 header = jit_data->header; 1628 extra_pass = true; 1629 pass = jit_data->pass + 1; 1630 goto skip_init_ctx; 1631 } 1632 1633 memset(&jit, 0, sizeof(jit)); 1634 jit.addrs = kvcalloc(fp->len + 1, sizeof(*jit.addrs), GFP_KERNEL); 1635 if (jit.addrs == NULL) { 1636 fp = orig_fp; 1637 goto out; 1638 } 1639 /* 1640 * Three initial passes: 1641 * - 1/2: Determine clobbered registers 1642 * - 3: Calculate program size and addrs arrray 1643 */ 1644 for (pass = 1; pass <= 3; pass++) { 1645 if (bpf_jit_prog(&jit, fp, extra_pass, stack_depth)) { 1646 fp = orig_fp; 1647 goto free_addrs; 1648 } 1649 } 1650 /* 1651 * Final pass: Allocate and generate program 1652 */ 1653 header = bpf_jit_binary_alloc(jit.size, &jit.prg_buf, 8, jit_fill_hole); 1654 if (!header) { 1655 fp = orig_fp; 1656 goto free_addrs; 1657 } 1658 skip_init_ctx: 1659 if (bpf_jit_prog(&jit, fp, extra_pass, stack_depth)) { 1660 bpf_jit_binary_free(header); 1661 fp = orig_fp; 1662 goto free_addrs; 1663 } 1664 if (bpf_jit_enable > 1) { 1665 bpf_jit_dump(fp->len, jit.size, pass, jit.prg_buf); 1666 print_fn_code(jit.prg_buf, jit.size_prg); 1667 } 1668 if (!fp->is_func || extra_pass) { 1669 bpf_jit_binary_lock_ro(header); 1670 } else { 1671 jit_data->header = header; 1672 jit_data->ctx = jit; 1673 jit_data->pass = pass; 1674 } 1675 fp->bpf_func = (void *) jit.prg_buf; 1676 fp->jited = 1; 1677 fp->jited_len = jit.size; 1678 1679 if (!fp->is_func || extra_pass) { 1680 bpf_prog_fill_jited_linfo(fp, jit.addrs + 1); 1681 free_addrs: 1682 kvfree(jit.addrs); 1683 kfree(jit_data); 1684 fp->aux->jit_data = NULL; 1685 } 1686 out: 1687 if (tmp_blinded) 1688 bpf_jit_prog_release_other(fp, fp == orig_fp ? 1689 tmp : orig_fp); 1690 return fp; 1691 } 1692