1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * BPF Jit compiler for s390. 4 * 5 * Minimum build requirements: 6 * 7 * - HAVE_MARCH_Z196_FEATURES: laal, laalg 8 * - HAVE_MARCH_Z10_FEATURES: msfi, cgrj, clgrj 9 * - HAVE_MARCH_Z9_109_FEATURES: alfi, llilf, clfi, oilf, nilf 10 * - PACK_STACK 11 * - 64BIT 12 * 13 * Copyright IBM Corp. 2012,2015 14 * 15 * Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com> 16 * Michael Holzheu <holzheu@linux.vnet.ibm.com> 17 */ 18 19 #define KMSG_COMPONENT "bpf_jit" 20 #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt 21 22 #include <linux/netdevice.h> 23 #include <linux/filter.h> 24 #include <linux/init.h> 25 #include <linux/bpf.h> 26 #include <asm/cacheflush.h> 27 #include <asm/dis.h> 28 #include <asm/facility.h> 29 #include <asm/nospec-branch.h> 30 #include <asm/set_memory.h> 31 #include "bpf_jit.h" 32 33 struct bpf_jit { 34 u32 seen; /* Flags to remember seen eBPF instructions */ 35 u32 seen_reg[16]; /* Array to remember which registers are used */ 36 u32 *addrs; /* Array with relative instruction addresses */ 37 u8 *prg_buf; /* Start of program */ 38 int size; /* Size of program and literal pool */ 39 int size_prg; /* Size of program */ 40 int prg; /* Current position in program */ 41 int lit_start; /* Start of literal pool */ 42 int lit; /* Current position in literal pool */ 43 int base_ip; /* Base address for literal pool */ 44 int ret0_ip; /* Address of return 0 */ 45 int exit_ip; /* Address of exit */ 46 int r1_thunk_ip; /* Address of expoline thunk for 'br %r1' */ 47 int r14_thunk_ip; /* Address of expoline thunk for 'br %r14' */ 48 int tail_call_start; /* Tail call start offset */ 49 int labels[1]; /* Labels for local jumps */ 50 }; 51 52 #define BPF_SIZE_MAX 0xffff /* Max size for program (16 bit branches) */ 53 54 #define SEEN_SKB 1 /* skb access */ 55 #define SEEN_MEM 2 /* use mem[] for temporary storage */ 56 #define SEEN_RET0 4 /* ret0_ip points to a valid return 0 */ 57 #define SEEN_LITERAL 8 /* code uses literals */ 58 #define SEEN_FUNC 16 /* calls C functions */ 59 #define SEEN_TAIL_CALL 32 /* code uses tail calls */ 60 #define SEEN_REG_AX 64 /* code uses constant blinding */ 61 #define SEEN_STACK (SEEN_FUNC | SEEN_MEM | SEEN_SKB) 62 63 /* 64 * s390 registers 65 */ 66 #define REG_W0 (MAX_BPF_JIT_REG + 0) /* Work register 1 (even) */ 67 #define REG_W1 (MAX_BPF_JIT_REG + 1) /* Work register 2 (odd) */ 68 #define REG_SKB_DATA (MAX_BPF_JIT_REG + 2) /* SKB data register */ 69 #define REG_L (MAX_BPF_JIT_REG + 3) /* Literal pool register */ 70 #define REG_15 (MAX_BPF_JIT_REG + 4) /* Register 15 */ 71 #define REG_0 REG_W0 /* Register 0 */ 72 #define REG_1 REG_W1 /* Register 1 */ 73 #define REG_2 BPF_REG_1 /* Register 2 */ 74 #define REG_14 BPF_REG_0 /* Register 14 */ 75 76 /* 77 * Mapping of BPF registers to s390 registers 78 */ 79 static const int reg2hex[] = { 80 /* Return code */ 81 [BPF_REG_0] = 14, 82 /* Function parameters */ 83 [BPF_REG_1] = 2, 84 [BPF_REG_2] = 3, 85 [BPF_REG_3] = 4, 86 [BPF_REG_4] = 5, 87 [BPF_REG_5] = 6, 88 /* Call saved registers */ 89 [BPF_REG_6] = 7, 90 [BPF_REG_7] = 8, 91 [BPF_REG_8] = 9, 92 [BPF_REG_9] = 10, 93 /* BPF stack pointer */ 94 [BPF_REG_FP] = 13, 95 /* Register for blinding (shared with REG_SKB_DATA) */ 96 [BPF_REG_AX] = 12, 97 /* SKB data pointer */ 98 [REG_SKB_DATA] = 12, 99 /* Work registers for s390x backend */ 100 [REG_W0] = 0, 101 [REG_W1] = 1, 102 [REG_L] = 11, 103 [REG_15] = 15, 104 }; 105 106 static inline u32 reg(u32 dst_reg, u32 src_reg) 107 { 108 return reg2hex[dst_reg] << 4 | reg2hex[src_reg]; 109 } 110 111 static inline u32 reg_high(u32 reg) 112 { 113 return reg2hex[reg] << 4; 114 } 115 116 static inline void reg_set_seen(struct bpf_jit *jit, u32 b1) 117 { 118 u32 r1 = reg2hex[b1]; 119 120 if (!jit->seen_reg[r1] && r1 >= 6 && r1 <= 15) 121 jit->seen_reg[r1] = 1; 122 } 123 124 #define REG_SET_SEEN(b1) \ 125 ({ \ 126 reg_set_seen(jit, b1); \ 127 }) 128 129 #define REG_SEEN(b1) jit->seen_reg[reg2hex[(b1)]] 130 131 /* 132 * EMIT macros for code generation 133 */ 134 135 #define _EMIT2(op) \ 136 ({ \ 137 if (jit->prg_buf) \ 138 *(u16 *) (jit->prg_buf + jit->prg) = op; \ 139 jit->prg += 2; \ 140 }) 141 142 #define EMIT2(op, b1, b2) \ 143 ({ \ 144 _EMIT2(op | reg(b1, b2)); \ 145 REG_SET_SEEN(b1); \ 146 REG_SET_SEEN(b2); \ 147 }) 148 149 #define _EMIT4(op) \ 150 ({ \ 151 if (jit->prg_buf) \ 152 *(u32 *) (jit->prg_buf + jit->prg) = op; \ 153 jit->prg += 4; \ 154 }) 155 156 #define EMIT4(op, b1, b2) \ 157 ({ \ 158 _EMIT4(op | reg(b1, b2)); \ 159 REG_SET_SEEN(b1); \ 160 REG_SET_SEEN(b2); \ 161 }) 162 163 #define EMIT4_RRF(op, b1, b2, b3) \ 164 ({ \ 165 _EMIT4(op | reg_high(b3) << 8 | reg(b1, b2)); \ 166 REG_SET_SEEN(b1); \ 167 REG_SET_SEEN(b2); \ 168 REG_SET_SEEN(b3); \ 169 }) 170 171 #define _EMIT4_DISP(op, disp) \ 172 ({ \ 173 unsigned int __disp = (disp) & 0xfff; \ 174 _EMIT4(op | __disp); \ 175 }) 176 177 #define EMIT4_DISP(op, b1, b2, disp) \ 178 ({ \ 179 _EMIT4_DISP(op | reg_high(b1) << 16 | \ 180 reg_high(b2) << 8, disp); \ 181 REG_SET_SEEN(b1); \ 182 REG_SET_SEEN(b2); \ 183 }) 184 185 #define EMIT4_IMM(op, b1, imm) \ 186 ({ \ 187 unsigned int __imm = (imm) & 0xffff; \ 188 _EMIT4(op | reg_high(b1) << 16 | __imm); \ 189 REG_SET_SEEN(b1); \ 190 }) 191 192 #define EMIT4_PCREL(op, pcrel) \ 193 ({ \ 194 long __pcrel = ((pcrel) >> 1) & 0xffff; \ 195 _EMIT4(op | __pcrel); \ 196 }) 197 198 #define _EMIT6(op1, op2) \ 199 ({ \ 200 if (jit->prg_buf) { \ 201 *(u32 *) (jit->prg_buf + jit->prg) = op1; \ 202 *(u16 *) (jit->prg_buf + jit->prg + 4) = op2; \ 203 } \ 204 jit->prg += 6; \ 205 }) 206 207 #define _EMIT6_DISP(op1, op2, disp) \ 208 ({ \ 209 unsigned int __disp = (disp) & 0xfff; \ 210 _EMIT6(op1 | __disp, op2); \ 211 }) 212 213 #define _EMIT6_DISP_LH(op1, op2, disp) \ 214 ({ \ 215 u32 _disp = (u32) disp; \ 216 unsigned int __disp_h = _disp & 0xff000; \ 217 unsigned int __disp_l = _disp & 0x00fff; \ 218 _EMIT6(op1 | __disp_l, op2 | __disp_h >> 4); \ 219 }) 220 221 #define EMIT6_DISP_LH(op1, op2, b1, b2, b3, disp) \ 222 ({ \ 223 _EMIT6_DISP_LH(op1 | reg(b1, b2) << 16 | \ 224 reg_high(b3) << 8, op2, disp); \ 225 REG_SET_SEEN(b1); \ 226 REG_SET_SEEN(b2); \ 227 REG_SET_SEEN(b3); \ 228 }) 229 230 #define EMIT6_PCREL_LABEL(op1, op2, b1, b2, label, mask) \ 231 ({ \ 232 int rel = (jit->labels[label] - jit->prg) >> 1; \ 233 _EMIT6(op1 | reg(b1, b2) << 16 | (rel & 0xffff), \ 234 op2 | mask << 12); \ 235 REG_SET_SEEN(b1); \ 236 REG_SET_SEEN(b2); \ 237 }) 238 239 #define EMIT6_PCREL_IMM_LABEL(op1, op2, b1, imm, label, mask) \ 240 ({ \ 241 int rel = (jit->labels[label] - jit->prg) >> 1; \ 242 _EMIT6(op1 | (reg_high(b1) | mask) << 16 | \ 243 (rel & 0xffff), op2 | (imm & 0xff) << 8); \ 244 REG_SET_SEEN(b1); \ 245 BUILD_BUG_ON(((unsigned long) imm) > 0xff); \ 246 }) 247 248 #define EMIT6_PCREL(op1, op2, b1, b2, i, off, mask) \ 249 ({ \ 250 /* Branch instruction needs 6 bytes */ \ 251 int rel = (addrs[i + off + 1] - (addrs[i + 1] - 6)) / 2;\ 252 _EMIT6(op1 | reg(b1, b2) << 16 | (rel & 0xffff), op2 | mask); \ 253 REG_SET_SEEN(b1); \ 254 REG_SET_SEEN(b2); \ 255 }) 256 257 #define EMIT6_PCREL_RILB(op, b, target) \ 258 ({ \ 259 int rel = (target - jit->prg) / 2; \ 260 _EMIT6(op | reg_high(b) << 16 | rel >> 16, rel & 0xffff); \ 261 REG_SET_SEEN(b); \ 262 }) 263 264 #define EMIT6_PCREL_RIL(op, target) \ 265 ({ \ 266 int rel = (target - jit->prg) / 2; \ 267 _EMIT6(op | rel >> 16, rel & 0xffff); \ 268 }) 269 270 #define _EMIT6_IMM(op, imm) \ 271 ({ \ 272 unsigned int __imm = (imm); \ 273 _EMIT6(op | (__imm >> 16), __imm & 0xffff); \ 274 }) 275 276 #define EMIT6_IMM(op, b1, imm) \ 277 ({ \ 278 _EMIT6_IMM(op | reg_high(b1) << 16, imm); \ 279 REG_SET_SEEN(b1); \ 280 }) 281 282 #define EMIT_CONST_U32(val) \ 283 ({ \ 284 unsigned int ret; \ 285 ret = jit->lit - jit->base_ip; \ 286 jit->seen |= SEEN_LITERAL; \ 287 if (jit->prg_buf) \ 288 *(u32 *) (jit->prg_buf + jit->lit) = (u32) val; \ 289 jit->lit += 4; \ 290 ret; \ 291 }) 292 293 #define EMIT_CONST_U64(val) \ 294 ({ \ 295 unsigned int ret; \ 296 ret = jit->lit - jit->base_ip; \ 297 jit->seen |= SEEN_LITERAL; \ 298 if (jit->prg_buf) \ 299 *(u64 *) (jit->prg_buf + jit->lit) = (u64) val; \ 300 jit->lit += 8; \ 301 ret; \ 302 }) 303 304 #define EMIT_ZERO(b1) \ 305 ({ \ 306 /* llgfr %dst,%dst (zero extend to 64 bit) */ \ 307 EMIT4(0xb9160000, b1, b1); \ 308 REG_SET_SEEN(b1); \ 309 }) 310 311 /* 312 * Fill whole space with illegal instructions 313 */ 314 static void jit_fill_hole(void *area, unsigned int size) 315 { 316 memset(area, 0, size); 317 } 318 319 /* 320 * Save registers from "rs" (register start) to "re" (register end) on stack 321 */ 322 static void save_regs(struct bpf_jit *jit, u32 rs, u32 re) 323 { 324 u32 off = STK_OFF_R6 + (rs - 6) * 8; 325 326 if (rs == re) 327 /* stg %rs,off(%r15) */ 328 _EMIT6(0xe300f000 | rs << 20 | off, 0x0024); 329 else 330 /* stmg %rs,%re,off(%r15) */ 331 _EMIT6_DISP(0xeb00f000 | rs << 20 | re << 16, 0x0024, off); 332 } 333 334 /* 335 * Restore registers from "rs" (register start) to "re" (register end) on stack 336 */ 337 static void restore_regs(struct bpf_jit *jit, u32 rs, u32 re, u32 stack_depth) 338 { 339 u32 off = STK_OFF_R6 + (rs - 6) * 8; 340 341 if (jit->seen & SEEN_STACK) 342 off += STK_OFF + stack_depth; 343 344 if (rs == re) 345 /* lg %rs,off(%r15) */ 346 _EMIT6(0xe300f000 | rs << 20 | off, 0x0004); 347 else 348 /* lmg %rs,%re,off(%r15) */ 349 _EMIT6_DISP(0xeb00f000 | rs << 20 | re << 16, 0x0004, off); 350 } 351 352 /* 353 * Return first seen register (from start) 354 */ 355 static int get_start(struct bpf_jit *jit, int start) 356 { 357 int i; 358 359 for (i = start; i <= 15; i++) { 360 if (jit->seen_reg[i]) 361 return i; 362 } 363 return 0; 364 } 365 366 /* 367 * Return last seen register (from start) (gap >= 2) 368 */ 369 static int get_end(struct bpf_jit *jit, int start) 370 { 371 int i; 372 373 for (i = start; i < 15; i++) { 374 if (!jit->seen_reg[i] && !jit->seen_reg[i + 1]) 375 return i - 1; 376 } 377 return jit->seen_reg[15] ? 15 : 14; 378 } 379 380 #define REGS_SAVE 1 381 #define REGS_RESTORE 0 382 /* 383 * Save and restore clobbered registers (6-15) on stack. 384 * We save/restore registers in chunks with gap >= 2 registers. 385 */ 386 static void save_restore_regs(struct bpf_jit *jit, int op, u32 stack_depth) 387 { 388 389 int re = 6, rs; 390 391 do { 392 rs = get_start(jit, re); 393 if (!rs) 394 break; 395 re = get_end(jit, rs + 1); 396 if (op == REGS_SAVE) 397 save_regs(jit, rs, re); 398 else 399 restore_regs(jit, rs, re, stack_depth); 400 re++; 401 } while (re <= 15); 402 } 403 404 /* 405 * For SKB access %b1 contains the SKB pointer. For "bpf_jit.S" 406 * we store the SKB header length on the stack and the SKB data 407 * pointer in REG_SKB_DATA if BPF_REG_AX is not used. 408 */ 409 static void emit_load_skb_data_hlen(struct bpf_jit *jit) 410 { 411 /* Header length: llgf %w1,<len>(%b1) */ 412 EMIT6_DISP_LH(0xe3000000, 0x0016, REG_W1, REG_0, BPF_REG_1, 413 offsetof(struct sk_buff, len)); 414 /* s %w1,<data_len>(%b1) */ 415 EMIT4_DISP(0x5b000000, REG_W1, BPF_REG_1, 416 offsetof(struct sk_buff, data_len)); 417 /* stg %w1,ST_OFF_HLEN(%r0,%r15) */ 418 EMIT6_DISP_LH(0xe3000000, 0x0024, REG_W1, REG_0, REG_15, STK_OFF_HLEN); 419 if (!(jit->seen & SEEN_REG_AX)) 420 /* lg %skb_data,data_off(%b1) */ 421 EMIT6_DISP_LH(0xe3000000, 0x0004, REG_SKB_DATA, REG_0, 422 BPF_REG_1, offsetof(struct sk_buff, data)); 423 } 424 425 /* 426 * Emit function prologue 427 * 428 * Save registers and create stack frame if necessary. 429 * See stack frame layout desription in "bpf_jit.h"! 430 */ 431 static void bpf_jit_prologue(struct bpf_jit *jit, u32 stack_depth) 432 { 433 if (jit->seen & SEEN_TAIL_CALL) { 434 /* xc STK_OFF_TCCNT(4,%r15),STK_OFF_TCCNT(%r15) */ 435 _EMIT6(0xd703f000 | STK_OFF_TCCNT, 0xf000 | STK_OFF_TCCNT); 436 } else { 437 /* j tail_call_start: NOP if no tail calls are used */ 438 EMIT4_PCREL(0xa7f40000, 6); 439 _EMIT2(0); 440 } 441 /* Tail calls have to skip above initialization */ 442 jit->tail_call_start = jit->prg; 443 /* Save registers */ 444 save_restore_regs(jit, REGS_SAVE, stack_depth); 445 /* Setup literal pool */ 446 if (jit->seen & SEEN_LITERAL) { 447 /* basr %r13,0 */ 448 EMIT2(0x0d00, REG_L, REG_0); 449 jit->base_ip = jit->prg; 450 } 451 /* Setup stack and backchain */ 452 if (jit->seen & SEEN_STACK) { 453 if (jit->seen & SEEN_FUNC) 454 /* lgr %w1,%r15 (backchain) */ 455 EMIT4(0xb9040000, REG_W1, REG_15); 456 /* la %bfp,STK_160_UNUSED(%r15) (BPF frame pointer) */ 457 EMIT4_DISP(0x41000000, BPF_REG_FP, REG_15, STK_160_UNUSED); 458 /* aghi %r15,-STK_OFF */ 459 EMIT4_IMM(0xa70b0000, REG_15, -(STK_OFF + stack_depth)); 460 if (jit->seen & SEEN_FUNC) 461 /* stg %w1,152(%r15) (backchain) */ 462 EMIT6_DISP_LH(0xe3000000, 0x0024, REG_W1, REG_0, 463 REG_15, 152); 464 } 465 if (jit->seen & SEEN_SKB) { 466 emit_load_skb_data_hlen(jit); 467 /* stg %b1,ST_OFF_SKBP(%r0,%r15) */ 468 EMIT6_DISP_LH(0xe3000000, 0x0024, BPF_REG_1, REG_0, REG_15, 469 STK_OFF_SKBP); 470 } 471 } 472 473 /* 474 * Function epilogue 475 */ 476 static void bpf_jit_epilogue(struct bpf_jit *jit, u32 stack_depth) 477 { 478 /* Return 0 */ 479 if (jit->seen & SEEN_RET0) { 480 jit->ret0_ip = jit->prg; 481 /* lghi %b0,0 */ 482 EMIT4_IMM(0xa7090000, BPF_REG_0, 0); 483 } 484 jit->exit_ip = jit->prg; 485 /* Load exit code: lgr %r2,%b0 */ 486 EMIT4(0xb9040000, REG_2, BPF_REG_0); 487 /* Restore registers */ 488 save_restore_regs(jit, REGS_RESTORE, stack_depth); 489 if (IS_ENABLED(CC_USING_EXPOLINE) && !nospec_disable) { 490 jit->r14_thunk_ip = jit->prg; 491 /* Generate __s390_indirect_jump_r14 thunk */ 492 if (test_facility(35)) { 493 /* exrl %r0,.+10 */ 494 EMIT6_PCREL_RIL(0xc6000000, jit->prg + 10); 495 } else { 496 /* larl %r1,.+14 */ 497 EMIT6_PCREL_RILB(0xc0000000, REG_1, jit->prg + 14); 498 /* ex 0,0(%r1) */ 499 EMIT4_DISP(0x44000000, REG_0, REG_1, 0); 500 } 501 /* j . */ 502 EMIT4_PCREL(0xa7f40000, 0); 503 } 504 /* br %r14 */ 505 _EMIT2(0x07fe); 506 507 if (IS_ENABLED(CC_USING_EXPOLINE) && !nospec_disable && 508 (jit->seen & SEEN_FUNC)) { 509 jit->r1_thunk_ip = jit->prg; 510 /* Generate __s390_indirect_jump_r1 thunk */ 511 if (test_facility(35)) { 512 /* exrl %r0,.+10 */ 513 EMIT6_PCREL_RIL(0xc6000000, jit->prg + 10); 514 /* j . */ 515 EMIT4_PCREL(0xa7f40000, 0); 516 /* br %r1 */ 517 _EMIT2(0x07f1); 518 } else { 519 /* larl %r1,.+14 */ 520 EMIT6_PCREL_RILB(0xc0000000, REG_1, jit->prg + 14); 521 /* ex 0,S390_lowcore.br_r1_tampoline */ 522 EMIT4_DISP(0x44000000, REG_0, REG_0, 523 offsetof(struct lowcore, br_r1_trampoline)); 524 /* j . */ 525 EMIT4_PCREL(0xa7f40000, 0); 526 } 527 } 528 } 529 530 /* 531 * Compile one eBPF instruction into s390x code 532 * 533 * NOTE: Use noinline because for gcov (-fprofile-arcs) gcc allocates a lot of 534 * stack space for the large switch statement. 535 */ 536 static noinline int bpf_jit_insn(struct bpf_jit *jit, struct bpf_prog *fp, int i) 537 { 538 struct bpf_insn *insn = &fp->insnsi[i]; 539 int jmp_off, last, insn_count = 1; 540 unsigned int func_addr, mask; 541 u32 dst_reg = insn->dst_reg; 542 u32 src_reg = insn->src_reg; 543 u32 *addrs = jit->addrs; 544 s32 imm = insn->imm; 545 s16 off = insn->off; 546 547 if (dst_reg == BPF_REG_AX || src_reg == BPF_REG_AX) 548 jit->seen |= SEEN_REG_AX; 549 switch (insn->code) { 550 /* 551 * BPF_MOV 552 */ 553 case BPF_ALU | BPF_MOV | BPF_X: /* dst = (u32) src */ 554 /* llgfr %dst,%src */ 555 EMIT4(0xb9160000, dst_reg, src_reg); 556 break; 557 case BPF_ALU64 | BPF_MOV | BPF_X: /* dst = src */ 558 /* lgr %dst,%src */ 559 EMIT4(0xb9040000, dst_reg, src_reg); 560 break; 561 case BPF_ALU | BPF_MOV | BPF_K: /* dst = (u32) imm */ 562 /* llilf %dst,imm */ 563 EMIT6_IMM(0xc00f0000, dst_reg, imm); 564 break; 565 case BPF_ALU64 | BPF_MOV | BPF_K: /* dst = imm */ 566 /* lgfi %dst,imm */ 567 EMIT6_IMM(0xc0010000, dst_reg, imm); 568 break; 569 /* 570 * BPF_LD 64 571 */ 572 case BPF_LD | BPF_IMM | BPF_DW: /* dst = (u64) imm */ 573 { 574 /* 16 byte instruction that uses two 'struct bpf_insn' */ 575 u64 imm64; 576 577 imm64 = (u64)(u32) insn[0].imm | ((u64)(u32) insn[1].imm) << 32; 578 /* lg %dst,<d(imm)>(%l) */ 579 EMIT6_DISP_LH(0xe3000000, 0x0004, dst_reg, REG_0, REG_L, 580 EMIT_CONST_U64(imm64)); 581 insn_count = 2; 582 break; 583 } 584 /* 585 * BPF_ADD 586 */ 587 case BPF_ALU | BPF_ADD | BPF_X: /* dst = (u32) dst + (u32) src */ 588 /* ar %dst,%src */ 589 EMIT2(0x1a00, dst_reg, src_reg); 590 EMIT_ZERO(dst_reg); 591 break; 592 case BPF_ALU64 | BPF_ADD | BPF_X: /* dst = dst + src */ 593 /* agr %dst,%src */ 594 EMIT4(0xb9080000, dst_reg, src_reg); 595 break; 596 case BPF_ALU | BPF_ADD | BPF_K: /* dst = (u32) dst + (u32) imm */ 597 if (!imm) 598 break; 599 /* alfi %dst,imm */ 600 EMIT6_IMM(0xc20b0000, dst_reg, imm); 601 EMIT_ZERO(dst_reg); 602 break; 603 case BPF_ALU64 | BPF_ADD | BPF_K: /* dst = dst + imm */ 604 if (!imm) 605 break; 606 /* agfi %dst,imm */ 607 EMIT6_IMM(0xc2080000, dst_reg, imm); 608 break; 609 /* 610 * BPF_SUB 611 */ 612 case BPF_ALU | BPF_SUB | BPF_X: /* dst = (u32) dst - (u32) src */ 613 /* sr %dst,%src */ 614 EMIT2(0x1b00, dst_reg, src_reg); 615 EMIT_ZERO(dst_reg); 616 break; 617 case BPF_ALU64 | BPF_SUB | BPF_X: /* dst = dst - src */ 618 /* sgr %dst,%src */ 619 EMIT4(0xb9090000, dst_reg, src_reg); 620 break; 621 case BPF_ALU | BPF_SUB | BPF_K: /* dst = (u32) dst - (u32) imm */ 622 if (!imm) 623 break; 624 /* alfi %dst,-imm */ 625 EMIT6_IMM(0xc20b0000, dst_reg, -imm); 626 EMIT_ZERO(dst_reg); 627 break; 628 case BPF_ALU64 | BPF_SUB | BPF_K: /* dst = dst - imm */ 629 if (!imm) 630 break; 631 /* agfi %dst,-imm */ 632 EMIT6_IMM(0xc2080000, dst_reg, -imm); 633 break; 634 /* 635 * BPF_MUL 636 */ 637 case BPF_ALU | BPF_MUL | BPF_X: /* dst = (u32) dst * (u32) src */ 638 /* msr %dst,%src */ 639 EMIT4(0xb2520000, dst_reg, src_reg); 640 EMIT_ZERO(dst_reg); 641 break; 642 case BPF_ALU64 | BPF_MUL | BPF_X: /* dst = dst * src */ 643 /* msgr %dst,%src */ 644 EMIT4(0xb90c0000, dst_reg, src_reg); 645 break; 646 case BPF_ALU | BPF_MUL | BPF_K: /* dst = (u32) dst * (u32) imm */ 647 if (imm == 1) 648 break; 649 /* msfi %r5,imm */ 650 EMIT6_IMM(0xc2010000, dst_reg, imm); 651 EMIT_ZERO(dst_reg); 652 break; 653 case BPF_ALU64 | BPF_MUL | BPF_K: /* dst = dst * imm */ 654 if (imm == 1) 655 break; 656 /* msgfi %dst,imm */ 657 EMIT6_IMM(0xc2000000, dst_reg, imm); 658 break; 659 /* 660 * BPF_DIV / BPF_MOD 661 */ 662 case BPF_ALU | BPF_DIV | BPF_X: /* dst = (u32) dst / (u32) src */ 663 case BPF_ALU | BPF_MOD | BPF_X: /* dst = (u32) dst % (u32) src */ 664 { 665 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0; 666 667 /* lhi %w0,0 */ 668 EMIT4_IMM(0xa7080000, REG_W0, 0); 669 /* lr %w1,%dst */ 670 EMIT2(0x1800, REG_W1, dst_reg); 671 /* dlr %w0,%src */ 672 EMIT4(0xb9970000, REG_W0, src_reg); 673 /* llgfr %dst,%rc */ 674 EMIT4(0xb9160000, dst_reg, rc_reg); 675 break; 676 } 677 case BPF_ALU64 | BPF_DIV | BPF_X: /* dst = dst / src */ 678 case BPF_ALU64 | BPF_MOD | BPF_X: /* dst = dst % src */ 679 { 680 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0; 681 682 /* lghi %w0,0 */ 683 EMIT4_IMM(0xa7090000, REG_W0, 0); 684 /* lgr %w1,%dst */ 685 EMIT4(0xb9040000, REG_W1, dst_reg); 686 /* dlgr %w0,%dst */ 687 EMIT4(0xb9870000, REG_W0, src_reg); 688 /* lgr %dst,%rc */ 689 EMIT4(0xb9040000, dst_reg, rc_reg); 690 break; 691 } 692 case BPF_ALU | BPF_DIV | BPF_K: /* dst = (u32) dst / (u32) imm */ 693 case BPF_ALU | BPF_MOD | BPF_K: /* dst = (u32) dst % (u32) imm */ 694 { 695 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0; 696 697 if (imm == 1) { 698 if (BPF_OP(insn->code) == BPF_MOD) 699 /* lhgi %dst,0 */ 700 EMIT4_IMM(0xa7090000, dst_reg, 0); 701 break; 702 } 703 /* lhi %w0,0 */ 704 EMIT4_IMM(0xa7080000, REG_W0, 0); 705 /* lr %w1,%dst */ 706 EMIT2(0x1800, REG_W1, dst_reg); 707 /* dl %w0,<d(imm)>(%l) */ 708 EMIT6_DISP_LH(0xe3000000, 0x0097, REG_W0, REG_0, REG_L, 709 EMIT_CONST_U32(imm)); 710 /* llgfr %dst,%rc */ 711 EMIT4(0xb9160000, dst_reg, rc_reg); 712 break; 713 } 714 case BPF_ALU64 | BPF_DIV | BPF_K: /* dst = dst / imm */ 715 case BPF_ALU64 | BPF_MOD | BPF_K: /* dst = dst % imm */ 716 { 717 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0; 718 719 if (imm == 1) { 720 if (BPF_OP(insn->code) == BPF_MOD) 721 /* lhgi %dst,0 */ 722 EMIT4_IMM(0xa7090000, dst_reg, 0); 723 break; 724 } 725 /* lghi %w0,0 */ 726 EMIT4_IMM(0xa7090000, REG_W0, 0); 727 /* lgr %w1,%dst */ 728 EMIT4(0xb9040000, REG_W1, dst_reg); 729 /* dlg %w0,<d(imm)>(%l) */ 730 EMIT6_DISP_LH(0xe3000000, 0x0087, REG_W0, REG_0, REG_L, 731 EMIT_CONST_U64(imm)); 732 /* lgr %dst,%rc */ 733 EMIT4(0xb9040000, dst_reg, rc_reg); 734 break; 735 } 736 /* 737 * BPF_AND 738 */ 739 case BPF_ALU | BPF_AND | BPF_X: /* dst = (u32) dst & (u32) src */ 740 /* nr %dst,%src */ 741 EMIT2(0x1400, dst_reg, src_reg); 742 EMIT_ZERO(dst_reg); 743 break; 744 case BPF_ALU64 | BPF_AND | BPF_X: /* dst = dst & src */ 745 /* ngr %dst,%src */ 746 EMIT4(0xb9800000, dst_reg, src_reg); 747 break; 748 case BPF_ALU | BPF_AND | BPF_K: /* dst = (u32) dst & (u32) imm */ 749 /* nilf %dst,imm */ 750 EMIT6_IMM(0xc00b0000, dst_reg, imm); 751 EMIT_ZERO(dst_reg); 752 break; 753 case BPF_ALU64 | BPF_AND | BPF_K: /* dst = dst & imm */ 754 /* ng %dst,<d(imm)>(%l) */ 755 EMIT6_DISP_LH(0xe3000000, 0x0080, dst_reg, REG_0, REG_L, 756 EMIT_CONST_U64(imm)); 757 break; 758 /* 759 * BPF_OR 760 */ 761 case BPF_ALU | BPF_OR | BPF_X: /* dst = (u32) dst | (u32) src */ 762 /* or %dst,%src */ 763 EMIT2(0x1600, dst_reg, src_reg); 764 EMIT_ZERO(dst_reg); 765 break; 766 case BPF_ALU64 | BPF_OR | BPF_X: /* dst = dst | src */ 767 /* ogr %dst,%src */ 768 EMIT4(0xb9810000, dst_reg, src_reg); 769 break; 770 case BPF_ALU | BPF_OR | BPF_K: /* dst = (u32) dst | (u32) imm */ 771 /* oilf %dst,imm */ 772 EMIT6_IMM(0xc00d0000, dst_reg, imm); 773 EMIT_ZERO(dst_reg); 774 break; 775 case BPF_ALU64 | BPF_OR | BPF_K: /* dst = dst | imm */ 776 /* og %dst,<d(imm)>(%l) */ 777 EMIT6_DISP_LH(0xe3000000, 0x0081, dst_reg, REG_0, REG_L, 778 EMIT_CONST_U64(imm)); 779 break; 780 /* 781 * BPF_XOR 782 */ 783 case BPF_ALU | BPF_XOR | BPF_X: /* dst = (u32) dst ^ (u32) src */ 784 /* xr %dst,%src */ 785 EMIT2(0x1700, dst_reg, src_reg); 786 EMIT_ZERO(dst_reg); 787 break; 788 case BPF_ALU64 | BPF_XOR | BPF_X: /* dst = dst ^ src */ 789 /* xgr %dst,%src */ 790 EMIT4(0xb9820000, dst_reg, src_reg); 791 break; 792 case BPF_ALU | BPF_XOR | BPF_K: /* dst = (u32) dst ^ (u32) imm */ 793 if (!imm) 794 break; 795 /* xilf %dst,imm */ 796 EMIT6_IMM(0xc0070000, dst_reg, imm); 797 EMIT_ZERO(dst_reg); 798 break; 799 case BPF_ALU64 | BPF_XOR | BPF_K: /* dst = dst ^ imm */ 800 /* xg %dst,<d(imm)>(%l) */ 801 EMIT6_DISP_LH(0xe3000000, 0x0082, dst_reg, REG_0, REG_L, 802 EMIT_CONST_U64(imm)); 803 break; 804 /* 805 * BPF_LSH 806 */ 807 case BPF_ALU | BPF_LSH | BPF_X: /* dst = (u32) dst << (u32) src */ 808 /* sll %dst,0(%src) */ 809 EMIT4_DISP(0x89000000, dst_reg, src_reg, 0); 810 EMIT_ZERO(dst_reg); 811 break; 812 case BPF_ALU64 | BPF_LSH | BPF_X: /* dst = dst << src */ 813 /* sllg %dst,%dst,0(%src) */ 814 EMIT6_DISP_LH(0xeb000000, 0x000d, dst_reg, dst_reg, src_reg, 0); 815 break; 816 case BPF_ALU | BPF_LSH | BPF_K: /* dst = (u32) dst << (u32) imm */ 817 if (imm == 0) 818 break; 819 /* sll %dst,imm(%r0) */ 820 EMIT4_DISP(0x89000000, dst_reg, REG_0, imm); 821 EMIT_ZERO(dst_reg); 822 break; 823 case BPF_ALU64 | BPF_LSH | BPF_K: /* dst = dst << imm */ 824 if (imm == 0) 825 break; 826 /* sllg %dst,%dst,imm(%r0) */ 827 EMIT6_DISP_LH(0xeb000000, 0x000d, dst_reg, dst_reg, REG_0, imm); 828 break; 829 /* 830 * BPF_RSH 831 */ 832 case BPF_ALU | BPF_RSH | BPF_X: /* dst = (u32) dst >> (u32) src */ 833 /* srl %dst,0(%src) */ 834 EMIT4_DISP(0x88000000, dst_reg, src_reg, 0); 835 EMIT_ZERO(dst_reg); 836 break; 837 case BPF_ALU64 | BPF_RSH | BPF_X: /* dst = dst >> src */ 838 /* srlg %dst,%dst,0(%src) */ 839 EMIT6_DISP_LH(0xeb000000, 0x000c, dst_reg, dst_reg, src_reg, 0); 840 break; 841 case BPF_ALU | BPF_RSH | BPF_K: /* dst = (u32) dst >> (u32) imm */ 842 if (imm == 0) 843 break; 844 /* srl %dst,imm(%r0) */ 845 EMIT4_DISP(0x88000000, dst_reg, REG_0, imm); 846 EMIT_ZERO(dst_reg); 847 break; 848 case BPF_ALU64 | BPF_RSH | BPF_K: /* dst = dst >> imm */ 849 if (imm == 0) 850 break; 851 /* srlg %dst,%dst,imm(%r0) */ 852 EMIT6_DISP_LH(0xeb000000, 0x000c, dst_reg, dst_reg, REG_0, imm); 853 break; 854 /* 855 * BPF_ARSH 856 */ 857 case BPF_ALU64 | BPF_ARSH | BPF_X: /* ((s64) dst) >>= src */ 858 /* srag %dst,%dst,0(%src) */ 859 EMIT6_DISP_LH(0xeb000000, 0x000a, dst_reg, dst_reg, src_reg, 0); 860 break; 861 case BPF_ALU64 | BPF_ARSH | BPF_K: /* ((s64) dst) >>= imm */ 862 if (imm == 0) 863 break; 864 /* srag %dst,%dst,imm(%r0) */ 865 EMIT6_DISP_LH(0xeb000000, 0x000a, dst_reg, dst_reg, REG_0, imm); 866 break; 867 /* 868 * BPF_NEG 869 */ 870 case BPF_ALU | BPF_NEG: /* dst = (u32) -dst */ 871 /* lcr %dst,%dst */ 872 EMIT2(0x1300, dst_reg, dst_reg); 873 EMIT_ZERO(dst_reg); 874 break; 875 case BPF_ALU64 | BPF_NEG: /* dst = -dst */ 876 /* lcgr %dst,%dst */ 877 EMIT4(0xb9130000, dst_reg, dst_reg); 878 break; 879 /* 880 * BPF_FROM_BE/LE 881 */ 882 case BPF_ALU | BPF_END | BPF_FROM_BE: 883 /* s390 is big endian, therefore only clear high order bytes */ 884 switch (imm) { 885 case 16: /* dst = (u16) cpu_to_be16(dst) */ 886 /* llghr %dst,%dst */ 887 EMIT4(0xb9850000, dst_reg, dst_reg); 888 break; 889 case 32: /* dst = (u32) cpu_to_be32(dst) */ 890 /* llgfr %dst,%dst */ 891 EMIT4(0xb9160000, dst_reg, dst_reg); 892 break; 893 case 64: /* dst = (u64) cpu_to_be64(dst) */ 894 break; 895 } 896 break; 897 case BPF_ALU | BPF_END | BPF_FROM_LE: 898 switch (imm) { 899 case 16: /* dst = (u16) cpu_to_le16(dst) */ 900 /* lrvr %dst,%dst */ 901 EMIT4(0xb91f0000, dst_reg, dst_reg); 902 /* srl %dst,16(%r0) */ 903 EMIT4_DISP(0x88000000, dst_reg, REG_0, 16); 904 /* llghr %dst,%dst */ 905 EMIT4(0xb9850000, dst_reg, dst_reg); 906 break; 907 case 32: /* dst = (u32) cpu_to_le32(dst) */ 908 /* lrvr %dst,%dst */ 909 EMIT4(0xb91f0000, dst_reg, dst_reg); 910 /* llgfr %dst,%dst */ 911 EMIT4(0xb9160000, dst_reg, dst_reg); 912 break; 913 case 64: /* dst = (u64) cpu_to_le64(dst) */ 914 /* lrvgr %dst,%dst */ 915 EMIT4(0xb90f0000, dst_reg, dst_reg); 916 break; 917 } 918 break; 919 /* 920 * BPF_ST(X) 921 */ 922 case BPF_STX | BPF_MEM | BPF_B: /* *(u8 *)(dst + off) = src_reg */ 923 /* stcy %src,off(%dst) */ 924 EMIT6_DISP_LH(0xe3000000, 0x0072, src_reg, dst_reg, REG_0, off); 925 jit->seen |= SEEN_MEM; 926 break; 927 case BPF_STX | BPF_MEM | BPF_H: /* (u16 *)(dst + off) = src */ 928 /* sthy %src,off(%dst) */ 929 EMIT6_DISP_LH(0xe3000000, 0x0070, src_reg, dst_reg, REG_0, off); 930 jit->seen |= SEEN_MEM; 931 break; 932 case BPF_STX | BPF_MEM | BPF_W: /* *(u32 *)(dst + off) = src */ 933 /* sty %src,off(%dst) */ 934 EMIT6_DISP_LH(0xe3000000, 0x0050, src_reg, dst_reg, REG_0, off); 935 jit->seen |= SEEN_MEM; 936 break; 937 case BPF_STX | BPF_MEM | BPF_DW: /* (u64 *)(dst + off) = src */ 938 /* stg %src,off(%dst) */ 939 EMIT6_DISP_LH(0xe3000000, 0x0024, src_reg, dst_reg, REG_0, off); 940 jit->seen |= SEEN_MEM; 941 break; 942 case BPF_ST | BPF_MEM | BPF_B: /* *(u8 *)(dst + off) = imm */ 943 /* lhi %w0,imm */ 944 EMIT4_IMM(0xa7080000, REG_W0, (u8) imm); 945 /* stcy %w0,off(dst) */ 946 EMIT6_DISP_LH(0xe3000000, 0x0072, REG_W0, dst_reg, REG_0, off); 947 jit->seen |= SEEN_MEM; 948 break; 949 case BPF_ST | BPF_MEM | BPF_H: /* (u16 *)(dst + off) = imm */ 950 /* lhi %w0,imm */ 951 EMIT4_IMM(0xa7080000, REG_W0, (u16) imm); 952 /* sthy %w0,off(dst) */ 953 EMIT6_DISP_LH(0xe3000000, 0x0070, REG_W0, dst_reg, REG_0, off); 954 jit->seen |= SEEN_MEM; 955 break; 956 case BPF_ST | BPF_MEM | BPF_W: /* *(u32 *)(dst + off) = imm */ 957 /* llilf %w0,imm */ 958 EMIT6_IMM(0xc00f0000, REG_W0, (u32) imm); 959 /* sty %w0,off(%dst) */ 960 EMIT6_DISP_LH(0xe3000000, 0x0050, REG_W0, dst_reg, REG_0, off); 961 jit->seen |= SEEN_MEM; 962 break; 963 case BPF_ST | BPF_MEM | BPF_DW: /* *(u64 *)(dst + off) = imm */ 964 /* lgfi %w0,imm */ 965 EMIT6_IMM(0xc0010000, REG_W0, imm); 966 /* stg %w0,off(%dst) */ 967 EMIT6_DISP_LH(0xe3000000, 0x0024, REG_W0, dst_reg, REG_0, off); 968 jit->seen |= SEEN_MEM; 969 break; 970 /* 971 * BPF_STX XADD (atomic_add) 972 */ 973 case BPF_STX | BPF_XADD | BPF_W: /* *(u32 *)(dst + off) += src */ 974 /* laal %w0,%src,off(%dst) */ 975 EMIT6_DISP_LH(0xeb000000, 0x00fa, REG_W0, src_reg, 976 dst_reg, off); 977 jit->seen |= SEEN_MEM; 978 break; 979 case BPF_STX | BPF_XADD | BPF_DW: /* *(u64 *)(dst + off) += src */ 980 /* laalg %w0,%src,off(%dst) */ 981 EMIT6_DISP_LH(0xeb000000, 0x00ea, REG_W0, src_reg, 982 dst_reg, off); 983 jit->seen |= SEEN_MEM; 984 break; 985 /* 986 * BPF_LDX 987 */ 988 case BPF_LDX | BPF_MEM | BPF_B: /* dst = *(u8 *)(ul) (src + off) */ 989 /* llgc %dst,0(off,%src) */ 990 EMIT6_DISP_LH(0xe3000000, 0x0090, dst_reg, src_reg, REG_0, off); 991 jit->seen |= SEEN_MEM; 992 break; 993 case BPF_LDX | BPF_MEM | BPF_H: /* dst = *(u16 *)(ul) (src + off) */ 994 /* llgh %dst,0(off,%src) */ 995 EMIT6_DISP_LH(0xe3000000, 0x0091, dst_reg, src_reg, REG_0, off); 996 jit->seen |= SEEN_MEM; 997 break; 998 case BPF_LDX | BPF_MEM | BPF_W: /* dst = *(u32 *)(ul) (src + off) */ 999 /* llgf %dst,off(%src) */ 1000 jit->seen |= SEEN_MEM; 1001 EMIT6_DISP_LH(0xe3000000, 0x0016, dst_reg, src_reg, REG_0, off); 1002 break; 1003 case BPF_LDX | BPF_MEM | BPF_DW: /* dst = *(u64 *)(ul) (src + off) */ 1004 /* lg %dst,0(off,%src) */ 1005 jit->seen |= SEEN_MEM; 1006 EMIT6_DISP_LH(0xe3000000, 0x0004, dst_reg, src_reg, REG_0, off); 1007 break; 1008 /* 1009 * BPF_JMP / CALL 1010 */ 1011 case BPF_JMP | BPF_CALL: 1012 { 1013 /* 1014 * b0 = (__bpf_call_base + imm)(b1, b2, b3, b4, b5) 1015 */ 1016 const u64 func = (u64)__bpf_call_base + imm; 1017 1018 REG_SET_SEEN(BPF_REG_5); 1019 jit->seen |= SEEN_FUNC; 1020 /* lg %w1,<d(imm)>(%l) */ 1021 EMIT6_DISP_LH(0xe3000000, 0x0004, REG_W1, REG_0, REG_L, 1022 EMIT_CONST_U64(func)); 1023 if (IS_ENABLED(CC_USING_EXPOLINE) && !nospec_disable) { 1024 /* brasl %r14,__s390_indirect_jump_r1 */ 1025 EMIT6_PCREL_RILB(0xc0050000, REG_14, jit->r1_thunk_ip); 1026 } else { 1027 /* basr %r14,%w1 */ 1028 EMIT2(0x0d00, REG_14, REG_W1); 1029 } 1030 /* lgr %b0,%r2: load return value into %b0 */ 1031 EMIT4(0xb9040000, BPF_REG_0, REG_2); 1032 if ((jit->seen & SEEN_SKB) && 1033 bpf_helper_changes_pkt_data((void *)func)) { 1034 /* lg %b1,ST_OFF_SKBP(%r15) */ 1035 EMIT6_DISP_LH(0xe3000000, 0x0004, BPF_REG_1, REG_0, 1036 REG_15, STK_OFF_SKBP); 1037 emit_load_skb_data_hlen(jit); 1038 } 1039 break; 1040 } 1041 case BPF_JMP | BPF_TAIL_CALL: 1042 /* 1043 * Implicit input: 1044 * B1: pointer to ctx 1045 * B2: pointer to bpf_array 1046 * B3: index in bpf_array 1047 */ 1048 jit->seen |= SEEN_TAIL_CALL; 1049 1050 /* 1051 * if (index >= array->map.max_entries) 1052 * goto out; 1053 */ 1054 1055 /* llgf %w1,map.max_entries(%b2) */ 1056 EMIT6_DISP_LH(0xe3000000, 0x0016, REG_W1, REG_0, BPF_REG_2, 1057 offsetof(struct bpf_array, map.max_entries)); 1058 /* clgrj %b3,%w1,0xa,label0: if %b3 >= %w1 goto out */ 1059 EMIT6_PCREL_LABEL(0xec000000, 0x0065, BPF_REG_3, 1060 REG_W1, 0, 0xa); 1061 1062 /* 1063 * if (tail_call_cnt++ > MAX_TAIL_CALL_CNT) 1064 * goto out; 1065 */ 1066 1067 if (jit->seen & SEEN_STACK) 1068 off = STK_OFF_TCCNT + STK_OFF + fp->aux->stack_depth; 1069 else 1070 off = STK_OFF_TCCNT; 1071 /* lhi %w0,1 */ 1072 EMIT4_IMM(0xa7080000, REG_W0, 1); 1073 /* laal %w1,%w0,off(%r15) */ 1074 EMIT6_DISP_LH(0xeb000000, 0x00fa, REG_W1, REG_W0, REG_15, off); 1075 /* clij %w1,MAX_TAIL_CALL_CNT,0x2,label0 */ 1076 EMIT6_PCREL_IMM_LABEL(0xec000000, 0x007f, REG_W1, 1077 MAX_TAIL_CALL_CNT, 0, 0x2); 1078 1079 /* 1080 * prog = array->ptrs[index]; 1081 * if (prog == NULL) 1082 * goto out; 1083 */ 1084 1085 /* sllg %r1,%b3,3: %r1 = index * 8 */ 1086 EMIT6_DISP_LH(0xeb000000, 0x000d, REG_1, BPF_REG_3, REG_0, 3); 1087 /* lg %r1,prog(%b2,%r1) */ 1088 EMIT6_DISP_LH(0xe3000000, 0x0004, REG_1, BPF_REG_2, 1089 REG_1, offsetof(struct bpf_array, ptrs)); 1090 /* clgij %r1,0,0x8,label0 */ 1091 EMIT6_PCREL_IMM_LABEL(0xec000000, 0x007d, REG_1, 0, 0, 0x8); 1092 1093 /* 1094 * Restore registers before calling function 1095 */ 1096 save_restore_regs(jit, REGS_RESTORE, fp->aux->stack_depth); 1097 1098 /* 1099 * goto *(prog->bpf_func + tail_call_start); 1100 */ 1101 1102 /* lg %r1,bpf_func(%r1) */ 1103 EMIT6_DISP_LH(0xe3000000, 0x0004, REG_1, REG_1, REG_0, 1104 offsetof(struct bpf_prog, bpf_func)); 1105 /* bc 0xf,tail_call_start(%r1) */ 1106 _EMIT4(0x47f01000 + jit->tail_call_start); 1107 /* out: */ 1108 jit->labels[0] = jit->prg; 1109 break; 1110 case BPF_JMP | BPF_EXIT: /* return b0 */ 1111 last = (i == fp->len - 1) ? 1 : 0; 1112 if (last && !(jit->seen & SEEN_RET0)) 1113 break; 1114 /* j <exit> */ 1115 EMIT4_PCREL(0xa7f40000, jit->exit_ip - jit->prg); 1116 break; 1117 /* 1118 * Branch relative (number of skipped instructions) to offset on 1119 * condition. 1120 * 1121 * Condition code to mask mapping: 1122 * 1123 * CC | Description | Mask 1124 * ------------------------------ 1125 * 0 | Operands equal | 8 1126 * 1 | First operand low | 4 1127 * 2 | First operand high | 2 1128 * 3 | Unused | 1 1129 * 1130 * For s390x relative branches: ip = ip + off_bytes 1131 * For BPF relative branches: insn = insn + off_insns + 1 1132 * 1133 * For example for s390x with offset 0 we jump to the branch 1134 * instruction itself (loop) and for BPF with offset 0 we 1135 * branch to the instruction behind the branch. 1136 */ 1137 case BPF_JMP | BPF_JA: /* if (true) */ 1138 mask = 0xf000; /* j */ 1139 goto branch_oc; 1140 case BPF_JMP | BPF_JSGT | BPF_K: /* ((s64) dst > (s64) imm) */ 1141 mask = 0x2000; /* jh */ 1142 goto branch_ks; 1143 case BPF_JMP | BPF_JSLT | BPF_K: /* ((s64) dst < (s64) imm) */ 1144 mask = 0x4000; /* jl */ 1145 goto branch_ks; 1146 case BPF_JMP | BPF_JSGE | BPF_K: /* ((s64) dst >= (s64) imm) */ 1147 mask = 0xa000; /* jhe */ 1148 goto branch_ks; 1149 case BPF_JMP | BPF_JSLE | BPF_K: /* ((s64) dst <= (s64) imm) */ 1150 mask = 0xc000; /* jle */ 1151 goto branch_ks; 1152 case BPF_JMP | BPF_JGT | BPF_K: /* (dst_reg > imm) */ 1153 mask = 0x2000; /* jh */ 1154 goto branch_ku; 1155 case BPF_JMP | BPF_JLT | BPF_K: /* (dst_reg < imm) */ 1156 mask = 0x4000; /* jl */ 1157 goto branch_ku; 1158 case BPF_JMP | BPF_JGE | BPF_K: /* (dst_reg >= imm) */ 1159 mask = 0xa000; /* jhe */ 1160 goto branch_ku; 1161 case BPF_JMP | BPF_JLE | BPF_K: /* (dst_reg <= imm) */ 1162 mask = 0xc000; /* jle */ 1163 goto branch_ku; 1164 case BPF_JMP | BPF_JNE | BPF_K: /* (dst_reg != imm) */ 1165 mask = 0x7000; /* jne */ 1166 goto branch_ku; 1167 case BPF_JMP | BPF_JEQ | BPF_K: /* (dst_reg == imm) */ 1168 mask = 0x8000; /* je */ 1169 goto branch_ku; 1170 case BPF_JMP | BPF_JSET | BPF_K: /* (dst_reg & imm) */ 1171 mask = 0x7000; /* jnz */ 1172 /* lgfi %w1,imm (load sign extend imm) */ 1173 EMIT6_IMM(0xc0010000, REG_W1, imm); 1174 /* ngr %w1,%dst */ 1175 EMIT4(0xb9800000, REG_W1, dst_reg); 1176 goto branch_oc; 1177 1178 case BPF_JMP | BPF_JSGT | BPF_X: /* ((s64) dst > (s64) src) */ 1179 mask = 0x2000; /* jh */ 1180 goto branch_xs; 1181 case BPF_JMP | BPF_JSLT | BPF_X: /* ((s64) dst < (s64) src) */ 1182 mask = 0x4000; /* jl */ 1183 goto branch_xs; 1184 case BPF_JMP | BPF_JSGE | BPF_X: /* ((s64) dst >= (s64) src) */ 1185 mask = 0xa000; /* jhe */ 1186 goto branch_xs; 1187 case BPF_JMP | BPF_JSLE | BPF_X: /* ((s64) dst <= (s64) src) */ 1188 mask = 0xc000; /* jle */ 1189 goto branch_xs; 1190 case BPF_JMP | BPF_JGT | BPF_X: /* (dst > src) */ 1191 mask = 0x2000; /* jh */ 1192 goto branch_xu; 1193 case BPF_JMP | BPF_JLT | BPF_X: /* (dst < src) */ 1194 mask = 0x4000; /* jl */ 1195 goto branch_xu; 1196 case BPF_JMP | BPF_JGE | BPF_X: /* (dst >= src) */ 1197 mask = 0xa000; /* jhe */ 1198 goto branch_xu; 1199 case BPF_JMP | BPF_JLE | BPF_X: /* (dst <= src) */ 1200 mask = 0xc000; /* jle */ 1201 goto branch_xu; 1202 case BPF_JMP | BPF_JNE | BPF_X: /* (dst != src) */ 1203 mask = 0x7000; /* jne */ 1204 goto branch_xu; 1205 case BPF_JMP | BPF_JEQ | BPF_X: /* (dst == src) */ 1206 mask = 0x8000; /* je */ 1207 goto branch_xu; 1208 case BPF_JMP | BPF_JSET | BPF_X: /* (dst & src) */ 1209 mask = 0x7000; /* jnz */ 1210 /* ngrk %w1,%dst,%src */ 1211 EMIT4_RRF(0xb9e40000, REG_W1, dst_reg, src_reg); 1212 goto branch_oc; 1213 branch_ks: 1214 /* lgfi %w1,imm (load sign extend imm) */ 1215 EMIT6_IMM(0xc0010000, REG_W1, imm); 1216 /* cgrj %dst,%w1,mask,off */ 1217 EMIT6_PCREL(0xec000000, 0x0064, dst_reg, REG_W1, i, off, mask); 1218 break; 1219 branch_ku: 1220 /* lgfi %w1,imm (load sign extend imm) */ 1221 EMIT6_IMM(0xc0010000, REG_W1, imm); 1222 /* clgrj %dst,%w1,mask,off */ 1223 EMIT6_PCREL(0xec000000, 0x0065, dst_reg, REG_W1, i, off, mask); 1224 break; 1225 branch_xs: 1226 /* cgrj %dst,%src,mask,off */ 1227 EMIT6_PCREL(0xec000000, 0x0064, dst_reg, src_reg, i, off, mask); 1228 break; 1229 branch_xu: 1230 /* clgrj %dst,%src,mask,off */ 1231 EMIT6_PCREL(0xec000000, 0x0065, dst_reg, src_reg, i, off, mask); 1232 break; 1233 branch_oc: 1234 /* brc mask,jmp_off (branch instruction needs 4 bytes) */ 1235 jmp_off = addrs[i + off + 1] - (addrs[i + 1] - 4); 1236 EMIT4_PCREL(0xa7040000 | mask << 8, jmp_off); 1237 break; 1238 /* 1239 * BPF_LD 1240 */ 1241 case BPF_LD | BPF_ABS | BPF_B: /* b0 = *(u8 *) (skb->data+imm) */ 1242 case BPF_LD | BPF_IND | BPF_B: /* b0 = *(u8 *) (skb->data+imm+src) */ 1243 if ((BPF_MODE(insn->code) == BPF_ABS) && (imm >= 0)) 1244 func_addr = __pa(sk_load_byte_pos); 1245 else 1246 func_addr = __pa(sk_load_byte); 1247 goto call_fn; 1248 case BPF_LD | BPF_ABS | BPF_H: /* b0 = *(u16 *) (skb->data+imm) */ 1249 case BPF_LD | BPF_IND | BPF_H: /* b0 = *(u16 *) (skb->data+imm+src) */ 1250 if ((BPF_MODE(insn->code) == BPF_ABS) && (imm >= 0)) 1251 func_addr = __pa(sk_load_half_pos); 1252 else 1253 func_addr = __pa(sk_load_half); 1254 goto call_fn; 1255 case BPF_LD | BPF_ABS | BPF_W: /* b0 = *(u32 *) (skb->data+imm) */ 1256 case BPF_LD | BPF_IND | BPF_W: /* b0 = *(u32 *) (skb->data+imm+src) */ 1257 if ((BPF_MODE(insn->code) == BPF_ABS) && (imm >= 0)) 1258 func_addr = __pa(sk_load_word_pos); 1259 else 1260 func_addr = __pa(sk_load_word); 1261 goto call_fn; 1262 call_fn: 1263 jit->seen |= SEEN_SKB | SEEN_RET0 | SEEN_FUNC; 1264 REG_SET_SEEN(REG_14); /* Return address of possible func call */ 1265 1266 /* 1267 * Implicit input: 1268 * BPF_REG_6 (R7) : skb pointer 1269 * REG_SKB_DATA (R12): skb data pointer (if no BPF_REG_AX) 1270 * 1271 * Calculated input: 1272 * BPF_REG_2 (R3) : offset of byte(s) to fetch in skb 1273 * BPF_REG_5 (R6) : return address 1274 * 1275 * Output: 1276 * BPF_REG_0 (R14): data read from skb 1277 * 1278 * Scratch registers (BPF_REG_1-5) 1279 */ 1280 1281 /* Call function: llilf %w1,func_addr */ 1282 EMIT6_IMM(0xc00f0000, REG_W1, func_addr); 1283 1284 /* Offset: lgfi %b2,imm */ 1285 EMIT6_IMM(0xc0010000, BPF_REG_2, imm); 1286 if (BPF_MODE(insn->code) == BPF_IND) 1287 /* agfr %b2,%src (%src is s32 here) */ 1288 EMIT4(0xb9180000, BPF_REG_2, src_reg); 1289 1290 /* Reload REG_SKB_DATA if BPF_REG_AX is used */ 1291 if (jit->seen & SEEN_REG_AX) 1292 /* lg %skb_data,data_off(%b6) */ 1293 EMIT6_DISP_LH(0xe3000000, 0x0004, REG_SKB_DATA, REG_0, 1294 BPF_REG_6, offsetof(struct sk_buff, data)); 1295 /* basr %b5,%w1 (%b5 is call saved) */ 1296 EMIT2(0x0d00, BPF_REG_5, REG_W1); 1297 1298 /* 1299 * Note: For fast access we jump directly after the 1300 * jnz instruction from bpf_jit.S 1301 */ 1302 /* jnz <ret0> */ 1303 EMIT4_PCREL(0xa7740000, jit->ret0_ip - jit->prg); 1304 break; 1305 default: /* too complex, give up */ 1306 pr_err("Unknown opcode %02x\n", insn->code); 1307 return -1; 1308 } 1309 return insn_count; 1310 } 1311 1312 /* 1313 * Compile eBPF program into s390x code 1314 */ 1315 static int bpf_jit_prog(struct bpf_jit *jit, struct bpf_prog *fp) 1316 { 1317 int i, insn_count; 1318 1319 jit->lit = jit->lit_start; 1320 jit->prg = 0; 1321 1322 bpf_jit_prologue(jit, fp->aux->stack_depth); 1323 for (i = 0; i < fp->len; i += insn_count) { 1324 insn_count = bpf_jit_insn(jit, fp, i); 1325 if (insn_count < 0) 1326 return -1; 1327 /* Next instruction address */ 1328 jit->addrs[i + insn_count] = jit->prg; 1329 } 1330 bpf_jit_epilogue(jit, fp->aux->stack_depth); 1331 1332 jit->lit_start = jit->prg; 1333 jit->size = jit->lit; 1334 jit->size_prg = jit->prg; 1335 return 0; 1336 } 1337 1338 /* 1339 * Compile eBPF program "fp" 1340 */ 1341 struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *fp) 1342 { 1343 struct bpf_prog *tmp, *orig_fp = fp; 1344 struct bpf_binary_header *header; 1345 bool tmp_blinded = false; 1346 struct bpf_jit jit; 1347 int pass; 1348 1349 if (!fp->jit_requested) 1350 return orig_fp; 1351 1352 tmp = bpf_jit_blind_constants(fp); 1353 /* 1354 * If blinding was requested and we failed during blinding, 1355 * we must fall back to the interpreter. 1356 */ 1357 if (IS_ERR(tmp)) 1358 return orig_fp; 1359 if (tmp != fp) { 1360 tmp_blinded = true; 1361 fp = tmp; 1362 } 1363 1364 memset(&jit, 0, sizeof(jit)); 1365 jit.addrs = kcalloc(fp->len + 1, sizeof(*jit.addrs), GFP_KERNEL); 1366 if (jit.addrs == NULL) { 1367 fp = orig_fp; 1368 goto out; 1369 } 1370 /* 1371 * Three initial passes: 1372 * - 1/2: Determine clobbered registers 1373 * - 3: Calculate program size and addrs arrray 1374 */ 1375 for (pass = 1; pass <= 3; pass++) { 1376 if (bpf_jit_prog(&jit, fp)) { 1377 fp = orig_fp; 1378 goto free_addrs; 1379 } 1380 } 1381 /* 1382 * Final pass: Allocate and generate program 1383 */ 1384 if (jit.size >= BPF_SIZE_MAX) { 1385 fp = orig_fp; 1386 goto free_addrs; 1387 } 1388 header = bpf_jit_binary_alloc(jit.size, &jit.prg_buf, 2, jit_fill_hole); 1389 if (!header) { 1390 fp = orig_fp; 1391 goto free_addrs; 1392 } 1393 if (bpf_jit_prog(&jit, fp)) { 1394 fp = orig_fp; 1395 goto free_addrs; 1396 } 1397 if (bpf_jit_enable > 1) { 1398 bpf_jit_dump(fp->len, jit.size, pass, jit.prg_buf); 1399 print_fn_code(jit.prg_buf, jit.size_prg); 1400 } 1401 bpf_jit_binary_lock_ro(header); 1402 fp->bpf_func = (void *) jit.prg_buf; 1403 fp->jited = 1; 1404 fp->jited_len = jit.size; 1405 free_addrs: 1406 kfree(jit.addrs); 1407 out: 1408 if (tmp_blinded) 1409 bpf_jit_prog_release_other(fp, fp == orig_fp ? 1410 tmp : orig_fp); 1411 return fp; 1412 } 1413