1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * BPF Jit compiler for s390. 4 * 5 * Minimum build requirements: 6 * 7 * - HAVE_MARCH_Z196_FEATURES: laal, laalg 8 * - HAVE_MARCH_Z10_FEATURES: msfi, cgrj, clgrj 9 * - HAVE_MARCH_Z9_109_FEATURES: alfi, llilf, clfi, oilf, nilf 10 * - PACK_STACK 11 * - 64BIT 12 * 13 * Copyright IBM Corp. 2012,2015 14 * 15 * Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com> 16 * Michael Holzheu <holzheu@linux.vnet.ibm.com> 17 */ 18 19 #define KMSG_COMPONENT "bpf_jit" 20 #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt 21 22 #include <linux/netdevice.h> 23 #include <linux/filter.h> 24 #include <linux/init.h> 25 #include <linux/bpf.h> 26 #include <linux/mm.h> 27 #include <linux/kernel.h> 28 #include <asm/cacheflush.h> 29 #include <asm/dis.h> 30 #include <asm/facility.h> 31 #include <asm/nospec-branch.h> 32 #include <asm/set_memory.h> 33 #include "bpf_jit.h" 34 35 struct bpf_jit { 36 u32 seen; /* Flags to remember seen eBPF instructions */ 37 u32 seen_reg[16]; /* Array to remember which registers are used */ 38 u32 *addrs; /* Array with relative instruction addresses */ 39 u8 *prg_buf; /* Start of program */ 40 int size; /* Size of program and literal pool */ 41 int size_prg; /* Size of program */ 42 int prg; /* Current position in program */ 43 int lit32_start; /* Start of 32-bit literal pool */ 44 int lit32; /* Current position in 32-bit literal pool */ 45 int lit64_start; /* Start of 64-bit literal pool */ 46 int lit64; /* Current position in 64-bit literal pool */ 47 int base_ip; /* Base address for literal pool */ 48 int exit_ip; /* Address of exit */ 49 int r1_thunk_ip; /* Address of expoline thunk for 'br %r1' */ 50 int r14_thunk_ip; /* Address of expoline thunk for 'br %r14' */ 51 int tail_call_start; /* Tail call start offset */ 52 int excnt; /* Number of exception table entries */ 53 int labels[1]; /* Labels for local jumps */ 54 }; 55 56 #define SEEN_MEM BIT(0) /* use mem[] for temporary storage */ 57 #define SEEN_LITERAL BIT(1) /* code uses literals */ 58 #define SEEN_FUNC BIT(2) /* calls C functions */ 59 #define SEEN_TAIL_CALL BIT(3) /* code uses tail calls */ 60 #define SEEN_STACK (SEEN_FUNC | SEEN_MEM) 61 62 /* 63 * s390 registers 64 */ 65 #define REG_W0 (MAX_BPF_JIT_REG + 0) /* Work register 1 (even) */ 66 #define REG_W1 (MAX_BPF_JIT_REG + 1) /* Work register 2 (odd) */ 67 #define REG_L (MAX_BPF_JIT_REG + 2) /* Literal pool register */ 68 #define REG_15 (MAX_BPF_JIT_REG + 3) /* Register 15 */ 69 #define REG_0 REG_W0 /* Register 0 */ 70 #define REG_1 REG_W1 /* Register 1 */ 71 #define REG_2 BPF_REG_1 /* Register 2 */ 72 #define REG_14 BPF_REG_0 /* Register 14 */ 73 74 /* 75 * Mapping of BPF registers to s390 registers 76 */ 77 static const int reg2hex[] = { 78 /* Return code */ 79 [BPF_REG_0] = 14, 80 /* Function parameters */ 81 [BPF_REG_1] = 2, 82 [BPF_REG_2] = 3, 83 [BPF_REG_3] = 4, 84 [BPF_REG_4] = 5, 85 [BPF_REG_5] = 6, 86 /* Call saved registers */ 87 [BPF_REG_6] = 7, 88 [BPF_REG_7] = 8, 89 [BPF_REG_8] = 9, 90 [BPF_REG_9] = 10, 91 /* BPF stack pointer */ 92 [BPF_REG_FP] = 13, 93 /* Register for blinding */ 94 [BPF_REG_AX] = 12, 95 /* Work registers for s390x backend */ 96 [REG_W0] = 0, 97 [REG_W1] = 1, 98 [REG_L] = 11, 99 [REG_15] = 15, 100 }; 101 102 static inline u32 reg(u32 dst_reg, u32 src_reg) 103 { 104 return reg2hex[dst_reg] << 4 | reg2hex[src_reg]; 105 } 106 107 static inline u32 reg_high(u32 reg) 108 { 109 return reg2hex[reg] << 4; 110 } 111 112 static inline void reg_set_seen(struct bpf_jit *jit, u32 b1) 113 { 114 u32 r1 = reg2hex[b1]; 115 116 if (!jit->seen_reg[r1] && r1 >= 6 && r1 <= 15) 117 jit->seen_reg[r1] = 1; 118 } 119 120 #define REG_SET_SEEN(b1) \ 121 ({ \ 122 reg_set_seen(jit, b1); \ 123 }) 124 125 #define REG_SEEN(b1) jit->seen_reg[reg2hex[(b1)]] 126 127 /* 128 * EMIT macros for code generation 129 */ 130 131 #define _EMIT2(op) \ 132 ({ \ 133 if (jit->prg_buf) \ 134 *(u16 *) (jit->prg_buf + jit->prg) = (op); \ 135 jit->prg += 2; \ 136 }) 137 138 #define EMIT2(op, b1, b2) \ 139 ({ \ 140 _EMIT2((op) | reg(b1, b2)); \ 141 REG_SET_SEEN(b1); \ 142 REG_SET_SEEN(b2); \ 143 }) 144 145 #define _EMIT4(op) \ 146 ({ \ 147 if (jit->prg_buf) \ 148 *(u32 *) (jit->prg_buf + jit->prg) = (op); \ 149 jit->prg += 4; \ 150 }) 151 152 #define EMIT4(op, b1, b2) \ 153 ({ \ 154 _EMIT4((op) | reg(b1, b2)); \ 155 REG_SET_SEEN(b1); \ 156 REG_SET_SEEN(b2); \ 157 }) 158 159 #define EMIT4_RRF(op, b1, b2, b3) \ 160 ({ \ 161 _EMIT4((op) | reg_high(b3) << 8 | reg(b1, b2)); \ 162 REG_SET_SEEN(b1); \ 163 REG_SET_SEEN(b2); \ 164 REG_SET_SEEN(b3); \ 165 }) 166 167 #define _EMIT4_DISP(op, disp) \ 168 ({ \ 169 unsigned int __disp = (disp) & 0xfff; \ 170 _EMIT4((op) | __disp); \ 171 }) 172 173 #define EMIT4_DISP(op, b1, b2, disp) \ 174 ({ \ 175 _EMIT4_DISP((op) | reg_high(b1) << 16 | \ 176 reg_high(b2) << 8, (disp)); \ 177 REG_SET_SEEN(b1); \ 178 REG_SET_SEEN(b2); \ 179 }) 180 181 #define EMIT4_IMM(op, b1, imm) \ 182 ({ \ 183 unsigned int __imm = (imm) & 0xffff; \ 184 _EMIT4((op) | reg_high(b1) << 16 | __imm); \ 185 REG_SET_SEEN(b1); \ 186 }) 187 188 #define EMIT4_PCREL(op, pcrel) \ 189 ({ \ 190 long __pcrel = ((pcrel) >> 1) & 0xffff; \ 191 _EMIT4((op) | __pcrel); \ 192 }) 193 194 #define EMIT4_PCREL_RIC(op, mask, target) \ 195 ({ \ 196 int __rel = ((target) - jit->prg) / 2; \ 197 _EMIT4((op) | (mask) << 20 | (__rel & 0xffff)); \ 198 }) 199 200 #define _EMIT6(op1, op2) \ 201 ({ \ 202 if (jit->prg_buf) { \ 203 *(u32 *) (jit->prg_buf + jit->prg) = (op1); \ 204 *(u16 *) (jit->prg_buf + jit->prg + 4) = (op2); \ 205 } \ 206 jit->prg += 6; \ 207 }) 208 209 #define _EMIT6_DISP(op1, op2, disp) \ 210 ({ \ 211 unsigned int __disp = (disp) & 0xfff; \ 212 _EMIT6((op1) | __disp, op2); \ 213 }) 214 215 #define _EMIT6_DISP_LH(op1, op2, disp) \ 216 ({ \ 217 u32 _disp = (u32) (disp); \ 218 unsigned int __disp_h = _disp & 0xff000; \ 219 unsigned int __disp_l = _disp & 0x00fff; \ 220 _EMIT6((op1) | __disp_l, (op2) | __disp_h >> 4); \ 221 }) 222 223 #define EMIT6_DISP_LH(op1, op2, b1, b2, b3, disp) \ 224 ({ \ 225 _EMIT6_DISP_LH((op1) | reg(b1, b2) << 16 | \ 226 reg_high(b3) << 8, op2, disp); \ 227 REG_SET_SEEN(b1); \ 228 REG_SET_SEEN(b2); \ 229 REG_SET_SEEN(b3); \ 230 }) 231 232 #define EMIT6_PCREL_LABEL(op1, op2, b1, b2, label, mask) \ 233 ({ \ 234 int rel = (jit->labels[label] - jit->prg) >> 1; \ 235 _EMIT6((op1) | reg(b1, b2) << 16 | (rel & 0xffff), \ 236 (op2) | (mask) << 12); \ 237 REG_SET_SEEN(b1); \ 238 REG_SET_SEEN(b2); \ 239 }) 240 241 #define EMIT6_PCREL_IMM_LABEL(op1, op2, b1, imm, label, mask) \ 242 ({ \ 243 int rel = (jit->labels[label] - jit->prg) >> 1; \ 244 _EMIT6((op1) | (reg_high(b1) | (mask)) << 16 | \ 245 (rel & 0xffff), (op2) | ((imm) & 0xff) << 8); \ 246 REG_SET_SEEN(b1); \ 247 BUILD_BUG_ON(((unsigned long) (imm)) > 0xff); \ 248 }) 249 250 #define EMIT6_PCREL(op1, op2, b1, b2, i, off, mask) \ 251 ({ \ 252 /* Branch instruction needs 6 bytes */ \ 253 int rel = (addrs[(i) + (off) + 1] - (addrs[(i) + 1] - 6)) / 2;\ 254 _EMIT6((op1) | reg(b1, b2) << 16 | (rel & 0xffff), (op2) | (mask));\ 255 REG_SET_SEEN(b1); \ 256 REG_SET_SEEN(b2); \ 257 }) 258 259 #define EMIT6_PCREL_RILB(op, b, target) \ 260 ({ \ 261 unsigned int rel = (int)((target) - jit->prg) / 2; \ 262 _EMIT6((op) | reg_high(b) << 16 | rel >> 16, rel & 0xffff);\ 263 REG_SET_SEEN(b); \ 264 }) 265 266 #define EMIT6_PCREL_RIL(op, target) \ 267 ({ \ 268 unsigned int rel = (int)((target) - jit->prg) / 2; \ 269 _EMIT6((op) | rel >> 16, rel & 0xffff); \ 270 }) 271 272 #define EMIT6_PCREL_RILC(op, mask, target) \ 273 ({ \ 274 EMIT6_PCREL_RIL((op) | (mask) << 20, (target)); \ 275 }) 276 277 #define _EMIT6_IMM(op, imm) \ 278 ({ \ 279 unsigned int __imm = (imm); \ 280 _EMIT6((op) | (__imm >> 16), __imm & 0xffff); \ 281 }) 282 283 #define EMIT6_IMM(op, b1, imm) \ 284 ({ \ 285 _EMIT6_IMM((op) | reg_high(b1) << 16, imm); \ 286 REG_SET_SEEN(b1); \ 287 }) 288 289 #define _EMIT_CONST_U32(val) \ 290 ({ \ 291 unsigned int ret; \ 292 ret = jit->lit32; \ 293 if (jit->prg_buf) \ 294 *(u32 *)(jit->prg_buf + jit->lit32) = (u32)(val);\ 295 jit->lit32 += 4; \ 296 ret; \ 297 }) 298 299 #define EMIT_CONST_U32(val) \ 300 ({ \ 301 jit->seen |= SEEN_LITERAL; \ 302 _EMIT_CONST_U32(val) - jit->base_ip; \ 303 }) 304 305 #define _EMIT_CONST_U64(val) \ 306 ({ \ 307 unsigned int ret; \ 308 ret = jit->lit64; \ 309 if (jit->prg_buf) \ 310 *(u64 *)(jit->prg_buf + jit->lit64) = (u64)(val);\ 311 jit->lit64 += 8; \ 312 ret; \ 313 }) 314 315 #define EMIT_CONST_U64(val) \ 316 ({ \ 317 jit->seen |= SEEN_LITERAL; \ 318 _EMIT_CONST_U64(val) - jit->base_ip; \ 319 }) 320 321 #define EMIT_ZERO(b1) \ 322 ({ \ 323 if (!fp->aux->verifier_zext) { \ 324 /* llgfr %dst,%dst (zero extend to 64 bit) */ \ 325 EMIT4(0xb9160000, b1, b1); \ 326 REG_SET_SEEN(b1); \ 327 } \ 328 }) 329 330 /* 331 * Return whether this is the first pass. The first pass is special, since we 332 * don't know any sizes yet, and thus must be conservative. 333 */ 334 static bool is_first_pass(struct bpf_jit *jit) 335 { 336 return jit->size == 0; 337 } 338 339 /* 340 * Return whether this is the code generation pass. The code generation pass is 341 * special, since we should change as little as possible. 342 */ 343 static bool is_codegen_pass(struct bpf_jit *jit) 344 { 345 return jit->prg_buf; 346 } 347 348 /* 349 * Return whether "rel" can be encoded as a short PC-relative offset 350 */ 351 static bool is_valid_rel(int rel) 352 { 353 return rel >= -65536 && rel <= 65534; 354 } 355 356 /* 357 * Return whether "off" can be reached using a short PC-relative offset 358 */ 359 static bool can_use_rel(struct bpf_jit *jit, int off) 360 { 361 return is_valid_rel(off - jit->prg); 362 } 363 364 /* 365 * Return whether given displacement can be encoded using 366 * Long-Displacement Facility 367 */ 368 static bool is_valid_ldisp(int disp) 369 { 370 return disp >= -524288 && disp <= 524287; 371 } 372 373 /* 374 * Return whether the next 32-bit literal pool entry can be referenced using 375 * Long-Displacement Facility 376 */ 377 static bool can_use_ldisp_for_lit32(struct bpf_jit *jit) 378 { 379 return is_valid_ldisp(jit->lit32 - jit->base_ip); 380 } 381 382 /* 383 * Return whether the next 64-bit literal pool entry can be referenced using 384 * Long-Displacement Facility 385 */ 386 static bool can_use_ldisp_for_lit64(struct bpf_jit *jit) 387 { 388 return is_valid_ldisp(jit->lit64 - jit->base_ip); 389 } 390 391 /* 392 * Fill whole space with illegal instructions 393 */ 394 static void jit_fill_hole(void *area, unsigned int size) 395 { 396 memset(area, 0, size); 397 } 398 399 /* 400 * Save registers from "rs" (register start) to "re" (register end) on stack 401 */ 402 static void save_regs(struct bpf_jit *jit, u32 rs, u32 re) 403 { 404 u32 off = STK_OFF_R6 + (rs - 6) * 8; 405 406 if (rs == re) 407 /* stg %rs,off(%r15) */ 408 _EMIT6(0xe300f000 | rs << 20 | off, 0x0024); 409 else 410 /* stmg %rs,%re,off(%r15) */ 411 _EMIT6_DISP(0xeb00f000 | rs << 20 | re << 16, 0x0024, off); 412 } 413 414 /* 415 * Restore registers from "rs" (register start) to "re" (register end) on stack 416 */ 417 static void restore_regs(struct bpf_jit *jit, u32 rs, u32 re, u32 stack_depth) 418 { 419 u32 off = STK_OFF_R6 + (rs - 6) * 8; 420 421 if (jit->seen & SEEN_STACK) 422 off += STK_OFF + stack_depth; 423 424 if (rs == re) 425 /* lg %rs,off(%r15) */ 426 _EMIT6(0xe300f000 | rs << 20 | off, 0x0004); 427 else 428 /* lmg %rs,%re,off(%r15) */ 429 _EMIT6_DISP(0xeb00f000 | rs << 20 | re << 16, 0x0004, off); 430 } 431 432 /* 433 * Return first seen register (from start) 434 */ 435 static int get_start(struct bpf_jit *jit, int start) 436 { 437 int i; 438 439 for (i = start; i <= 15; i++) { 440 if (jit->seen_reg[i]) 441 return i; 442 } 443 return 0; 444 } 445 446 /* 447 * Return last seen register (from start) (gap >= 2) 448 */ 449 static int get_end(struct bpf_jit *jit, int start) 450 { 451 int i; 452 453 for (i = start; i < 15; i++) { 454 if (!jit->seen_reg[i] && !jit->seen_reg[i + 1]) 455 return i - 1; 456 } 457 return jit->seen_reg[15] ? 15 : 14; 458 } 459 460 #define REGS_SAVE 1 461 #define REGS_RESTORE 0 462 /* 463 * Save and restore clobbered registers (6-15) on stack. 464 * We save/restore registers in chunks with gap >= 2 registers. 465 */ 466 static void save_restore_regs(struct bpf_jit *jit, int op, u32 stack_depth) 467 { 468 const int last = 15, save_restore_size = 6; 469 int re = 6, rs; 470 471 if (is_first_pass(jit)) { 472 /* 473 * We don't know yet which registers are used. Reserve space 474 * conservatively. 475 */ 476 jit->prg += (last - re + 1) * save_restore_size; 477 return; 478 } 479 480 do { 481 rs = get_start(jit, re); 482 if (!rs) 483 break; 484 re = get_end(jit, rs + 1); 485 if (op == REGS_SAVE) 486 save_regs(jit, rs, re); 487 else 488 restore_regs(jit, rs, re, stack_depth); 489 re++; 490 } while (re <= last); 491 } 492 493 /* 494 * Emit function prologue 495 * 496 * Save registers and create stack frame if necessary. 497 * See stack frame layout desription in "bpf_jit.h"! 498 */ 499 static void bpf_jit_prologue(struct bpf_jit *jit, u32 stack_depth) 500 { 501 if (jit->seen & SEEN_TAIL_CALL) { 502 /* xc STK_OFF_TCCNT(4,%r15),STK_OFF_TCCNT(%r15) */ 503 _EMIT6(0xd703f000 | STK_OFF_TCCNT, 0xf000 | STK_OFF_TCCNT); 504 } else { 505 /* j tail_call_start: NOP if no tail calls are used */ 506 EMIT4_PCREL(0xa7f40000, 6); 507 /* bcr 0,%0 */ 508 EMIT2(0x0700, 0, REG_0); 509 } 510 /* Tail calls have to skip above initialization */ 511 jit->tail_call_start = jit->prg; 512 /* Save registers */ 513 save_restore_regs(jit, REGS_SAVE, stack_depth); 514 /* Setup literal pool */ 515 if (is_first_pass(jit) || (jit->seen & SEEN_LITERAL)) { 516 if (!is_first_pass(jit) && 517 is_valid_ldisp(jit->size - (jit->prg + 2))) { 518 /* basr %l,0 */ 519 EMIT2(0x0d00, REG_L, REG_0); 520 jit->base_ip = jit->prg; 521 } else { 522 /* larl %l,lit32_start */ 523 EMIT6_PCREL_RILB(0xc0000000, REG_L, jit->lit32_start); 524 jit->base_ip = jit->lit32_start; 525 } 526 } 527 /* Setup stack and backchain */ 528 if (is_first_pass(jit) || (jit->seen & SEEN_STACK)) { 529 if (is_first_pass(jit) || (jit->seen & SEEN_FUNC)) 530 /* lgr %w1,%r15 (backchain) */ 531 EMIT4(0xb9040000, REG_W1, REG_15); 532 /* la %bfp,STK_160_UNUSED(%r15) (BPF frame pointer) */ 533 EMIT4_DISP(0x41000000, BPF_REG_FP, REG_15, STK_160_UNUSED); 534 /* aghi %r15,-STK_OFF */ 535 EMIT4_IMM(0xa70b0000, REG_15, -(STK_OFF + stack_depth)); 536 if (is_first_pass(jit) || (jit->seen & SEEN_FUNC)) 537 /* stg %w1,152(%r15) (backchain) */ 538 EMIT6_DISP_LH(0xe3000000, 0x0024, REG_W1, REG_0, 539 REG_15, 152); 540 } 541 } 542 543 /* 544 * Function epilogue 545 */ 546 static void bpf_jit_epilogue(struct bpf_jit *jit, u32 stack_depth) 547 { 548 jit->exit_ip = jit->prg; 549 /* Load exit code: lgr %r2,%b0 */ 550 EMIT4(0xb9040000, REG_2, BPF_REG_0); 551 /* Restore registers */ 552 save_restore_regs(jit, REGS_RESTORE, stack_depth); 553 if (__is_defined(CC_USING_EXPOLINE) && !nospec_disable) { 554 jit->r14_thunk_ip = jit->prg; 555 /* Generate __s390_indirect_jump_r14 thunk */ 556 if (test_facility(35)) { 557 /* exrl %r0,.+10 */ 558 EMIT6_PCREL_RIL(0xc6000000, jit->prg + 10); 559 } else { 560 /* larl %r1,.+14 */ 561 EMIT6_PCREL_RILB(0xc0000000, REG_1, jit->prg + 14); 562 /* ex 0,0(%r1) */ 563 EMIT4_DISP(0x44000000, REG_0, REG_1, 0); 564 } 565 /* j . */ 566 EMIT4_PCREL(0xa7f40000, 0); 567 } 568 /* br %r14 */ 569 _EMIT2(0x07fe); 570 571 if (__is_defined(CC_USING_EXPOLINE) && !nospec_disable && 572 (is_first_pass(jit) || (jit->seen & SEEN_FUNC))) { 573 jit->r1_thunk_ip = jit->prg; 574 /* Generate __s390_indirect_jump_r1 thunk */ 575 if (test_facility(35)) { 576 /* exrl %r0,.+10 */ 577 EMIT6_PCREL_RIL(0xc6000000, jit->prg + 10); 578 /* j . */ 579 EMIT4_PCREL(0xa7f40000, 0); 580 /* br %r1 */ 581 _EMIT2(0x07f1); 582 } else { 583 /* ex 0,S390_lowcore.br_r1_tampoline */ 584 EMIT4_DISP(0x44000000, REG_0, REG_0, 585 offsetof(struct lowcore, br_r1_trampoline)); 586 /* j . */ 587 EMIT4_PCREL(0xa7f40000, 0); 588 } 589 } 590 } 591 592 static int get_probe_mem_regno(const u8 *insn) 593 { 594 /* 595 * insn must point to llgc, llgh, llgf or lg, which have destination 596 * register at the same position. 597 */ 598 if (insn[0] != 0xe3) /* common llgc, llgh, llgf and lg prefix */ 599 return -1; 600 if (insn[5] != 0x90 && /* llgc */ 601 insn[5] != 0x91 && /* llgh */ 602 insn[5] != 0x16 && /* llgf */ 603 insn[5] != 0x04) /* lg */ 604 return -1; 605 return insn[1] >> 4; 606 } 607 608 static bool ex_handler_bpf(const struct exception_table_entry *x, 609 struct pt_regs *regs) 610 { 611 int regno; 612 u8 *insn; 613 614 regs->psw.addr = extable_fixup(x); 615 insn = (u8 *)__rewind_psw(regs->psw, regs->int_code >> 16); 616 regno = get_probe_mem_regno(insn); 617 if (WARN_ON_ONCE(regno < 0)) 618 /* JIT bug - unexpected instruction. */ 619 return false; 620 regs->gprs[regno] = 0; 621 return true; 622 } 623 624 static int bpf_jit_probe_mem(struct bpf_jit *jit, struct bpf_prog *fp, 625 int probe_prg, int nop_prg) 626 { 627 struct exception_table_entry *ex; 628 s64 delta; 629 u8 *insn; 630 int prg; 631 int i; 632 633 if (!fp->aux->extable) 634 /* Do nothing during early JIT passes. */ 635 return 0; 636 insn = jit->prg_buf + probe_prg; 637 if (WARN_ON_ONCE(get_probe_mem_regno(insn) < 0)) 638 /* JIT bug - unexpected probe instruction. */ 639 return -1; 640 if (WARN_ON_ONCE(probe_prg + insn_length(*insn) != nop_prg)) 641 /* JIT bug - gap between probe and nop instructions. */ 642 return -1; 643 for (i = 0; i < 2; i++) { 644 if (WARN_ON_ONCE(jit->excnt >= fp->aux->num_exentries)) 645 /* Verifier bug - not enough entries. */ 646 return -1; 647 ex = &fp->aux->extable[jit->excnt]; 648 /* Add extable entries for probe and nop instructions. */ 649 prg = i == 0 ? probe_prg : nop_prg; 650 delta = jit->prg_buf + prg - (u8 *)&ex->insn; 651 if (WARN_ON_ONCE(delta < INT_MIN || delta > INT_MAX)) 652 /* JIT bug - code and extable must be close. */ 653 return -1; 654 ex->insn = delta; 655 /* 656 * Always land on the nop. Note that extable infrastructure 657 * ignores fixup field, it is handled by ex_handler_bpf(). 658 */ 659 delta = jit->prg_buf + nop_prg - (u8 *)&ex->fixup; 660 if (WARN_ON_ONCE(delta < INT_MIN || delta > INT_MAX)) 661 /* JIT bug - landing pad and extable must be close. */ 662 return -1; 663 ex->fixup = delta; 664 ex->handler = (u8 *)ex_handler_bpf - (u8 *)&ex->handler; 665 jit->excnt++; 666 } 667 return 0; 668 } 669 670 /* 671 * Compile one eBPF instruction into s390x code 672 * 673 * NOTE: Use noinline because for gcov (-fprofile-arcs) gcc allocates a lot of 674 * stack space for the large switch statement. 675 */ 676 static noinline int bpf_jit_insn(struct bpf_jit *jit, struct bpf_prog *fp, 677 int i, bool extra_pass, u32 stack_depth) 678 { 679 struct bpf_insn *insn = &fp->insnsi[i]; 680 u32 dst_reg = insn->dst_reg; 681 u32 src_reg = insn->src_reg; 682 int last, insn_count = 1; 683 u32 *addrs = jit->addrs; 684 s32 imm = insn->imm; 685 s16 off = insn->off; 686 int probe_prg = -1; 687 unsigned int mask; 688 int nop_prg; 689 int err; 690 691 if (BPF_CLASS(insn->code) == BPF_LDX && 692 BPF_MODE(insn->code) == BPF_PROBE_MEM) 693 probe_prg = jit->prg; 694 695 switch (insn->code) { 696 /* 697 * BPF_MOV 698 */ 699 case BPF_ALU | BPF_MOV | BPF_X: /* dst = (u32) src */ 700 /* llgfr %dst,%src */ 701 EMIT4(0xb9160000, dst_reg, src_reg); 702 if (insn_is_zext(&insn[1])) 703 insn_count = 2; 704 break; 705 case BPF_ALU64 | BPF_MOV | BPF_X: /* dst = src */ 706 /* lgr %dst,%src */ 707 EMIT4(0xb9040000, dst_reg, src_reg); 708 break; 709 case BPF_ALU | BPF_MOV | BPF_K: /* dst = (u32) imm */ 710 /* llilf %dst,imm */ 711 EMIT6_IMM(0xc00f0000, dst_reg, imm); 712 if (insn_is_zext(&insn[1])) 713 insn_count = 2; 714 break; 715 case BPF_ALU64 | BPF_MOV | BPF_K: /* dst = imm */ 716 /* lgfi %dst,imm */ 717 EMIT6_IMM(0xc0010000, dst_reg, imm); 718 break; 719 /* 720 * BPF_LD 64 721 */ 722 case BPF_LD | BPF_IMM | BPF_DW: /* dst = (u64) imm */ 723 { 724 /* 16 byte instruction that uses two 'struct bpf_insn' */ 725 u64 imm64; 726 727 imm64 = (u64)(u32) insn[0].imm | ((u64)(u32) insn[1].imm) << 32; 728 /* lgrl %dst,imm */ 729 EMIT6_PCREL_RILB(0xc4080000, dst_reg, _EMIT_CONST_U64(imm64)); 730 insn_count = 2; 731 break; 732 } 733 /* 734 * BPF_ADD 735 */ 736 case BPF_ALU | BPF_ADD | BPF_X: /* dst = (u32) dst + (u32) src */ 737 /* ar %dst,%src */ 738 EMIT2(0x1a00, dst_reg, src_reg); 739 EMIT_ZERO(dst_reg); 740 break; 741 case BPF_ALU64 | BPF_ADD | BPF_X: /* dst = dst + src */ 742 /* agr %dst,%src */ 743 EMIT4(0xb9080000, dst_reg, src_reg); 744 break; 745 case BPF_ALU | BPF_ADD | BPF_K: /* dst = (u32) dst + (u32) imm */ 746 if (!imm) 747 break; 748 /* alfi %dst,imm */ 749 EMIT6_IMM(0xc20b0000, dst_reg, imm); 750 EMIT_ZERO(dst_reg); 751 break; 752 case BPF_ALU64 | BPF_ADD | BPF_K: /* dst = dst + imm */ 753 if (!imm) 754 break; 755 /* agfi %dst,imm */ 756 EMIT6_IMM(0xc2080000, dst_reg, imm); 757 break; 758 /* 759 * BPF_SUB 760 */ 761 case BPF_ALU | BPF_SUB | BPF_X: /* dst = (u32) dst - (u32) src */ 762 /* sr %dst,%src */ 763 EMIT2(0x1b00, dst_reg, src_reg); 764 EMIT_ZERO(dst_reg); 765 break; 766 case BPF_ALU64 | BPF_SUB | BPF_X: /* dst = dst - src */ 767 /* sgr %dst,%src */ 768 EMIT4(0xb9090000, dst_reg, src_reg); 769 break; 770 case BPF_ALU | BPF_SUB | BPF_K: /* dst = (u32) dst - (u32) imm */ 771 if (!imm) 772 break; 773 /* alfi %dst,-imm */ 774 EMIT6_IMM(0xc20b0000, dst_reg, -imm); 775 EMIT_ZERO(dst_reg); 776 break; 777 case BPF_ALU64 | BPF_SUB | BPF_K: /* dst = dst - imm */ 778 if (!imm) 779 break; 780 /* agfi %dst,-imm */ 781 EMIT6_IMM(0xc2080000, dst_reg, -imm); 782 break; 783 /* 784 * BPF_MUL 785 */ 786 case BPF_ALU | BPF_MUL | BPF_X: /* dst = (u32) dst * (u32) src */ 787 /* msr %dst,%src */ 788 EMIT4(0xb2520000, dst_reg, src_reg); 789 EMIT_ZERO(dst_reg); 790 break; 791 case BPF_ALU64 | BPF_MUL | BPF_X: /* dst = dst * src */ 792 /* msgr %dst,%src */ 793 EMIT4(0xb90c0000, dst_reg, src_reg); 794 break; 795 case BPF_ALU | BPF_MUL | BPF_K: /* dst = (u32) dst * (u32) imm */ 796 if (imm == 1) 797 break; 798 /* msfi %r5,imm */ 799 EMIT6_IMM(0xc2010000, dst_reg, imm); 800 EMIT_ZERO(dst_reg); 801 break; 802 case BPF_ALU64 | BPF_MUL | BPF_K: /* dst = dst * imm */ 803 if (imm == 1) 804 break; 805 /* msgfi %dst,imm */ 806 EMIT6_IMM(0xc2000000, dst_reg, imm); 807 break; 808 /* 809 * BPF_DIV / BPF_MOD 810 */ 811 case BPF_ALU | BPF_DIV | BPF_X: /* dst = (u32) dst / (u32) src */ 812 case BPF_ALU | BPF_MOD | BPF_X: /* dst = (u32) dst % (u32) src */ 813 { 814 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0; 815 816 /* lhi %w0,0 */ 817 EMIT4_IMM(0xa7080000, REG_W0, 0); 818 /* lr %w1,%dst */ 819 EMIT2(0x1800, REG_W1, dst_reg); 820 /* dlr %w0,%src */ 821 EMIT4(0xb9970000, REG_W0, src_reg); 822 /* llgfr %dst,%rc */ 823 EMIT4(0xb9160000, dst_reg, rc_reg); 824 if (insn_is_zext(&insn[1])) 825 insn_count = 2; 826 break; 827 } 828 case BPF_ALU64 | BPF_DIV | BPF_X: /* dst = dst / src */ 829 case BPF_ALU64 | BPF_MOD | BPF_X: /* dst = dst % src */ 830 { 831 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0; 832 833 /* lghi %w0,0 */ 834 EMIT4_IMM(0xa7090000, REG_W0, 0); 835 /* lgr %w1,%dst */ 836 EMIT4(0xb9040000, REG_W1, dst_reg); 837 /* dlgr %w0,%dst */ 838 EMIT4(0xb9870000, REG_W0, src_reg); 839 /* lgr %dst,%rc */ 840 EMIT4(0xb9040000, dst_reg, rc_reg); 841 break; 842 } 843 case BPF_ALU | BPF_DIV | BPF_K: /* dst = (u32) dst / (u32) imm */ 844 case BPF_ALU | BPF_MOD | BPF_K: /* dst = (u32) dst % (u32) imm */ 845 { 846 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0; 847 848 if (imm == 1) { 849 if (BPF_OP(insn->code) == BPF_MOD) 850 /* lhgi %dst,0 */ 851 EMIT4_IMM(0xa7090000, dst_reg, 0); 852 break; 853 } 854 /* lhi %w0,0 */ 855 EMIT4_IMM(0xa7080000, REG_W0, 0); 856 /* lr %w1,%dst */ 857 EMIT2(0x1800, REG_W1, dst_reg); 858 if (!is_first_pass(jit) && can_use_ldisp_for_lit32(jit)) { 859 /* dl %w0,<d(imm)>(%l) */ 860 EMIT6_DISP_LH(0xe3000000, 0x0097, REG_W0, REG_0, REG_L, 861 EMIT_CONST_U32(imm)); 862 } else { 863 /* lgfrl %dst,imm */ 864 EMIT6_PCREL_RILB(0xc40c0000, dst_reg, 865 _EMIT_CONST_U32(imm)); 866 jit->seen |= SEEN_LITERAL; 867 /* dlr %w0,%dst */ 868 EMIT4(0xb9970000, REG_W0, dst_reg); 869 } 870 /* llgfr %dst,%rc */ 871 EMIT4(0xb9160000, dst_reg, rc_reg); 872 if (insn_is_zext(&insn[1])) 873 insn_count = 2; 874 break; 875 } 876 case BPF_ALU64 | BPF_DIV | BPF_K: /* dst = dst / imm */ 877 case BPF_ALU64 | BPF_MOD | BPF_K: /* dst = dst % imm */ 878 { 879 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0; 880 881 if (imm == 1) { 882 if (BPF_OP(insn->code) == BPF_MOD) 883 /* lhgi %dst,0 */ 884 EMIT4_IMM(0xa7090000, dst_reg, 0); 885 break; 886 } 887 /* lghi %w0,0 */ 888 EMIT4_IMM(0xa7090000, REG_W0, 0); 889 /* lgr %w1,%dst */ 890 EMIT4(0xb9040000, REG_W1, dst_reg); 891 if (!is_first_pass(jit) && can_use_ldisp_for_lit64(jit)) { 892 /* dlg %w0,<d(imm)>(%l) */ 893 EMIT6_DISP_LH(0xe3000000, 0x0087, REG_W0, REG_0, REG_L, 894 EMIT_CONST_U64(imm)); 895 } else { 896 /* lgrl %dst,imm */ 897 EMIT6_PCREL_RILB(0xc4080000, dst_reg, 898 _EMIT_CONST_U64(imm)); 899 jit->seen |= SEEN_LITERAL; 900 /* dlgr %w0,%dst */ 901 EMIT4(0xb9870000, REG_W0, dst_reg); 902 } 903 /* lgr %dst,%rc */ 904 EMIT4(0xb9040000, dst_reg, rc_reg); 905 break; 906 } 907 /* 908 * BPF_AND 909 */ 910 case BPF_ALU | BPF_AND | BPF_X: /* dst = (u32) dst & (u32) src */ 911 /* nr %dst,%src */ 912 EMIT2(0x1400, dst_reg, src_reg); 913 EMIT_ZERO(dst_reg); 914 break; 915 case BPF_ALU64 | BPF_AND | BPF_X: /* dst = dst & src */ 916 /* ngr %dst,%src */ 917 EMIT4(0xb9800000, dst_reg, src_reg); 918 break; 919 case BPF_ALU | BPF_AND | BPF_K: /* dst = (u32) dst & (u32) imm */ 920 /* nilf %dst,imm */ 921 EMIT6_IMM(0xc00b0000, dst_reg, imm); 922 EMIT_ZERO(dst_reg); 923 break; 924 case BPF_ALU64 | BPF_AND | BPF_K: /* dst = dst & imm */ 925 if (!is_first_pass(jit) && can_use_ldisp_for_lit64(jit)) { 926 /* ng %dst,<d(imm)>(%l) */ 927 EMIT6_DISP_LH(0xe3000000, 0x0080, 928 dst_reg, REG_0, REG_L, 929 EMIT_CONST_U64(imm)); 930 } else { 931 /* lgrl %w0,imm */ 932 EMIT6_PCREL_RILB(0xc4080000, REG_W0, 933 _EMIT_CONST_U64(imm)); 934 jit->seen |= SEEN_LITERAL; 935 /* ngr %dst,%w0 */ 936 EMIT4(0xb9800000, dst_reg, REG_W0); 937 } 938 break; 939 /* 940 * BPF_OR 941 */ 942 case BPF_ALU | BPF_OR | BPF_X: /* dst = (u32) dst | (u32) src */ 943 /* or %dst,%src */ 944 EMIT2(0x1600, dst_reg, src_reg); 945 EMIT_ZERO(dst_reg); 946 break; 947 case BPF_ALU64 | BPF_OR | BPF_X: /* dst = dst | src */ 948 /* ogr %dst,%src */ 949 EMIT4(0xb9810000, dst_reg, src_reg); 950 break; 951 case BPF_ALU | BPF_OR | BPF_K: /* dst = (u32) dst | (u32) imm */ 952 /* oilf %dst,imm */ 953 EMIT6_IMM(0xc00d0000, dst_reg, imm); 954 EMIT_ZERO(dst_reg); 955 break; 956 case BPF_ALU64 | BPF_OR | BPF_K: /* dst = dst | imm */ 957 if (!is_first_pass(jit) && can_use_ldisp_for_lit64(jit)) { 958 /* og %dst,<d(imm)>(%l) */ 959 EMIT6_DISP_LH(0xe3000000, 0x0081, 960 dst_reg, REG_0, REG_L, 961 EMIT_CONST_U64(imm)); 962 } else { 963 /* lgrl %w0,imm */ 964 EMIT6_PCREL_RILB(0xc4080000, REG_W0, 965 _EMIT_CONST_U64(imm)); 966 jit->seen |= SEEN_LITERAL; 967 /* ogr %dst,%w0 */ 968 EMIT4(0xb9810000, dst_reg, REG_W0); 969 } 970 break; 971 /* 972 * BPF_XOR 973 */ 974 case BPF_ALU | BPF_XOR | BPF_X: /* dst = (u32) dst ^ (u32) src */ 975 /* xr %dst,%src */ 976 EMIT2(0x1700, dst_reg, src_reg); 977 EMIT_ZERO(dst_reg); 978 break; 979 case BPF_ALU64 | BPF_XOR | BPF_X: /* dst = dst ^ src */ 980 /* xgr %dst,%src */ 981 EMIT4(0xb9820000, dst_reg, src_reg); 982 break; 983 case BPF_ALU | BPF_XOR | BPF_K: /* dst = (u32) dst ^ (u32) imm */ 984 if (!imm) 985 break; 986 /* xilf %dst,imm */ 987 EMIT6_IMM(0xc0070000, dst_reg, imm); 988 EMIT_ZERO(dst_reg); 989 break; 990 case BPF_ALU64 | BPF_XOR | BPF_K: /* dst = dst ^ imm */ 991 if (!is_first_pass(jit) && can_use_ldisp_for_lit64(jit)) { 992 /* xg %dst,<d(imm)>(%l) */ 993 EMIT6_DISP_LH(0xe3000000, 0x0082, 994 dst_reg, REG_0, REG_L, 995 EMIT_CONST_U64(imm)); 996 } else { 997 /* lgrl %w0,imm */ 998 EMIT6_PCREL_RILB(0xc4080000, REG_W0, 999 _EMIT_CONST_U64(imm)); 1000 jit->seen |= SEEN_LITERAL; 1001 /* xgr %dst,%w0 */ 1002 EMIT4(0xb9820000, dst_reg, REG_W0); 1003 } 1004 break; 1005 /* 1006 * BPF_LSH 1007 */ 1008 case BPF_ALU | BPF_LSH | BPF_X: /* dst = (u32) dst << (u32) src */ 1009 /* sll %dst,0(%src) */ 1010 EMIT4_DISP(0x89000000, dst_reg, src_reg, 0); 1011 EMIT_ZERO(dst_reg); 1012 break; 1013 case BPF_ALU64 | BPF_LSH | BPF_X: /* dst = dst << src */ 1014 /* sllg %dst,%dst,0(%src) */ 1015 EMIT6_DISP_LH(0xeb000000, 0x000d, dst_reg, dst_reg, src_reg, 0); 1016 break; 1017 case BPF_ALU | BPF_LSH | BPF_K: /* dst = (u32) dst << (u32) imm */ 1018 if (imm == 0) 1019 break; 1020 /* sll %dst,imm(%r0) */ 1021 EMIT4_DISP(0x89000000, dst_reg, REG_0, imm); 1022 EMIT_ZERO(dst_reg); 1023 break; 1024 case BPF_ALU64 | BPF_LSH | BPF_K: /* dst = dst << imm */ 1025 if (imm == 0) 1026 break; 1027 /* sllg %dst,%dst,imm(%r0) */ 1028 EMIT6_DISP_LH(0xeb000000, 0x000d, dst_reg, dst_reg, REG_0, imm); 1029 break; 1030 /* 1031 * BPF_RSH 1032 */ 1033 case BPF_ALU | BPF_RSH | BPF_X: /* dst = (u32) dst >> (u32) src */ 1034 /* srl %dst,0(%src) */ 1035 EMIT4_DISP(0x88000000, dst_reg, src_reg, 0); 1036 EMIT_ZERO(dst_reg); 1037 break; 1038 case BPF_ALU64 | BPF_RSH | BPF_X: /* dst = dst >> src */ 1039 /* srlg %dst,%dst,0(%src) */ 1040 EMIT6_DISP_LH(0xeb000000, 0x000c, dst_reg, dst_reg, src_reg, 0); 1041 break; 1042 case BPF_ALU | BPF_RSH | BPF_K: /* dst = (u32) dst >> (u32) imm */ 1043 if (imm == 0) 1044 break; 1045 /* srl %dst,imm(%r0) */ 1046 EMIT4_DISP(0x88000000, dst_reg, REG_0, imm); 1047 EMIT_ZERO(dst_reg); 1048 break; 1049 case BPF_ALU64 | BPF_RSH | BPF_K: /* dst = dst >> imm */ 1050 if (imm == 0) 1051 break; 1052 /* srlg %dst,%dst,imm(%r0) */ 1053 EMIT6_DISP_LH(0xeb000000, 0x000c, dst_reg, dst_reg, REG_0, imm); 1054 break; 1055 /* 1056 * BPF_ARSH 1057 */ 1058 case BPF_ALU | BPF_ARSH | BPF_X: /* ((s32) dst) >>= src */ 1059 /* sra %dst,%dst,0(%src) */ 1060 EMIT4_DISP(0x8a000000, dst_reg, src_reg, 0); 1061 EMIT_ZERO(dst_reg); 1062 break; 1063 case BPF_ALU64 | BPF_ARSH | BPF_X: /* ((s64) dst) >>= src */ 1064 /* srag %dst,%dst,0(%src) */ 1065 EMIT6_DISP_LH(0xeb000000, 0x000a, dst_reg, dst_reg, src_reg, 0); 1066 break; 1067 case BPF_ALU | BPF_ARSH | BPF_K: /* ((s32) dst >> imm */ 1068 if (imm == 0) 1069 break; 1070 /* sra %dst,imm(%r0) */ 1071 EMIT4_DISP(0x8a000000, dst_reg, REG_0, imm); 1072 EMIT_ZERO(dst_reg); 1073 break; 1074 case BPF_ALU64 | BPF_ARSH | BPF_K: /* ((s64) dst) >>= imm */ 1075 if (imm == 0) 1076 break; 1077 /* srag %dst,%dst,imm(%r0) */ 1078 EMIT6_DISP_LH(0xeb000000, 0x000a, dst_reg, dst_reg, REG_0, imm); 1079 break; 1080 /* 1081 * BPF_NEG 1082 */ 1083 case BPF_ALU | BPF_NEG: /* dst = (u32) -dst */ 1084 /* lcr %dst,%dst */ 1085 EMIT2(0x1300, dst_reg, dst_reg); 1086 EMIT_ZERO(dst_reg); 1087 break; 1088 case BPF_ALU64 | BPF_NEG: /* dst = -dst */ 1089 /* lcgr %dst,%dst */ 1090 EMIT4(0xb9030000, dst_reg, dst_reg); 1091 break; 1092 /* 1093 * BPF_FROM_BE/LE 1094 */ 1095 case BPF_ALU | BPF_END | BPF_FROM_BE: 1096 /* s390 is big endian, therefore only clear high order bytes */ 1097 switch (imm) { 1098 case 16: /* dst = (u16) cpu_to_be16(dst) */ 1099 /* llghr %dst,%dst */ 1100 EMIT4(0xb9850000, dst_reg, dst_reg); 1101 if (insn_is_zext(&insn[1])) 1102 insn_count = 2; 1103 break; 1104 case 32: /* dst = (u32) cpu_to_be32(dst) */ 1105 if (!fp->aux->verifier_zext) 1106 /* llgfr %dst,%dst */ 1107 EMIT4(0xb9160000, dst_reg, dst_reg); 1108 break; 1109 case 64: /* dst = (u64) cpu_to_be64(dst) */ 1110 break; 1111 } 1112 break; 1113 case BPF_ALU | BPF_END | BPF_FROM_LE: 1114 switch (imm) { 1115 case 16: /* dst = (u16) cpu_to_le16(dst) */ 1116 /* lrvr %dst,%dst */ 1117 EMIT4(0xb91f0000, dst_reg, dst_reg); 1118 /* srl %dst,16(%r0) */ 1119 EMIT4_DISP(0x88000000, dst_reg, REG_0, 16); 1120 /* llghr %dst,%dst */ 1121 EMIT4(0xb9850000, dst_reg, dst_reg); 1122 if (insn_is_zext(&insn[1])) 1123 insn_count = 2; 1124 break; 1125 case 32: /* dst = (u32) cpu_to_le32(dst) */ 1126 /* lrvr %dst,%dst */ 1127 EMIT4(0xb91f0000, dst_reg, dst_reg); 1128 if (!fp->aux->verifier_zext) 1129 /* llgfr %dst,%dst */ 1130 EMIT4(0xb9160000, dst_reg, dst_reg); 1131 break; 1132 case 64: /* dst = (u64) cpu_to_le64(dst) */ 1133 /* lrvgr %dst,%dst */ 1134 EMIT4(0xb90f0000, dst_reg, dst_reg); 1135 break; 1136 } 1137 break; 1138 /* 1139 * BPF_ST(X) 1140 */ 1141 case BPF_STX | BPF_MEM | BPF_B: /* *(u8 *)(dst + off) = src_reg */ 1142 /* stcy %src,off(%dst) */ 1143 EMIT6_DISP_LH(0xe3000000, 0x0072, src_reg, dst_reg, REG_0, off); 1144 jit->seen |= SEEN_MEM; 1145 break; 1146 case BPF_STX | BPF_MEM | BPF_H: /* (u16 *)(dst + off) = src */ 1147 /* sthy %src,off(%dst) */ 1148 EMIT6_DISP_LH(0xe3000000, 0x0070, src_reg, dst_reg, REG_0, off); 1149 jit->seen |= SEEN_MEM; 1150 break; 1151 case BPF_STX | BPF_MEM | BPF_W: /* *(u32 *)(dst + off) = src */ 1152 /* sty %src,off(%dst) */ 1153 EMIT6_DISP_LH(0xe3000000, 0x0050, src_reg, dst_reg, REG_0, off); 1154 jit->seen |= SEEN_MEM; 1155 break; 1156 case BPF_STX | BPF_MEM | BPF_DW: /* (u64 *)(dst + off) = src */ 1157 /* stg %src,off(%dst) */ 1158 EMIT6_DISP_LH(0xe3000000, 0x0024, src_reg, dst_reg, REG_0, off); 1159 jit->seen |= SEEN_MEM; 1160 break; 1161 case BPF_ST | BPF_MEM | BPF_B: /* *(u8 *)(dst + off) = imm */ 1162 /* lhi %w0,imm */ 1163 EMIT4_IMM(0xa7080000, REG_W0, (u8) imm); 1164 /* stcy %w0,off(dst) */ 1165 EMIT6_DISP_LH(0xe3000000, 0x0072, REG_W0, dst_reg, REG_0, off); 1166 jit->seen |= SEEN_MEM; 1167 break; 1168 case BPF_ST | BPF_MEM | BPF_H: /* (u16 *)(dst + off) = imm */ 1169 /* lhi %w0,imm */ 1170 EMIT4_IMM(0xa7080000, REG_W0, (u16) imm); 1171 /* sthy %w0,off(dst) */ 1172 EMIT6_DISP_LH(0xe3000000, 0x0070, REG_W0, dst_reg, REG_0, off); 1173 jit->seen |= SEEN_MEM; 1174 break; 1175 case BPF_ST | BPF_MEM | BPF_W: /* *(u32 *)(dst + off) = imm */ 1176 /* llilf %w0,imm */ 1177 EMIT6_IMM(0xc00f0000, REG_W0, (u32) imm); 1178 /* sty %w0,off(%dst) */ 1179 EMIT6_DISP_LH(0xe3000000, 0x0050, REG_W0, dst_reg, REG_0, off); 1180 jit->seen |= SEEN_MEM; 1181 break; 1182 case BPF_ST | BPF_MEM | BPF_DW: /* *(u64 *)(dst + off) = imm */ 1183 /* lgfi %w0,imm */ 1184 EMIT6_IMM(0xc0010000, REG_W0, imm); 1185 /* stg %w0,off(%dst) */ 1186 EMIT6_DISP_LH(0xe3000000, 0x0024, REG_W0, dst_reg, REG_0, off); 1187 jit->seen |= SEEN_MEM; 1188 break; 1189 /* 1190 * BPF_STX XADD (atomic_add) 1191 */ 1192 case BPF_STX | BPF_XADD | BPF_W: /* *(u32 *)(dst + off) += src */ 1193 /* laal %w0,%src,off(%dst) */ 1194 EMIT6_DISP_LH(0xeb000000, 0x00fa, REG_W0, src_reg, 1195 dst_reg, off); 1196 jit->seen |= SEEN_MEM; 1197 break; 1198 case BPF_STX | BPF_XADD | BPF_DW: /* *(u64 *)(dst + off) += src */ 1199 /* laalg %w0,%src,off(%dst) */ 1200 EMIT6_DISP_LH(0xeb000000, 0x00ea, REG_W0, src_reg, 1201 dst_reg, off); 1202 jit->seen |= SEEN_MEM; 1203 break; 1204 /* 1205 * BPF_LDX 1206 */ 1207 case BPF_LDX | BPF_MEM | BPF_B: /* dst = *(u8 *)(ul) (src + off) */ 1208 case BPF_LDX | BPF_PROBE_MEM | BPF_B: 1209 /* llgc %dst,0(off,%src) */ 1210 EMIT6_DISP_LH(0xe3000000, 0x0090, dst_reg, src_reg, REG_0, off); 1211 jit->seen |= SEEN_MEM; 1212 if (insn_is_zext(&insn[1])) 1213 insn_count = 2; 1214 break; 1215 case BPF_LDX | BPF_MEM | BPF_H: /* dst = *(u16 *)(ul) (src + off) */ 1216 case BPF_LDX | BPF_PROBE_MEM | BPF_H: 1217 /* llgh %dst,0(off,%src) */ 1218 EMIT6_DISP_LH(0xe3000000, 0x0091, dst_reg, src_reg, REG_0, off); 1219 jit->seen |= SEEN_MEM; 1220 if (insn_is_zext(&insn[1])) 1221 insn_count = 2; 1222 break; 1223 case BPF_LDX | BPF_MEM | BPF_W: /* dst = *(u32 *)(ul) (src + off) */ 1224 case BPF_LDX | BPF_PROBE_MEM | BPF_W: 1225 /* llgf %dst,off(%src) */ 1226 jit->seen |= SEEN_MEM; 1227 EMIT6_DISP_LH(0xe3000000, 0x0016, dst_reg, src_reg, REG_0, off); 1228 if (insn_is_zext(&insn[1])) 1229 insn_count = 2; 1230 break; 1231 case BPF_LDX | BPF_MEM | BPF_DW: /* dst = *(u64 *)(ul) (src + off) */ 1232 case BPF_LDX | BPF_PROBE_MEM | BPF_DW: 1233 /* lg %dst,0(off,%src) */ 1234 jit->seen |= SEEN_MEM; 1235 EMIT6_DISP_LH(0xe3000000, 0x0004, dst_reg, src_reg, REG_0, off); 1236 break; 1237 /* 1238 * BPF_JMP / CALL 1239 */ 1240 case BPF_JMP | BPF_CALL: 1241 { 1242 u64 func; 1243 bool func_addr_fixed; 1244 int ret; 1245 1246 ret = bpf_jit_get_func_addr(fp, insn, extra_pass, 1247 &func, &func_addr_fixed); 1248 if (ret < 0) 1249 return -1; 1250 1251 REG_SET_SEEN(BPF_REG_5); 1252 jit->seen |= SEEN_FUNC; 1253 /* lgrl %w1,func */ 1254 EMIT6_PCREL_RILB(0xc4080000, REG_W1, _EMIT_CONST_U64(func)); 1255 if (__is_defined(CC_USING_EXPOLINE) && !nospec_disable) { 1256 /* brasl %r14,__s390_indirect_jump_r1 */ 1257 EMIT6_PCREL_RILB(0xc0050000, REG_14, jit->r1_thunk_ip); 1258 } else { 1259 /* basr %r14,%w1 */ 1260 EMIT2(0x0d00, REG_14, REG_W1); 1261 } 1262 /* lgr %b0,%r2: load return value into %b0 */ 1263 EMIT4(0xb9040000, BPF_REG_0, REG_2); 1264 break; 1265 } 1266 case BPF_JMP | BPF_TAIL_CALL: 1267 /* 1268 * Implicit input: 1269 * B1: pointer to ctx 1270 * B2: pointer to bpf_array 1271 * B3: index in bpf_array 1272 */ 1273 jit->seen |= SEEN_TAIL_CALL; 1274 1275 /* 1276 * if (index >= array->map.max_entries) 1277 * goto out; 1278 */ 1279 1280 /* llgf %w1,map.max_entries(%b2) */ 1281 EMIT6_DISP_LH(0xe3000000, 0x0016, REG_W1, REG_0, BPF_REG_2, 1282 offsetof(struct bpf_array, map.max_entries)); 1283 /* if ((u32)%b3 >= (u32)%w1) goto out; */ 1284 if (!is_first_pass(jit) && can_use_rel(jit, jit->labels[0])) { 1285 /* clrj %b3,%w1,0xa,label0 */ 1286 EMIT6_PCREL_LABEL(0xec000000, 0x0077, BPF_REG_3, 1287 REG_W1, 0, 0xa); 1288 } else { 1289 /* clr %b3,%w1 */ 1290 EMIT2(0x1500, BPF_REG_3, REG_W1); 1291 /* brcl 0xa,label0 */ 1292 EMIT6_PCREL_RILC(0xc0040000, 0xa, jit->labels[0]); 1293 } 1294 1295 /* 1296 * if (tail_call_cnt++ > MAX_TAIL_CALL_CNT) 1297 * goto out; 1298 */ 1299 1300 if (jit->seen & SEEN_STACK) 1301 off = STK_OFF_TCCNT + STK_OFF + stack_depth; 1302 else 1303 off = STK_OFF_TCCNT; 1304 /* lhi %w0,1 */ 1305 EMIT4_IMM(0xa7080000, REG_W0, 1); 1306 /* laal %w1,%w0,off(%r15) */ 1307 EMIT6_DISP_LH(0xeb000000, 0x00fa, REG_W1, REG_W0, REG_15, off); 1308 if (!is_first_pass(jit) && can_use_rel(jit, jit->labels[0])) { 1309 /* clij %w1,MAX_TAIL_CALL_CNT,0x2,label0 */ 1310 EMIT6_PCREL_IMM_LABEL(0xec000000, 0x007f, REG_W1, 1311 MAX_TAIL_CALL_CNT, 0, 0x2); 1312 } else { 1313 /* clfi %w1,MAX_TAIL_CALL_CNT */ 1314 EMIT6_IMM(0xc20f0000, REG_W1, MAX_TAIL_CALL_CNT); 1315 /* brcl 0x2,label0 */ 1316 EMIT6_PCREL_RILC(0xc0040000, 0x2, jit->labels[0]); 1317 } 1318 1319 /* 1320 * prog = array->ptrs[index]; 1321 * if (prog == NULL) 1322 * goto out; 1323 */ 1324 1325 /* llgfr %r1,%b3: %r1 = (u32) index */ 1326 EMIT4(0xb9160000, REG_1, BPF_REG_3); 1327 /* sllg %r1,%r1,3: %r1 *= 8 */ 1328 EMIT6_DISP_LH(0xeb000000, 0x000d, REG_1, REG_1, REG_0, 3); 1329 /* ltg %r1,prog(%b2,%r1) */ 1330 EMIT6_DISP_LH(0xe3000000, 0x0002, REG_1, BPF_REG_2, 1331 REG_1, offsetof(struct bpf_array, ptrs)); 1332 if (!is_first_pass(jit) && can_use_rel(jit, jit->labels[0])) { 1333 /* brc 0x8,label0 */ 1334 EMIT4_PCREL_RIC(0xa7040000, 0x8, jit->labels[0]); 1335 } else { 1336 /* brcl 0x8,label0 */ 1337 EMIT6_PCREL_RILC(0xc0040000, 0x8, jit->labels[0]); 1338 } 1339 1340 /* 1341 * Restore registers before calling function 1342 */ 1343 save_restore_regs(jit, REGS_RESTORE, stack_depth); 1344 1345 /* 1346 * goto *(prog->bpf_func + tail_call_start); 1347 */ 1348 1349 /* lg %r1,bpf_func(%r1) */ 1350 EMIT6_DISP_LH(0xe3000000, 0x0004, REG_1, REG_1, REG_0, 1351 offsetof(struct bpf_prog, bpf_func)); 1352 /* bc 0xf,tail_call_start(%r1) */ 1353 _EMIT4(0x47f01000 + jit->tail_call_start); 1354 /* out: */ 1355 jit->labels[0] = jit->prg; 1356 break; 1357 case BPF_JMP | BPF_EXIT: /* return b0 */ 1358 last = (i == fp->len - 1) ? 1 : 0; 1359 if (last) 1360 break; 1361 /* j <exit> */ 1362 EMIT4_PCREL(0xa7f40000, jit->exit_ip - jit->prg); 1363 break; 1364 /* 1365 * Branch relative (number of skipped instructions) to offset on 1366 * condition. 1367 * 1368 * Condition code to mask mapping: 1369 * 1370 * CC | Description | Mask 1371 * ------------------------------ 1372 * 0 | Operands equal | 8 1373 * 1 | First operand low | 4 1374 * 2 | First operand high | 2 1375 * 3 | Unused | 1 1376 * 1377 * For s390x relative branches: ip = ip + off_bytes 1378 * For BPF relative branches: insn = insn + off_insns + 1 1379 * 1380 * For example for s390x with offset 0 we jump to the branch 1381 * instruction itself (loop) and for BPF with offset 0 we 1382 * branch to the instruction behind the branch. 1383 */ 1384 case BPF_JMP | BPF_JA: /* if (true) */ 1385 mask = 0xf000; /* j */ 1386 goto branch_oc; 1387 case BPF_JMP | BPF_JSGT | BPF_K: /* ((s64) dst > (s64) imm) */ 1388 case BPF_JMP32 | BPF_JSGT | BPF_K: /* ((s32) dst > (s32) imm) */ 1389 mask = 0x2000; /* jh */ 1390 goto branch_ks; 1391 case BPF_JMP | BPF_JSLT | BPF_K: /* ((s64) dst < (s64) imm) */ 1392 case BPF_JMP32 | BPF_JSLT | BPF_K: /* ((s32) dst < (s32) imm) */ 1393 mask = 0x4000; /* jl */ 1394 goto branch_ks; 1395 case BPF_JMP | BPF_JSGE | BPF_K: /* ((s64) dst >= (s64) imm) */ 1396 case BPF_JMP32 | BPF_JSGE | BPF_K: /* ((s32) dst >= (s32) imm) */ 1397 mask = 0xa000; /* jhe */ 1398 goto branch_ks; 1399 case BPF_JMP | BPF_JSLE | BPF_K: /* ((s64) dst <= (s64) imm) */ 1400 case BPF_JMP32 | BPF_JSLE | BPF_K: /* ((s32) dst <= (s32) imm) */ 1401 mask = 0xc000; /* jle */ 1402 goto branch_ks; 1403 case BPF_JMP | BPF_JGT | BPF_K: /* (dst_reg > imm) */ 1404 case BPF_JMP32 | BPF_JGT | BPF_K: /* ((u32) dst_reg > (u32) imm) */ 1405 mask = 0x2000; /* jh */ 1406 goto branch_ku; 1407 case BPF_JMP | BPF_JLT | BPF_K: /* (dst_reg < imm) */ 1408 case BPF_JMP32 | BPF_JLT | BPF_K: /* ((u32) dst_reg < (u32) imm) */ 1409 mask = 0x4000; /* jl */ 1410 goto branch_ku; 1411 case BPF_JMP | BPF_JGE | BPF_K: /* (dst_reg >= imm) */ 1412 case BPF_JMP32 | BPF_JGE | BPF_K: /* ((u32) dst_reg >= (u32) imm) */ 1413 mask = 0xa000; /* jhe */ 1414 goto branch_ku; 1415 case BPF_JMP | BPF_JLE | BPF_K: /* (dst_reg <= imm) */ 1416 case BPF_JMP32 | BPF_JLE | BPF_K: /* ((u32) dst_reg <= (u32) imm) */ 1417 mask = 0xc000; /* jle */ 1418 goto branch_ku; 1419 case BPF_JMP | BPF_JNE | BPF_K: /* (dst_reg != imm) */ 1420 case BPF_JMP32 | BPF_JNE | BPF_K: /* ((u32) dst_reg != (u32) imm) */ 1421 mask = 0x7000; /* jne */ 1422 goto branch_ku; 1423 case BPF_JMP | BPF_JEQ | BPF_K: /* (dst_reg == imm) */ 1424 case BPF_JMP32 | BPF_JEQ | BPF_K: /* ((u32) dst_reg == (u32) imm) */ 1425 mask = 0x8000; /* je */ 1426 goto branch_ku; 1427 case BPF_JMP | BPF_JSET | BPF_K: /* (dst_reg & imm) */ 1428 case BPF_JMP32 | BPF_JSET | BPF_K: /* ((u32) dst_reg & (u32) imm) */ 1429 mask = 0x7000; /* jnz */ 1430 if (BPF_CLASS(insn->code) == BPF_JMP32) { 1431 /* llilf %w1,imm (load zero extend imm) */ 1432 EMIT6_IMM(0xc00f0000, REG_W1, imm); 1433 /* nr %w1,%dst */ 1434 EMIT2(0x1400, REG_W1, dst_reg); 1435 } else { 1436 /* lgfi %w1,imm (load sign extend imm) */ 1437 EMIT6_IMM(0xc0010000, REG_W1, imm); 1438 /* ngr %w1,%dst */ 1439 EMIT4(0xb9800000, REG_W1, dst_reg); 1440 } 1441 goto branch_oc; 1442 1443 case BPF_JMP | BPF_JSGT | BPF_X: /* ((s64) dst > (s64) src) */ 1444 case BPF_JMP32 | BPF_JSGT | BPF_X: /* ((s32) dst > (s32) src) */ 1445 mask = 0x2000; /* jh */ 1446 goto branch_xs; 1447 case BPF_JMP | BPF_JSLT | BPF_X: /* ((s64) dst < (s64) src) */ 1448 case BPF_JMP32 | BPF_JSLT | BPF_X: /* ((s32) dst < (s32) src) */ 1449 mask = 0x4000; /* jl */ 1450 goto branch_xs; 1451 case BPF_JMP | BPF_JSGE | BPF_X: /* ((s64) dst >= (s64) src) */ 1452 case BPF_JMP32 | BPF_JSGE | BPF_X: /* ((s32) dst >= (s32) src) */ 1453 mask = 0xa000; /* jhe */ 1454 goto branch_xs; 1455 case BPF_JMP | BPF_JSLE | BPF_X: /* ((s64) dst <= (s64) src) */ 1456 case BPF_JMP32 | BPF_JSLE | BPF_X: /* ((s32) dst <= (s32) src) */ 1457 mask = 0xc000; /* jle */ 1458 goto branch_xs; 1459 case BPF_JMP | BPF_JGT | BPF_X: /* (dst > src) */ 1460 case BPF_JMP32 | BPF_JGT | BPF_X: /* ((u32) dst > (u32) src) */ 1461 mask = 0x2000; /* jh */ 1462 goto branch_xu; 1463 case BPF_JMP | BPF_JLT | BPF_X: /* (dst < src) */ 1464 case BPF_JMP32 | BPF_JLT | BPF_X: /* ((u32) dst < (u32) src) */ 1465 mask = 0x4000; /* jl */ 1466 goto branch_xu; 1467 case BPF_JMP | BPF_JGE | BPF_X: /* (dst >= src) */ 1468 case BPF_JMP32 | BPF_JGE | BPF_X: /* ((u32) dst >= (u32) src) */ 1469 mask = 0xa000; /* jhe */ 1470 goto branch_xu; 1471 case BPF_JMP | BPF_JLE | BPF_X: /* (dst <= src) */ 1472 case BPF_JMP32 | BPF_JLE | BPF_X: /* ((u32) dst <= (u32) src) */ 1473 mask = 0xc000; /* jle */ 1474 goto branch_xu; 1475 case BPF_JMP | BPF_JNE | BPF_X: /* (dst != src) */ 1476 case BPF_JMP32 | BPF_JNE | BPF_X: /* ((u32) dst != (u32) src) */ 1477 mask = 0x7000; /* jne */ 1478 goto branch_xu; 1479 case BPF_JMP | BPF_JEQ | BPF_X: /* (dst == src) */ 1480 case BPF_JMP32 | BPF_JEQ | BPF_X: /* ((u32) dst == (u32) src) */ 1481 mask = 0x8000; /* je */ 1482 goto branch_xu; 1483 case BPF_JMP | BPF_JSET | BPF_X: /* (dst & src) */ 1484 case BPF_JMP32 | BPF_JSET | BPF_X: /* ((u32) dst & (u32) src) */ 1485 { 1486 bool is_jmp32 = BPF_CLASS(insn->code) == BPF_JMP32; 1487 1488 mask = 0x7000; /* jnz */ 1489 /* nrk or ngrk %w1,%dst,%src */ 1490 EMIT4_RRF((is_jmp32 ? 0xb9f40000 : 0xb9e40000), 1491 REG_W1, dst_reg, src_reg); 1492 goto branch_oc; 1493 branch_ks: 1494 is_jmp32 = BPF_CLASS(insn->code) == BPF_JMP32; 1495 /* cfi or cgfi %dst,imm */ 1496 EMIT6_IMM(is_jmp32 ? 0xc20d0000 : 0xc20c0000, 1497 dst_reg, imm); 1498 if (!is_first_pass(jit) && 1499 can_use_rel(jit, addrs[i + off + 1])) { 1500 /* brc mask,off */ 1501 EMIT4_PCREL_RIC(0xa7040000, 1502 mask >> 12, addrs[i + off + 1]); 1503 } else { 1504 /* brcl mask,off */ 1505 EMIT6_PCREL_RILC(0xc0040000, 1506 mask >> 12, addrs[i + off + 1]); 1507 } 1508 break; 1509 branch_ku: 1510 is_jmp32 = BPF_CLASS(insn->code) == BPF_JMP32; 1511 /* clfi or clgfi %dst,imm */ 1512 EMIT6_IMM(is_jmp32 ? 0xc20f0000 : 0xc20e0000, 1513 dst_reg, imm); 1514 if (!is_first_pass(jit) && 1515 can_use_rel(jit, addrs[i + off + 1])) { 1516 /* brc mask,off */ 1517 EMIT4_PCREL_RIC(0xa7040000, 1518 mask >> 12, addrs[i + off + 1]); 1519 } else { 1520 /* brcl mask,off */ 1521 EMIT6_PCREL_RILC(0xc0040000, 1522 mask >> 12, addrs[i + off + 1]); 1523 } 1524 break; 1525 branch_xs: 1526 is_jmp32 = BPF_CLASS(insn->code) == BPF_JMP32; 1527 if (!is_first_pass(jit) && 1528 can_use_rel(jit, addrs[i + off + 1])) { 1529 /* crj or cgrj %dst,%src,mask,off */ 1530 EMIT6_PCREL(0xec000000, (is_jmp32 ? 0x0076 : 0x0064), 1531 dst_reg, src_reg, i, off, mask); 1532 } else { 1533 /* cr or cgr %dst,%src */ 1534 if (is_jmp32) 1535 EMIT2(0x1900, dst_reg, src_reg); 1536 else 1537 EMIT4(0xb9200000, dst_reg, src_reg); 1538 /* brcl mask,off */ 1539 EMIT6_PCREL_RILC(0xc0040000, 1540 mask >> 12, addrs[i + off + 1]); 1541 } 1542 break; 1543 branch_xu: 1544 is_jmp32 = BPF_CLASS(insn->code) == BPF_JMP32; 1545 if (!is_first_pass(jit) && 1546 can_use_rel(jit, addrs[i + off + 1])) { 1547 /* clrj or clgrj %dst,%src,mask,off */ 1548 EMIT6_PCREL(0xec000000, (is_jmp32 ? 0x0077 : 0x0065), 1549 dst_reg, src_reg, i, off, mask); 1550 } else { 1551 /* clr or clgr %dst,%src */ 1552 if (is_jmp32) 1553 EMIT2(0x1500, dst_reg, src_reg); 1554 else 1555 EMIT4(0xb9210000, dst_reg, src_reg); 1556 /* brcl mask,off */ 1557 EMIT6_PCREL_RILC(0xc0040000, 1558 mask >> 12, addrs[i + off + 1]); 1559 } 1560 break; 1561 branch_oc: 1562 if (!is_first_pass(jit) && 1563 can_use_rel(jit, addrs[i + off + 1])) { 1564 /* brc mask,off */ 1565 EMIT4_PCREL_RIC(0xa7040000, 1566 mask >> 12, addrs[i + off + 1]); 1567 } else { 1568 /* brcl mask,off */ 1569 EMIT6_PCREL_RILC(0xc0040000, 1570 mask >> 12, addrs[i + off + 1]); 1571 } 1572 break; 1573 } 1574 default: /* too complex, give up */ 1575 pr_err("Unknown opcode %02x\n", insn->code); 1576 return -1; 1577 } 1578 1579 if (probe_prg != -1) { 1580 /* 1581 * Handlers of certain exceptions leave psw.addr pointing to 1582 * the instruction directly after the failing one. Therefore, 1583 * create two exception table entries and also add a nop in 1584 * case two probing instructions come directly after each 1585 * other. 1586 */ 1587 nop_prg = jit->prg; 1588 /* bcr 0,%0 */ 1589 _EMIT2(0x0700); 1590 err = bpf_jit_probe_mem(jit, fp, probe_prg, nop_prg); 1591 if (err < 0) 1592 return err; 1593 } 1594 1595 return insn_count; 1596 } 1597 1598 /* 1599 * Return whether new i-th instruction address does not violate any invariant 1600 */ 1601 static bool bpf_is_new_addr_sane(struct bpf_jit *jit, int i) 1602 { 1603 /* On the first pass anything goes */ 1604 if (is_first_pass(jit)) 1605 return true; 1606 1607 /* The codegen pass must not change anything */ 1608 if (is_codegen_pass(jit)) 1609 return jit->addrs[i] == jit->prg; 1610 1611 /* Passes in between must not increase code size */ 1612 return jit->addrs[i] >= jit->prg; 1613 } 1614 1615 /* 1616 * Update the address of i-th instruction 1617 */ 1618 static int bpf_set_addr(struct bpf_jit *jit, int i) 1619 { 1620 if (!bpf_is_new_addr_sane(jit, i)) 1621 return -1; 1622 jit->addrs[i] = jit->prg; 1623 return 0; 1624 } 1625 1626 /* 1627 * Compile eBPF program into s390x code 1628 */ 1629 static int bpf_jit_prog(struct bpf_jit *jit, struct bpf_prog *fp, 1630 bool extra_pass, u32 stack_depth) 1631 { 1632 int i, insn_count, lit32_size, lit64_size; 1633 1634 jit->lit32 = jit->lit32_start; 1635 jit->lit64 = jit->lit64_start; 1636 jit->prg = 0; 1637 jit->excnt = 0; 1638 1639 bpf_jit_prologue(jit, stack_depth); 1640 if (bpf_set_addr(jit, 0) < 0) 1641 return -1; 1642 for (i = 0; i < fp->len; i += insn_count) { 1643 insn_count = bpf_jit_insn(jit, fp, i, extra_pass, stack_depth); 1644 if (insn_count < 0) 1645 return -1; 1646 /* Next instruction address */ 1647 if (bpf_set_addr(jit, i + insn_count) < 0) 1648 return -1; 1649 } 1650 bpf_jit_epilogue(jit, stack_depth); 1651 1652 lit32_size = jit->lit32 - jit->lit32_start; 1653 lit64_size = jit->lit64 - jit->lit64_start; 1654 jit->lit32_start = jit->prg; 1655 if (lit32_size) 1656 jit->lit32_start = ALIGN(jit->lit32_start, 4); 1657 jit->lit64_start = jit->lit32_start + lit32_size; 1658 if (lit64_size) 1659 jit->lit64_start = ALIGN(jit->lit64_start, 8); 1660 jit->size = jit->lit64_start + lit64_size; 1661 jit->size_prg = jit->prg; 1662 1663 if (WARN_ON_ONCE(fp->aux->extable && 1664 jit->excnt != fp->aux->num_exentries)) 1665 /* Verifier bug - too many entries. */ 1666 return -1; 1667 1668 return 0; 1669 } 1670 1671 bool bpf_jit_needs_zext(void) 1672 { 1673 return true; 1674 } 1675 1676 struct s390_jit_data { 1677 struct bpf_binary_header *header; 1678 struct bpf_jit ctx; 1679 int pass; 1680 }; 1681 1682 static struct bpf_binary_header *bpf_jit_alloc(struct bpf_jit *jit, 1683 struct bpf_prog *fp) 1684 { 1685 struct bpf_binary_header *header; 1686 u32 extable_size; 1687 u32 code_size; 1688 1689 /* We need two entries per insn. */ 1690 fp->aux->num_exentries *= 2; 1691 1692 code_size = roundup(jit->size, 1693 __alignof__(struct exception_table_entry)); 1694 extable_size = fp->aux->num_exentries * 1695 sizeof(struct exception_table_entry); 1696 header = bpf_jit_binary_alloc(code_size + extable_size, &jit->prg_buf, 1697 8, jit_fill_hole); 1698 if (!header) 1699 return NULL; 1700 fp->aux->extable = (struct exception_table_entry *) 1701 (jit->prg_buf + code_size); 1702 return header; 1703 } 1704 1705 /* 1706 * Compile eBPF program "fp" 1707 */ 1708 struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *fp) 1709 { 1710 u32 stack_depth = round_up(fp->aux->stack_depth, 8); 1711 struct bpf_prog *tmp, *orig_fp = fp; 1712 struct bpf_binary_header *header; 1713 struct s390_jit_data *jit_data; 1714 bool tmp_blinded = false; 1715 bool extra_pass = false; 1716 struct bpf_jit jit; 1717 int pass; 1718 1719 if (!fp->jit_requested) 1720 return orig_fp; 1721 1722 tmp = bpf_jit_blind_constants(fp); 1723 /* 1724 * If blinding was requested and we failed during blinding, 1725 * we must fall back to the interpreter. 1726 */ 1727 if (IS_ERR(tmp)) 1728 return orig_fp; 1729 if (tmp != fp) { 1730 tmp_blinded = true; 1731 fp = tmp; 1732 } 1733 1734 jit_data = fp->aux->jit_data; 1735 if (!jit_data) { 1736 jit_data = kzalloc(sizeof(*jit_data), GFP_KERNEL); 1737 if (!jit_data) { 1738 fp = orig_fp; 1739 goto out; 1740 } 1741 fp->aux->jit_data = jit_data; 1742 } 1743 if (jit_data->ctx.addrs) { 1744 jit = jit_data->ctx; 1745 header = jit_data->header; 1746 extra_pass = true; 1747 pass = jit_data->pass + 1; 1748 goto skip_init_ctx; 1749 } 1750 1751 memset(&jit, 0, sizeof(jit)); 1752 jit.addrs = kvcalloc(fp->len + 1, sizeof(*jit.addrs), GFP_KERNEL); 1753 if (jit.addrs == NULL) { 1754 fp = orig_fp; 1755 goto out; 1756 } 1757 /* 1758 * Three initial passes: 1759 * - 1/2: Determine clobbered registers 1760 * - 3: Calculate program size and addrs arrray 1761 */ 1762 for (pass = 1; pass <= 3; pass++) { 1763 if (bpf_jit_prog(&jit, fp, extra_pass, stack_depth)) { 1764 fp = orig_fp; 1765 goto free_addrs; 1766 } 1767 } 1768 /* 1769 * Final pass: Allocate and generate program 1770 */ 1771 header = bpf_jit_alloc(&jit, fp); 1772 if (!header) { 1773 fp = orig_fp; 1774 goto free_addrs; 1775 } 1776 skip_init_ctx: 1777 if (bpf_jit_prog(&jit, fp, extra_pass, stack_depth)) { 1778 bpf_jit_binary_free(header); 1779 fp = orig_fp; 1780 goto free_addrs; 1781 } 1782 if (bpf_jit_enable > 1) { 1783 bpf_jit_dump(fp->len, jit.size, pass, jit.prg_buf); 1784 print_fn_code(jit.prg_buf, jit.size_prg); 1785 } 1786 if (!fp->is_func || extra_pass) { 1787 bpf_jit_binary_lock_ro(header); 1788 } else { 1789 jit_data->header = header; 1790 jit_data->ctx = jit; 1791 jit_data->pass = pass; 1792 } 1793 fp->bpf_func = (void *) jit.prg_buf; 1794 fp->jited = 1; 1795 fp->jited_len = jit.size; 1796 1797 if (!fp->is_func || extra_pass) { 1798 bpf_prog_fill_jited_linfo(fp, jit.addrs + 1); 1799 free_addrs: 1800 kvfree(jit.addrs); 1801 kfree(jit_data); 1802 fp->aux->jit_data = NULL; 1803 } 1804 out: 1805 if (tmp_blinded) 1806 bpf_jit_prog_release_other(fp, fp == orig_fp ? 1807 tmp : orig_fp); 1808 return fp; 1809 } 1810