1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * SMP related functions 4 * 5 * Copyright IBM Corp. 1999, 2012 6 * Author(s): Denis Joseph Barrow, 7 * Martin Schwidefsky <schwidefsky@de.ibm.com>, 8 * Heiko Carstens <heiko.carstens@de.ibm.com>, 9 * 10 * based on other smp stuff by 11 * (c) 1995 Alan Cox, CymruNET Ltd <alan@cymru.net> 12 * (c) 1998 Ingo Molnar 13 * 14 * The code outside of smp.c uses logical cpu numbers, only smp.c does 15 * the translation of logical to physical cpu ids. All new code that 16 * operates on physical cpu numbers needs to go into smp.c. 17 */ 18 19 #define KMSG_COMPONENT "cpu" 20 #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt 21 22 #include <linux/workqueue.h> 23 #include <linux/memblock.h> 24 #include <linux/export.h> 25 #include <linux/init.h> 26 #include <linux/mm.h> 27 #include <linux/err.h> 28 #include <linux/spinlock.h> 29 #include <linux/kernel_stat.h> 30 #include <linux/delay.h> 31 #include <linux/interrupt.h> 32 #include <linux/irqflags.h> 33 #include <linux/irq_work.h> 34 #include <linux/cpu.h> 35 #include <linux/slab.h> 36 #include <linux/sched/hotplug.h> 37 #include <linux/sched/task_stack.h> 38 #include <linux/crash_dump.h> 39 #include <linux/kprobes.h> 40 #include <asm/asm-offsets.h> 41 #include <asm/diag.h> 42 #include <asm/switch_to.h> 43 #include <asm/facility.h> 44 #include <asm/ipl.h> 45 #include <asm/setup.h> 46 #include <asm/irq.h> 47 #include <asm/tlbflush.h> 48 #include <asm/vtimer.h> 49 #include <asm/lowcore.h> 50 #include <asm/sclp.h> 51 #include <asm/debug.h> 52 #include <asm/os_info.h> 53 #include <asm/sigp.h> 54 #include <asm/idle.h> 55 #include <asm/nmi.h> 56 #include <asm/stacktrace.h> 57 #include <asm/topology.h> 58 #include <asm/vdso.h> 59 #include "entry.h" 60 61 enum { 62 ec_schedule = 0, 63 ec_call_function_single, 64 ec_stop_cpu, 65 ec_mcck_pending, 66 ec_irq_work, 67 }; 68 69 enum { 70 CPU_STATE_STANDBY, 71 CPU_STATE_CONFIGURED, 72 }; 73 74 static DEFINE_PER_CPU(struct cpu *, cpu_device); 75 76 struct pcpu { 77 unsigned long ec_mask; /* bit mask for ec_xxx functions */ 78 unsigned long ec_clk; /* sigp timestamp for ec_xxx */ 79 signed char state; /* physical cpu state */ 80 signed char polarization; /* physical polarization */ 81 u16 address; /* physical cpu address */ 82 }; 83 84 static u8 boot_core_type; 85 static struct pcpu pcpu_devices[NR_CPUS]; 86 87 unsigned int smp_cpu_mt_shift; 88 EXPORT_SYMBOL(smp_cpu_mt_shift); 89 90 unsigned int smp_cpu_mtid; 91 EXPORT_SYMBOL(smp_cpu_mtid); 92 93 #ifdef CONFIG_CRASH_DUMP 94 __vector128 __initdata boot_cpu_vector_save_area[__NUM_VXRS]; 95 #endif 96 97 static unsigned int smp_max_threads __initdata = -1U; 98 cpumask_t cpu_setup_mask; 99 100 static int __init early_nosmt(char *s) 101 { 102 smp_max_threads = 1; 103 return 0; 104 } 105 early_param("nosmt", early_nosmt); 106 107 static int __init early_smt(char *s) 108 { 109 get_option(&s, &smp_max_threads); 110 return 0; 111 } 112 early_param("smt", early_smt); 113 114 /* 115 * The smp_cpu_state_mutex must be held when changing the state or polarization 116 * member of a pcpu data structure within the pcpu_devices arreay. 117 */ 118 DEFINE_MUTEX(smp_cpu_state_mutex); 119 120 /* 121 * Signal processor helper functions. 122 */ 123 static inline int __pcpu_sigp_relax(u16 addr, u8 order, unsigned long parm) 124 { 125 int cc; 126 127 while (1) { 128 cc = __pcpu_sigp(addr, order, parm, NULL); 129 if (cc != SIGP_CC_BUSY) 130 return cc; 131 cpu_relax(); 132 } 133 } 134 135 static int pcpu_sigp_retry(struct pcpu *pcpu, u8 order, u32 parm) 136 { 137 int cc, retry; 138 139 for (retry = 0; ; retry++) { 140 cc = __pcpu_sigp(pcpu->address, order, parm, NULL); 141 if (cc != SIGP_CC_BUSY) 142 break; 143 if (retry >= 3) 144 udelay(10); 145 } 146 return cc; 147 } 148 149 static inline int pcpu_stopped(struct pcpu *pcpu) 150 { 151 u32 status; 152 153 if (__pcpu_sigp(pcpu->address, SIGP_SENSE, 154 0, &status) != SIGP_CC_STATUS_STORED) 155 return 0; 156 return !!(status & (SIGP_STATUS_CHECK_STOP|SIGP_STATUS_STOPPED)); 157 } 158 159 static inline int pcpu_running(struct pcpu *pcpu) 160 { 161 if (__pcpu_sigp(pcpu->address, SIGP_SENSE_RUNNING, 162 0, NULL) != SIGP_CC_STATUS_STORED) 163 return 1; 164 /* Status stored condition code is equivalent to cpu not running. */ 165 return 0; 166 } 167 168 /* 169 * Find struct pcpu by cpu address. 170 */ 171 static struct pcpu *pcpu_find_address(const struct cpumask *mask, u16 address) 172 { 173 int cpu; 174 175 for_each_cpu(cpu, mask) 176 if (pcpu_devices[cpu].address == address) 177 return pcpu_devices + cpu; 178 return NULL; 179 } 180 181 static void pcpu_ec_call(struct pcpu *pcpu, int ec_bit) 182 { 183 int order; 184 185 if (test_and_set_bit(ec_bit, &pcpu->ec_mask)) 186 return; 187 order = pcpu_running(pcpu) ? SIGP_EXTERNAL_CALL : SIGP_EMERGENCY_SIGNAL; 188 pcpu->ec_clk = get_tod_clock_fast(); 189 pcpu_sigp_retry(pcpu, order, 0); 190 } 191 192 static int pcpu_alloc_lowcore(struct pcpu *pcpu, int cpu) 193 { 194 unsigned long async_stack, nodat_stack, mcck_stack; 195 struct lowcore *lc; 196 197 lc = (struct lowcore *) __get_free_pages(GFP_KERNEL | GFP_DMA, LC_ORDER); 198 nodat_stack = __get_free_pages(GFP_KERNEL, THREAD_SIZE_ORDER); 199 async_stack = stack_alloc(); 200 mcck_stack = stack_alloc(); 201 if (!lc || !nodat_stack || !async_stack || !mcck_stack) 202 goto out; 203 memcpy(lc, &S390_lowcore, 512); 204 memset((char *) lc + 512, 0, sizeof(*lc) - 512); 205 lc->async_stack = async_stack + STACK_INIT_OFFSET; 206 lc->nodat_stack = nodat_stack + STACK_INIT_OFFSET; 207 lc->mcck_stack = mcck_stack + STACK_INIT_OFFSET; 208 lc->cpu_nr = cpu; 209 lc->spinlock_lockval = arch_spin_lockval(cpu); 210 lc->spinlock_index = 0; 211 lc->br_r1_trampoline = 0x07f1; /* br %r1 */ 212 lc->return_lpswe = gen_lpswe(__LC_RETURN_PSW); 213 lc->return_mcck_lpswe = gen_lpswe(__LC_RETURN_MCCK_PSW); 214 lc->preempt_count = PREEMPT_DISABLED; 215 if (nmi_alloc_per_cpu(lc)) 216 goto out; 217 lowcore_ptr[cpu] = lc; 218 pcpu_sigp_retry(pcpu, SIGP_SET_PREFIX, (u32)(unsigned long) lc); 219 return 0; 220 221 out: 222 stack_free(mcck_stack); 223 stack_free(async_stack); 224 free_pages(nodat_stack, THREAD_SIZE_ORDER); 225 free_pages((unsigned long) lc, LC_ORDER); 226 return -ENOMEM; 227 } 228 229 static void pcpu_free_lowcore(struct pcpu *pcpu) 230 { 231 unsigned long async_stack, nodat_stack, mcck_stack; 232 struct lowcore *lc; 233 int cpu; 234 235 cpu = pcpu - pcpu_devices; 236 lc = lowcore_ptr[cpu]; 237 nodat_stack = lc->nodat_stack - STACK_INIT_OFFSET; 238 async_stack = lc->async_stack - STACK_INIT_OFFSET; 239 mcck_stack = lc->mcck_stack - STACK_INIT_OFFSET; 240 pcpu_sigp_retry(pcpu, SIGP_SET_PREFIX, 0); 241 lowcore_ptr[cpu] = NULL; 242 nmi_free_per_cpu(lc); 243 stack_free(async_stack); 244 stack_free(mcck_stack); 245 free_pages(nodat_stack, THREAD_SIZE_ORDER); 246 free_pages((unsigned long) lc, LC_ORDER); 247 } 248 249 static void pcpu_prepare_secondary(struct pcpu *pcpu, int cpu) 250 { 251 struct lowcore *lc = lowcore_ptr[cpu]; 252 253 cpumask_set_cpu(cpu, &init_mm.context.cpu_attach_mask); 254 cpumask_set_cpu(cpu, mm_cpumask(&init_mm)); 255 lc->cpu_nr = cpu; 256 lc->restart_flags = RESTART_FLAG_CTLREGS; 257 lc->spinlock_lockval = arch_spin_lockval(cpu); 258 lc->spinlock_index = 0; 259 lc->percpu_offset = __per_cpu_offset[cpu]; 260 lc->kernel_asce = S390_lowcore.kernel_asce; 261 lc->user_asce = s390_invalid_asce; 262 lc->machine_flags = S390_lowcore.machine_flags; 263 lc->user_timer = lc->system_timer = 264 lc->steal_timer = lc->avg_steal_timer = 0; 265 __ctl_store(lc->cregs_save_area, 0, 15); 266 lc->cregs_save_area[1] = lc->kernel_asce; 267 lc->cregs_save_area[7] = lc->user_asce; 268 save_access_regs((unsigned int *) lc->access_regs_save_area); 269 arch_spin_lock_setup(cpu); 270 } 271 272 static void pcpu_attach_task(struct pcpu *pcpu, struct task_struct *tsk) 273 { 274 struct lowcore *lc; 275 int cpu; 276 277 cpu = pcpu - pcpu_devices; 278 lc = lowcore_ptr[cpu]; 279 lc->kernel_stack = (unsigned long) task_stack_page(tsk) 280 + THREAD_SIZE - STACK_FRAME_OVERHEAD - sizeof(struct pt_regs); 281 lc->current_task = (unsigned long) tsk; 282 lc->lpp = LPP_MAGIC; 283 lc->current_pid = tsk->pid; 284 lc->user_timer = tsk->thread.user_timer; 285 lc->guest_timer = tsk->thread.guest_timer; 286 lc->system_timer = tsk->thread.system_timer; 287 lc->hardirq_timer = tsk->thread.hardirq_timer; 288 lc->softirq_timer = tsk->thread.softirq_timer; 289 lc->steal_timer = 0; 290 } 291 292 static void pcpu_start_fn(struct pcpu *pcpu, void (*func)(void *), void *data) 293 { 294 struct lowcore *lc; 295 int cpu; 296 297 cpu = pcpu - pcpu_devices; 298 lc = lowcore_ptr[cpu]; 299 lc->restart_stack = lc->kernel_stack; 300 lc->restart_fn = (unsigned long) func; 301 lc->restart_data = (unsigned long) data; 302 lc->restart_source = -1U; 303 pcpu_sigp_retry(pcpu, SIGP_RESTART, 0); 304 } 305 306 typedef void (pcpu_delegate_fn)(void *); 307 308 /* 309 * Call function via PSW restart on pcpu and stop the current cpu. 310 */ 311 static void __pcpu_delegate(pcpu_delegate_fn *func, void *data) 312 { 313 func(data); /* should not return */ 314 } 315 316 static void pcpu_delegate(struct pcpu *pcpu, 317 pcpu_delegate_fn *func, 318 void *data, unsigned long stack) 319 { 320 struct lowcore *lc = lowcore_ptr[pcpu - pcpu_devices]; 321 unsigned int source_cpu = stap(); 322 323 __load_psw_mask(PSW_KERNEL_BITS | PSW_MASK_DAT); 324 if (pcpu->address == source_cpu) { 325 call_on_stack(2, stack, void, __pcpu_delegate, 326 pcpu_delegate_fn *, func, void *, data); 327 } 328 /* Stop target cpu (if func returns this stops the current cpu). */ 329 pcpu_sigp_retry(pcpu, SIGP_STOP, 0); 330 /* Restart func on the target cpu and stop the current cpu. */ 331 mem_assign_absolute(lc->restart_stack, stack); 332 mem_assign_absolute(lc->restart_fn, (unsigned long) func); 333 mem_assign_absolute(lc->restart_data, (unsigned long) data); 334 mem_assign_absolute(lc->restart_source, source_cpu); 335 __bpon(); 336 asm volatile( 337 "0: sigp 0,%0,%2 # sigp restart to target cpu\n" 338 " brc 2,0b # busy, try again\n" 339 "1: sigp 0,%1,%3 # sigp stop to current cpu\n" 340 " brc 2,1b # busy, try again\n" 341 : : "d" (pcpu->address), "d" (source_cpu), 342 "K" (SIGP_RESTART), "K" (SIGP_STOP) 343 : "0", "1", "cc"); 344 for (;;) ; 345 } 346 347 /* 348 * Enable additional logical cpus for multi-threading. 349 */ 350 static int pcpu_set_smt(unsigned int mtid) 351 { 352 int cc; 353 354 if (smp_cpu_mtid == mtid) 355 return 0; 356 cc = __pcpu_sigp(0, SIGP_SET_MULTI_THREADING, mtid, NULL); 357 if (cc == 0) { 358 smp_cpu_mtid = mtid; 359 smp_cpu_mt_shift = 0; 360 while (smp_cpu_mtid >= (1U << smp_cpu_mt_shift)) 361 smp_cpu_mt_shift++; 362 pcpu_devices[0].address = stap(); 363 } 364 return cc; 365 } 366 367 /* 368 * Call function on an online CPU. 369 */ 370 void smp_call_online_cpu(void (*func)(void *), void *data) 371 { 372 struct pcpu *pcpu; 373 374 /* Use the current cpu if it is online. */ 375 pcpu = pcpu_find_address(cpu_online_mask, stap()); 376 if (!pcpu) 377 /* Use the first online cpu. */ 378 pcpu = pcpu_devices + cpumask_first(cpu_online_mask); 379 pcpu_delegate(pcpu, func, data, (unsigned long) restart_stack); 380 } 381 382 /* 383 * Call function on the ipl CPU. 384 */ 385 void smp_call_ipl_cpu(void (*func)(void *), void *data) 386 { 387 struct lowcore *lc = lowcore_ptr[0]; 388 389 if (pcpu_devices[0].address == stap()) 390 lc = &S390_lowcore; 391 392 pcpu_delegate(&pcpu_devices[0], func, data, 393 lc->nodat_stack); 394 } 395 396 int smp_find_processor_id(u16 address) 397 { 398 int cpu; 399 400 for_each_present_cpu(cpu) 401 if (pcpu_devices[cpu].address == address) 402 return cpu; 403 return -1; 404 } 405 406 void schedule_mcck_handler(void) 407 { 408 pcpu_ec_call(pcpu_devices + smp_processor_id(), ec_mcck_pending); 409 } 410 411 bool notrace arch_vcpu_is_preempted(int cpu) 412 { 413 if (test_cpu_flag_of(CIF_ENABLED_WAIT, cpu)) 414 return false; 415 if (pcpu_running(pcpu_devices + cpu)) 416 return false; 417 return true; 418 } 419 EXPORT_SYMBOL(arch_vcpu_is_preempted); 420 421 void notrace smp_yield_cpu(int cpu) 422 { 423 if (!MACHINE_HAS_DIAG9C) 424 return; 425 diag_stat_inc_norecursion(DIAG_STAT_X09C); 426 asm volatile("diag %0,0,0x9c" 427 : : "d" (pcpu_devices[cpu].address)); 428 } 429 EXPORT_SYMBOL_GPL(smp_yield_cpu); 430 431 /* 432 * Send cpus emergency shutdown signal. This gives the cpus the 433 * opportunity to complete outstanding interrupts. 434 */ 435 void notrace smp_emergency_stop(void) 436 { 437 static arch_spinlock_t lock = __ARCH_SPIN_LOCK_UNLOCKED; 438 static cpumask_t cpumask; 439 u64 end; 440 int cpu; 441 442 arch_spin_lock(&lock); 443 cpumask_copy(&cpumask, cpu_online_mask); 444 cpumask_clear_cpu(smp_processor_id(), &cpumask); 445 446 end = get_tod_clock() + (1000000UL << 12); 447 for_each_cpu(cpu, &cpumask) { 448 struct pcpu *pcpu = pcpu_devices + cpu; 449 set_bit(ec_stop_cpu, &pcpu->ec_mask); 450 while (__pcpu_sigp(pcpu->address, SIGP_EMERGENCY_SIGNAL, 451 0, NULL) == SIGP_CC_BUSY && 452 get_tod_clock() < end) 453 cpu_relax(); 454 } 455 while (get_tod_clock() < end) { 456 for_each_cpu(cpu, &cpumask) 457 if (pcpu_stopped(pcpu_devices + cpu)) 458 cpumask_clear_cpu(cpu, &cpumask); 459 if (cpumask_empty(&cpumask)) 460 break; 461 cpu_relax(); 462 } 463 arch_spin_unlock(&lock); 464 } 465 NOKPROBE_SYMBOL(smp_emergency_stop); 466 467 /* 468 * Stop all cpus but the current one. 469 */ 470 void smp_send_stop(void) 471 { 472 int cpu; 473 474 /* Disable all interrupts/machine checks */ 475 __load_psw_mask(PSW_KERNEL_BITS | PSW_MASK_DAT); 476 trace_hardirqs_off(); 477 478 debug_set_critical(); 479 480 if (oops_in_progress) 481 smp_emergency_stop(); 482 483 /* stop all processors */ 484 for_each_online_cpu(cpu) { 485 if (cpu == smp_processor_id()) 486 continue; 487 pcpu_sigp_retry(pcpu_devices + cpu, SIGP_STOP, 0); 488 while (!pcpu_stopped(pcpu_devices + cpu)) 489 cpu_relax(); 490 } 491 } 492 493 /* 494 * This is the main routine where commands issued by other 495 * cpus are handled. 496 */ 497 static void smp_handle_ext_call(void) 498 { 499 unsigned long bits; 500 501 /* handle bit signal external calls */ 502 bits = xchg(&pcpu_devices[smp_processor_id()].ec_mask, 0); 503 if (test_bit(ec_stop_cpu, &bits)) 504 smp_stop_cpu(); 505 if (test_bit(ec_schedule, &bits)) 506 scheduler_ipi(); 507 if (test_bit(ec_call_function_single, &bits)) 508 generic_smp_call_function_single_interrupt(); 509 if (test_bit(ec_mcck_pending, &bits)) 510 __s390_handle_mcck(); 511 if (test_bit(ec_irq_work, &bits)) 512 irq_work_run(); 513 } 514 515 static void do_ext_call_interrupt(struct ext_code ext_code, 516 unsigned int param32, unsigned long param64) 517 { 518 inc_irq_stat(ext_code.code == 0x1202 ? IRQEXT_EXC : IRQEXT_EMS); 519 smp_handle_ext_call(); 520 } 521 522 void arch_send_call_function_ipi_mask(const struct cpumask *mask) 523 { 524 int cpu; 525 526 for_each_cpu(cpu, mask) 527 pcpu_ec_call(pcpu_devices + cpu, ec_call_function_single); 528 } 529 530 void arch_send_call_function_single_ipi(int cpu) 531 { 532 pcpu_ec_call(pcpu_devices + cpu, ec_call_function_single); 533 } 534 535 /* 536 * this function sends a 'reschedule' IPI to another CPU. 537 * it goes straight through and wastes no time serializing 538 * anything. Worst case is that we lose a reschedule ... 539 */ 540 void smp_send_reschedule(int cpu) 541 { 542 pcpu_ec_call(pcpu_devices + cpu, ec_schedule); 543 } 544 545 #ifdef CONFIG_IRQ_WORK 546 void arch_irq_work_raise(void) 547 { 548 pcpu_ec_call(pcpu_devices + smp_processor_id(), ec_irq_work); 549 } 550 #endif 551 552 /* 553 * parameter area for the set/clear control bit callbacks 554 */ 555 struct ec_creg_mask_parms { 556 unsigned long orval; 557 unsigned long andval; 558 int cr; 559 }; 560 561 /* 562 * callback for setting/clearing control bits 563 */ 564 static void smp_ctl_bit_callback(void *info) 565 { 566 struct ec_creg_mask_parms *pp = info; 567 unsigned long cregs[16]; 568 569 __ctl_store(cregs, 0, 15); 570 cregs[pp->cr] = (cregs[pp->cr] & pp->andval) | pp->orval; 571 __ctl_load(cregs, 0, 15); 572 } 573 574 static DEFINE_SPINLOCK(ctl_lock); 575 static unsigned long ctlreg; 576 577 /* 578 * Set a bit in a control register of all cpus 579 */ 580 void smp_ctl_set_bit(int cr, int bit) 581 { 582 struct ec_creg_mask_parms parms = { 1UL << bit, -1UL, cr }; 583 584 spin_lock(&ctl_lock); 585 memcpy_absolute(&ctlreg, &S390_lowcore.cregs_save_area[cr], sizeof(ctlreg)); 586 __set_bit(bit, &ctlreg); 587 memcpy_absolute(&S390_lowcore.cregs_save_area[cr], &ctlreg, sizeof(ctlreg)); 588 spin_unlock(&ctl_lock); 589 on_each_cpu(smp_ctl_bit_callback, &parms, 1); 590 } 591 EXPORT_SYMBOL(smp_ctl_set_bit); 592 593 /* 594 * Clear a bit in a control register of all cpus 595 */ 596 void smp_ctl_clear_bit(int cr, int bit) 597 { 598 struct ec_creg_mask_parms parms = { 0, ~(1UL << bit), cr }; 599 600 spin_lock(&ctl_lock); 601 memcpy_absolute(&ctlreg, &S390_lowcore.cregs_save_area[cr], sizeof(ctlreg)); 602 __clear_bit(bit, &ctlreg); 603 memcpy_absolute(&S390_lowcore.cregs_save_area[cr], &ctlreg, sizeof(ctlreg)); 604 spin_unlock(&ctl_lock); 605 on_each_cpu(smp_ctl_bit_callback, &parms, 1); 606 } 607 EXPORT_SYMBOL(smp_ctl_clear_bit); 608 609 #ifdef CONFIG_CRASH_DUMP 610 611 int smp_store_status(int cpu) 612 { 613 struct lowcore *lc; 614 struct pcpu *pcpu; 615 unsigned long pa; 616 617 pcpu = pcpu_devices + cpu; 618 lc = lowcore_ptr[cpu]; 619 pa = __pa(&lc->floating_pt_save_area); 620 if (__pcpu_sigp_relax(pcpu->address, SIGP_STORE_STATUS_AT_ADDRESS, 621 pa) != SIGP_CC_ORDER_CODE_ACCEPTED) 622 return -EIO; 623 if (!MACHINE_HAS_VX && !MACHINE_HAS_GS) 624 return 0; 625 pa = __pa(lc->mcesad & MCESA_ORIGIN_MASK); 626 if (MACHINE_HAS_GS) 627 pa |= lc->mcesad & MCESA_LC_MASK; 628 if (__pcpu_sigp_relax(pcpu->address, SIGP_STORE_ADDITIONAL_STATUS, 629 pa) != SIGP_CC_ORDER_CODE_ACCEPTED) 630 return -EIO; 631 return 0; 632 } 633 634 /* 635 * Collect CPU state of the previous, crashed system. 636 * There are four cases: 637 * 1) standard zfcp/nvme dump 638 * condition: OLDMEM_BASE == NULL && is_ipl_type_dump() == true 639 * The state for all CPUs except the boot CPU needs to be collected 640 * with sigp stop-and-store-status. The boot CPU state is located in 641 * the absolute lowcore of the memory stored in the HSA. The zcore code 642 * will copy the boot CPU state from the HSA. 643 * 2) stand-alone kdump for SCSI/NVMe (zfcp/nvme dump with swapped memory) 644 * condition: OLDMEM_BASE != NULL && is_ipl_type_dump() == true 645 * The state for all CPUs except the boot CPU needs to be collected 646 * with sigp stop-and-store-status. The firmware or the boot-loader 647 * stored the registers of the boot CPU in the absolute lowcore in the 648 * memory of the old system. 649 * 3) kdump and the old kernel did not store the CPU state, 650 * or stand-alone kdump for DASD 651 * condition: OLDMEM_BASE != NULL && !is_kdump_kernel() 652 * The state for all CPUs except the boot CPU needs to be collected 653 * with sigp stop-and-store-status. The kexec code or the boot-loader 654 * stored the registers of the boot CPU in the memory of the old system. 655 * 4) kdump and the old kernel stored the CPU state 656 * condition: OLDMEM_BASE != NULL && is_kdump_kernel() 657 * This case does not exist for s390 anymore, setup_arch explicitly 658 * deactivates the elfcorehdr= kernel parameter 659 */ 660 static __init void smp_save_cpu_vxrs(struct save_area *sa, u16 addr, 661 bool is_boot_cpu, unsigned long page) 662 { 663 __vector128 *vxrs = (__vector128 *) page; 664 665 if (is_boot_cpu) 666 vxrs = boot_cpu_vector_save_area; 667 else 668 __pcpu_sigp_relax(addr, SIGP_STORE_ADDITIONAL_STATUS, page); 669 save_area_add_vxrs(sa, vxrs); 670 } 671 672 static __init void smp_save_cpu_regs(struct save_area *sa, u16 addr, 673 bool is_boot_cpu, unsigned long page) 674 { 675 void *regs = (void *) page; 676 677 if (is_boot_cpu) 678 copy_oldmem_kernel(regs, (void *) __LC_FPREGS_SAVE_AREA, 512); 679 else 680 __pcpu_sigp_relax(addr, SIGP_STORE_STATUS_AT_ADDRESS, page); 681 save_area_add_regs(sa, regs); 682 } 683 684 void __init smp_save_dump_cpus(void) 685 { 686 int addr, boot_cpu_addr, max_cpu_addr; 687 struct save_area *sa; 688 unsigned long page; 689 bool is_boot_cpu; 690 691 if (!(oldmem_data.start || is_ipl_type_dump())) 692 /* No previous system present, normal boot. */ 693 return; 694 /* Allocate a page as dumping area for the store status sigps */ 695 page = memblock_phys_alloc_range(PAGE_SIZE, PAGE_SIZE, 0, 1UL << 31); 696 if (!page) 697 panic("ERROR: Failed to allocate %lx bytes below %lx\n", 698 PAGE_SIZE, 1UL << 31); 699 700 /* Set multi-threading state to the previous system. */ 701 pcpu_set_smt(sclp.mtid_prev); 702 boot_cpu_addr = stap(); 703 max_cpu_addr = SCLP_MAX_CORES << sclp.mtid_prev; 704 for (addr = 0; addr <= max_cpu_addr; addr++) { 705 if (__pcpu_sigp_relax(addr, SIGP_SENSE, 0) == 706 SIGP_CC_NOT_OPERATIONAL) 707 continue; 708 is_boot_cpu = (addr == boot_cpu_addr); 709 /* Allocate save area */ 710 sa = save_area_alloc(is_boot_cpu); 711 if (!sa) 712 panic("could not allocate memory for save area\n"); 713 if (MACHINE_HAS_VX) 714 /* Get the vector registers */ 715 smp_save_cpu_vxrs(sa, addr, is_boot_cpu, page); 716 /* 717 * For a zfcp/nvme dump OLDMEM_BASE == NULL and the registers 718 * of the boot CPU are stored in the HSA. To retrieve 719 * these registers an SCLP request is required which is 720 * done by drivers/s390/char/zcore.c:init_cpu_info() 721 */ 722 if (!is_boot_cpu || oldmem_data.start) 723 /* Get the CPU registers */ 724 smp_save_cpu_regs(sa, addr, is_boot_cpu, page); 725 } 726 memblock_phys_free(page, PAGE_SIZE); 727 diag_amode31_ops.diag308_reset(); 728 pcpu_set_smt(0); 729 } 730 #endif /* CONFIG_CRASH_DUMP */ 731 732 void smp_cpu_set_polarization(int cpu, int val) 733 { 734 pcpu_devices[cpu].polarization = val; 735 } 736 737 int smp_cpu_get_polarization(int cpu) 738 { 739 return pcpu_devices[cpu].polarization; 740 } 741 742 int smp_cpu_get_cpu_address(int cpu) 743 { 744 return pcpu_devices[cpu].address; 745 } 746 747 static void __ref smp_get_core_info(struct sclp_core_info *info, int early) 748 { 749 static int use_sigp_detection; 750 int address; 751 752 if (use_sigp_detection || sclp_get_core_info(info, early)) { 753 use_sigp_detection = 1; 754 for (address = 0; 755 address < (SCLP_MAX_CORES << smp_cpu_mt_shift); 756 address += (1U << smp_cpu_mt_shift)) { 757 if (__pcpu_sigp_relax(address, SIGP_SENSE, 0) == 758 SIGP_CC_NOT_OPERATIONAL) 759 continue; 760 info->core[info->configured].core_id = 761 address >> smp_cpu_mt_shift; 762 info->configured++; 763 } 764 info->combined = info->configured; 765 } 766 } 767 768 static int smp_add_present_cpu(int cpu); 769 770 static int smp_add_core(struct sclp_core_entry *core, cpumask_t *avail, 771 bool configured, bool early) 772 { 773 struct pcpu *pcpu; 774 int cpu, nr, i; 775 u16 address; 776 777 nr = 0; 778 if (sclp.has_core_type && core->type != boot_core_type) 779 return nr; 780 cpu = cpumask_first(avail); 781 address = core->core_id << smp_cpu_mt_shift; 782 for (i = 0; (i <= smp_cpu_mtid) && (cpu < nr_cpu_ids); i++) { 783 if (pcpu_find_address(cpu_present_mask, address + i)) 784 continue; 785 pcpu = pcpu_devices + cpu; 786 pcpu->address = address + i; 787 if (configured) 788 pcpu->state = CPU_STATE_CONFIGURED; 789 else 790 pcpu->state = CPU_STATE_STANDBY; 791 smp_cpu_set_polarization(cpu, POLARIZATION_UNKNOWN); 792 set_cpu_present(cpu, true); 793 if (!early && smp_add_present_cpu(cpu) != 0) 794 set_cpu_present(cpu, false); 795 else 796 nr++; 797 cpumask_clear_cpu(cpu, avail); 798 cpu = cpumask_next(cpu, avail); 799 } 800 return nr; 801 } 802 803 static int __smp_rescan_cpus(struct sclp_core_info *info, bool early) 804 { 805 struct sclp_core_entry *core; 806 static cpumask_t avail; 807 bool configured; 808 u16 core_id; 809 int nr, i; 810 811 cpus_read_lock(); 812 mutex_lock(&smp_cpu_state_mutex); 813 nr = 0; 814 cpumask_xor(&avail, cpu_possible_mask, cpu_present_mask); 815 /* 816 * Add IPL core first (which got logical CPU number 0) to make sure 817 * that all SMT threads get subsequent logical CPU numbers. 818 */ 819 if (early) { 820 core_id = pcpu_devices[0].address >> smp_cpu_mt_shift; 821 for (i = 0; i < info->configured; i++) { 822 core = &info->core[i]; 823 if (core->core_id == core_id) { 824 nr += smp_add_core(core, &avail, true, early); 825 break; 826 } 827 } 828 } 829 for (i = 0; i < info->combined; i++) { 830 configured = i < info->configured; 831 nr += smp_add_core(&info->core[i], &avail, configured, early); 832 } 833 mutex_unlock(&smp_cpu_state_mutex); 834 cpus_read_unlock(); 835 return nr; 836 } 837 838 void __init smp_detect_cpus(void) 839 { 840 unsigned int cpu, mtid, c_cpus, s_cpus; 841 struct sclp_core_info *info; 842 u16 address; 843 844 /* Get CPU information */ 845 info = memblock_alloc(sizeof(*info), 8); 846 if (!info) 847 panic("%s: Failed to allocate %zu bytes align=0x%x\n", 848 __func__, sizeof(*info), 8); 849 smp_get_core_info(info, 1); 850 /* Find boot CPU type */ 851 if (sclp.has_core_type) { 852 address = stap(); 853 for (cpu = 0; cpu < info->combined; cpu++) 854 if (info->core[cpu].core_id == address) { 855 /* The boot cpu dictates the cpu type. */ 856 boot_core_type = info->core[cpu].type; 857 break; 858 } 859 if (cpu >= info->combined) 860 panic("Could not find boot CPU type"); 861 } 862 863 /* Set multi-threading state for the current system */ 864 mtid = boot_core_type ? sclp.mtid : sclp.mtid_cp; 865 mtid = (mtid < smp_max_threads) ? mtid : smp_max_threads - 1; 866 pcpu_set_smt(mtid); 867 868 /* Print number of CPUs */ 869 c_cpus = s_cpus = 0; 870 for (cpu = 0; cpu < info->combined; cpu++) { 871 if (sclp.has_core_type && 872 info->core[cpu].type != boot_core_type) 873 continue; 874 if (cpu < info->configured) 875 c_cpus += smp_cpu_mtid + 1; 876 else 877 s_cpus += smp_cpu_mtid + 1; 878 } 879 pr_info("%d configured CPUs, %d standby CPUs\n", c_cpus, s_cpus); 880 881 /* Add CPUs present at boot */ 882 __smp_rescan_cpus(info, true); 883 memblock_phys_free((unsigned long)info, sizeof(*info)); 884 } 885 886 /* 887 * Activate a secondary processor. 888 */ 889 static void smp_start_secondary(void *cpuvoid) 890 { 891 int cpu = raw_smp_processor_id(); 892 893 S390_lowcore.last_update_clock = get_tod_clock(); 894 S390_lowcore.restart_stack = (unsigned long)restart_stack; 895 S390_lowcore.restart_fn = (unsigned long)do_restart; 896 S390_lowcore.restart_data = 0; 897 S390_lowcore.restart_source = -1U; 898 S390_lowcore.restart_flags = 0; 899 restore_access_regs(S390_lowcore.access_regs_save_area); 900 cpu_init(); 901 rcu_cpu_starting(cpu); 902 init_cpu_timer(); 903 vtime_init(); 904 vdso_getcpu_init(); 905 pfault_init(); 906 cpumask_set_cpu(cpu, &cpu_setup_mask); 907 update_cpu_masks(); 908 notify_cpu_starting(cpu); 909 if (topology_cpu_dedicated(cpu)) 910 set_cpu_flag(CIF_DEDICATED_CPU); 911 else 912 clear_cpu_flag(CIF_DEDICATED_CPU); 913 set_cpu_online(cpu, true); 914 inc_irq_stat(CPU_RST); 915 local_irq_enable(); 916 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE); 917 } 918 919 /* Upping and downing of CPUs */ 920 int __cpu_up(unsigned int cpu, struct task_struct *tidle) 921 { 922 struct pcpu *pcpu = pcpu_devices + cpu; 923 int rc; 924 925 if (pcpu->state != CPU_STATE_CONFIGURED) 926 return -EIO; 927 if (pcpu_sigp_retry(pcpu, SIGP_INITIAL_CPU_RESET, 0) != 928 SIGP_CC_ORDER_CODE_ACCEPTED) 929 return -EIO; 930 931 rc = pcpu_alloc_lowcore(pcpu, cpu); 932 if (rc) 933 return rc; 934 pcpu_prepare_secondary(pcpu, cpu); 935 pcpu_attach_task(pcpu, tidle); 936 pcpu_start_fn(pcpu, smp_start_secondary, NULL); 937 /* Wait until cpu puts itself in the online & active maps */ 938 while (!cpu_online(cpu)) 939 cpu_relax(); 940 return 0; 941 } 942 943 static unsigned int setup_possible_cpus __initdata; 944 945 static int __init _setup_possible_cpus(char *s) 946 { 947 get_option(&s, &setup_possible_cpus); 948 return 0; 949 } 950 early_param("possible_cpus", _setup_possible_cpus); 951 952 int __cpu_disable(void) 953 { 954 unsigned long cregs[16]; 955 int cpu; 956 957 /* Handle possible pending IPIs */ 958 smp_handle_ext_call(); 959 cpu = smp_processor_id(); 960 set_cpu_online(cpu, false); 961 cpumask_clear_cpu(cpu, &cpu_setup_mask); 962 update_cpu_masks(); 963 /* Disable pseudo page faults on this cpu. */ 964 pfault_fini(); 965 /* Disable interrupt sources via control register. */ 966 __ctl_store(cregs, 0, 15); 967 cregs[0] &= ~0x0000ee70UL; /* disable all external interrupts */ 968 cregs[6] &= ~0xff000000UL; /* disable all I/O interrupts */ 969 cregs[14] &= ~0x1f000000UL; /* disable most machine checks */ 970 __ctl_load(cregs, 0, 15); 971 clear_cpu_flag(CIF_NOHZ_DELAY); 972 return 0; 973 } 974 975 void __cpu_die(unsigned int cpu) 976 { 977 struct pcpu *pcpu; 978 979 /* Wait until target cpu is down */ 980 pcpu = pcpu_devices + cpu; 981 while (!pcpu_stopped(pcpu)) 982 cpu_relax(); 983 pcpu_free_lowcore(pcpu); 984 cpumask_clear_cpu(cpu, mm_cpumask(&init_mm)); 985 cpumask_clear_cpu(cpu, &init_mm.context.cpu_attach_mask); 986 } 987 988 void __noreturn cpu_die(void) 989 { 990 idle_task_exit(); 991 __bpon(); 992 pcpu_sigp_retry(pcpu_devices + smp_processor_id(), SIGP_STOP, 0); 993 for (;;) ; 994 } 995 996 void __init smp_fill_possible_mask(void) 997 { 998 unsigned int possible, sclp_max, cpu; 999 1000 sclp_max = max(sclp.mtid, sclp.mtid_cp) + 1; 1001 sclp_max = min(smp_max_threads, sclp_max); 1002 sclp_max = (sclp.max_cores * sclp_max) ?: nr_cpu_ids; 1003 possible = setup_possible_cpus ?: nr_cpu_ids; 1004 possible = min(possible, sclp_max); 1005 for (cpu = 0; cpu < possible && cpu < nr_cpu_ids; cpu++) 1006 set_cpu_possible(cpu, true); 1007 } 1008 1009 void __init smp_prepare_cpus(unsigned int max_cpus) 1010 { 1011 /* request the 0x1201 emergency signal external interrupt */ 1012 if (register_external_irq(EXT_IRQ_EMERGENCY_SIG, do_ext_call_interrupt)) 1013 panic("Couldn't request external interrupt 0x1201"); 1014 /* request the 0x1202 external call external interrupt */ 1015 if (register_external_irq(EXT_IRQ_EXTERNAL_CALL, do_ext_call_interrupt)) 1016 panic("Couldn't request external interrupt 0x1202"); 1017 } 1018 1019 void __init smp_prepare_boot_cpu(void) 1020 { 1021 struct pcpu *pcpu = pcpu_devices; 1022 1023 WARN_ON(!cpu_present(0) || !cpu_online(0)); 1024 pcpu->state = CPU_STATE_CONFIGURED; 1025 S390_lowcore.percpu_offset = __per_cpu_offset[0]; 1026 smp_cpu_set_polarization(0, POLARIZATION_UNKNOWN); 1027 } 1028 1029 void __init smp_setup_processor_id(void) 1030 { 1031 pcpu_devices[0].address = stap(); 1032 S390_lowcore.cpu_nr = 0; 1033 S390_lowcore.spinlock_lockval = arch_spin_lockval(0); 1034 S390_lowcore.spinlock_index = 0; 1035 } 1036 1037 /* 1038 * the frequency of the profiling timer can be changed 1039 * by writing a multiplier value into /proc/profile. 1040 * 1041 * usually you want to run this on all CPUs ;) 1042 */ 1043 int setup_profiling_timer(unsigned int multiplier) 1044 { 1045 return 0; 1046 } 1047 1048 static ssize_t cpu_configure_show(struct device *dev, 1049 struct device_attribute *attr, char *buf) 1050 { 1051 ssize_t count; 1052 1053 mutex_lock(&smp_cpu_state_mutex); 1054 count = sprintf(buf, "%d\n", pcpu_devices[dev->id].state); 1055 mutex_unlock(&smp_cpu_state_mutex); 1056 return count; 1057 } 1058 1059 static ssize_t cpu_configure_store(struct device *dev, 1060 struct device_attribute *attr, 1061 const char *buf, size_t count) 1062 { 1063 struct pcpu *pcpu; 1064 int cpu, val, rc, i; 1065 char delim; 1066 1067 if (sscanf(buf, "%d %c", &val, &delim) != 1) 1068 return -EINVAL; 1069 if (val != 0 && val != 1) 1070 return -EINVAL; 1071 cpus_read_lock(); 1072 mutex_lock(&smp_cpu_state_mutex); 1073 rc = -EBUSY; 1074 /* disallow configuration changes of online cpus and cpu 0 */ 1075 cpu = dev->id; 1076 cpu = smp_get_base_cpu(cpu); 1077 if (cpu == 0) 1078 goto out; 1079 for (i = 0; i <= smp_cpu_mtid; i++) 1080 if (cpu_online(cpu + i)) 1081 goto out; 1082 pcpu = pcpu_devices + cpu; 1083 rc = 0; 1084 switch (val) { 1085 case 0: 1086 if (pcpu->state != CPU_STATE_CONFIGURED) 1087 break; 1088 rc = sclp_core_deconfigure(pcpu->address >> smp_cpu_mt_shift); 1089 if (rc) 1090 break; 1091 for (i = 0; i <= smp_cpu_mtid; i++) { 1092 if (cpu + i >= nr_cpu_ids || !cpu_present(cpu + i)) 1093 continue; 1094 pcpu[i].state = CPU_STATE_STANDBY; 1095 smp_cpu_set_polarization(cpu + i, 1096 POLARIZATION_UNKNOWN); 1097 } 1098 topology_expect_change(); 1099 break; 1100 case 1: 1101 if (pcpu->state != CPU_STATE_STANDBY) 1102 break; 1103 rc = sclp_core_configure(pcpu->address >> smp_cpu_mt_shift); 1104 if (rc) 1105 break; 1106 for (i = 0; i <= smp_cpu_mtid; i++) { 1107 if (cpu + i >= nr_cpu_ids || !cpu_present(cpu + i)) 1108 continue; 1109 pcpu[i].state = CPU_STATE_CONFIGURED; 1110 smp_cpu_set_polarization(cpu + i, 1111 POLARIZATION_UNKNOWN); 1112 } 1113 topology_expect_change(); 1114 break; 1115 default: 1116 break; 1117 } 1118 out: 1119 mutex_unlock(&smp_cpu_state_mutex); 1120 cpus_read_unlock(); 1121 return rc ? rc : count; 1122 } 1123 static DEVICE_ATTR(configure, 0644, cpu_configure_show, cpu_configure_store); 1124 1125 static ssize_t show_cpu_address(struct device *dev, 1126 struct device_attribute *attr, char *buf) 1127 { 1128 return sprintf(buf, "%d\n", pcpu_devices[dev->id].address); 1129 } 1130 static DEVICE_ATTR(address, 0444, show_cpu_address, NULL); 1131 1132 static struct attribute *cpu_common_attrs[] = { 1133 &dev_attr_configure.attr, 1134 &dev_attr_address.attr, 1135 NULL, 1136 }; 1137 1138 static struct attribute_group cpu_common_attr_group = { 1139 .attrs = cpu_common_attrs, 1140 }; 1141 1142 static struct attribute *cpu_online_attrs[] = { 1143 &dev_attr_idle_count.attr, 1144 &dev_attr_idle_time_us.attr, 1145 NULL, 1146 }; 1147 1148 static struct attribute_group cpu_online_attr_group = { 1149 .attrs = cpu_online_attrs, 1150 }; 1151 1152 static int smp_cpu_online(unsigned int cpu) 1153 { 1154 struct device *s = &per_cpu(cpu_device, cpu)->dev; 1155 1156 return sysfs_create_group(&s->kobj, &cpu_online_attr_group); 1157 } 1158 1159 static int smp_cpu_pre_down(unsigned int cpu) 1160 { 1161 struct device *s = &per_cpu(cpu_device, cpu)->dev; 1162 1163 sysfs_remove_group(&s->kobj, &cpu_online_attr_group); 1164 return 0; 1165 } 1166 1167 static int smp_add_present_cpu(int cpu) 1168 { 1169 struct device *s; 1170 struct cpu *c; 1171 int rc; 1172 1173 c = kzalloc(sizeof(*c), GFP_KERNEL); 1174 if (!c) 1175 return -ENOMEM; 1176 per_cpu(cpu_device, cpu) = c; 1177 s = &c->dev; 1178 c->hotpluggable = 1; 1179 rc = register_cpu(c, cpu); 1180 if (rc) 1181 goto out; 1182 rc = sysfs_create_group(&s->kobj, &cpu_common_attr_group); 1183 if (rc) 1184 goto out_cpu; 1185 rc = topology_cpu_init(c); 1186 if (rc) 1187 goto out_topology; 1188 return 0; 1189 1190 out_topology: 1191 sysfs_remove_group(&s->kobj, &cpu_common_attr_group); 1192 out_cpu: 1193 unregister_cpu(c); 1194 out: 1195 return rc; 1196 } 1197 1198 int __ref smp_rescan_cpus(void) 1199 { 1200 struct sclp_core_info *info; 1201 int nr; 1202 1203 info = kzalloc(sizeof(*info), GFP_KERNEL); 1204 if (!info) 1205 return -ENOMEM; 1206 smp_get_core_info(info, 0); 1207 nr = __smp_rescan_cpus(info, false); 1208 kfree(info); 1209 if (nr) 1210 topology_schedule_update(); 1211 return 0; 1212 } 1213 1214 static ssize_t __ref rescan_store(struct device *dev, 1215 struct device_attribute *attr, 1216 const char *buf, 1217 size_t count) 1218 { 1219 int rc; 1220 1221 rc = lock_device_hotplug_sysfs(); 1222 if (rc) 1223 return rc; 1224 rc = smp_rescan_cpus(); 1225 unlock_device_hotplug(); 1226 return rc ? rc : count; 1227 } 1228 static DEVICE_ATTR_WO(rescan); 1229 1230 static int __init s390_smp_init(void) 1231 { 1232 int cpu, rc = 0; 1233 1234 rc = device_create_file(cpu_subsys.dev_root, &dev_attr_rescan); 1235 if (rc) 1236 return rc; 1237 for_each_present_cpu(cpu) { 1238 rc = smp_add_present_cpu(cpu); 1239 if (rc) 1240 goto out; 1241 } 1242 1243 rc = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "s390/smp:online", 1244 smp_cpu_online, smp_cpu_pre_down); 1245 rc = rc <= 0 ? rc : 0; 1246 out: 1247 return rc; 1248 } 1249 subsys_initcall(s390_smp_init); 1250 1251 static __always_inline void set_new_lowcore(struct lowcore *lc) 1252 { 1253 union register_pair dst, src; 1254 u32 pfx; 1255 1256 src.even = (unsigned long) &S390_lowcore; 1257 src.odd = sizeof(S390_lowcore); 1258 dst.even = (unsigned long) lc; 1259 dst.odd = sizeof(*lc); 1260 pfx = (unsigned long) lc; 1261 1262 asm volatile( 1263 " mvcl %[dst],%[src]\n" 1264 " spx %[pfx]\n" 1265 : [dst] "+&d" (dst.pair), [src] "+&d" (src.pair) 1266 : [pfx] "Q" (pfx) 1267 : "memory", "cc"); 1268 } 1269 1270 static int __init smp_reinit_ipl_cpu(void) 1271 { 1272 unsigned long async_stack, nodat_stack, mcck_stack; 1273 struct lowcore *lc, *lc_ipl; 1274 unsigned long flags; 1275 1276 lc_ipl = lowcore_ptr[0]; 1277 lc = (struct lowcore *) __get_free_pages(GFP_KERNEL | GFP_DMA, LC_ORDER); 1278 nodat_stack = __get_free_pages(GFP_KERNEL, THREAD_SIZE_ORDER); 1279 async_stack = stack_alloc(); 1280 mcck_stack = stack_alloc(); 1281 if (!lc || !nodat_stack || !async_stack || !mcck_stack) 1282 panic("Couldn't allocate memory"); 1283 1284 local_irq_save(flags); 1285 local_mcck_disable(); 1286 set_new_lowcore(lc); 1287 S390_lowcore.nodat_stack = nodat_stack + STACK_INIT_OFFSET; 1288 S390_lowcore.async_stack = async_stack + STACK_INIT_OFFSET; 1289 S390_lowcore.mcck_stack = mcck_stack + STACK_INIT_OFFSET; 1290 lowcore_ptr[0] = lc; 1291 local_mcck_enable(); 1292 local_irq_restore(flags); 1293 1294 free_pages(lc_ipl->async_stack - STACK_INIT_OFFSET, THREAD_SIZE_ORDER); 1295 memblock_free_late(lc_ipl->mcck_stack - STACK_INIT_OFFSET, THREAD_SIZE); 1296 memblock_free_late((unsigned long) lc_ipl, sizeof(*lc_ipl)); 1297 1298 return 0; 1299 } 1300 early_initcall(smp_reinit_ipl_cpu); 1301