1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * SMP related functions 4 * 5 * Copyright IBM Corp. 1999, 2012 6 * Author(s): Denis Joseph Barrow, 7 * Martin Schwidefsky <schwidefsky@de.ibm.com>, 8 * Heiko Carstens <heiko.carstens@de.ibm.com>, 9 * 10 * based on other smp stuff by 11 * (c) 1995 Alan Cox, CymruNET Ltd <alan@cymru.net> 12 * (c) 1998 Ingo Molnar 13 * 14 * The code outside of smp.c uses logical cpu numbers, only smp.c does 15 * the translation of logical to physical cpu ids. All new code that 16 * operates on physical cpu numbers needs to go into smp.c. 17 */ 18 19 #define KMSG_COMPONENT "cpu" 20 #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt 21 22 #include <linux/workqueue.h> 23 #include <linux/memblock.h> 24 #include <linux/export.h> 25 #include <linux/init.h> 26 #include <linux/mm.h> 27 #include <linux/err.h> 28 #include <linux/spinlock.h> 29 #include <linux/kernel_stat.h> 30 #include <linux/delay.h> 31 #include <linux/interrupt.h> 32 #include <linux/irqflags.h> 33 #include <linux/irq_work.h> 34 #include <linux/cpu.h> 35 #include <linux/slab.h> 36 #include <linux/sched/hotplug.h> 37 #include <linux/sched/task_stack.h> 38 #include <linux/crash_dump.h> 39 #include <linux/kprobes.h> 40 #include <asm/asm-offsets.h> 41 #include <asm/diag.h> 42 #include <asm/switch_to.h> 43 #include <asm/facility.h> 44 #include <asm/ipl.h> 45 #include <asm/setup.h> 46 #include <asm/irq.h> 47 #include <asm/tlbflush.h> 48 #include <asm/vtimer.h> 49 #include <asm/lowcore.h> 50 #include <asm/sclp.h> 51 #include <asm/debug.h> 52 #include <asm/os_info.h> 53 #include <asm/sigp.h> 54 #include <asm/idle.h> 55 #include <asm/nmi.h> 56 #include <asm/stacktrace.h> 57 #include <asm/topology.h> 58 #include <asm/vdso.h> 59 #include "entry.h" 60 61 enum { 62 ec_schedule = 0, 63 ec_call_function_single, 64 ec_stop_cpu, 65 ec_mcck_pending, 66 ec_irq_work, 67 }; 68 69 enum { 70 CPU_STATE_STANDBY, 71 CPU_STATE_CONFIGURED, 72 }; 73 74 static DEFINE_PER_CPU(struct cpu *, cpu_device); 75 76 struct pcpu { 77 unsigned long ec_mask; /* bit mask for ec_xxx functions */ 78 unsigned long ec_clk; /* sigp timestamp for ec_xxx */ 79 signed char state; /* physical cpu state */ 80 signed char polarization; /* physical polarization */ 81 u16 address; /* physical cpu address */ 82 }; 83 84 static u8 boot_core_type; 85 static struct pcpu pcpu_devices[NR_CPUS]; 86 87 unsigned int smp_cpu_mt_shift; 88 EXPORT_SYMBOL(smp_cpu_mt_shift); 89 90 unsigned int smp_cpu_mtid; 91 EXPORT_SYMBOL(smp_cpu_mtid); 92 93 #ifdef CONFIG_CRASH_DUMP 94 __vector128 __initdata boot_cpu_vector_save_area[__NUM_VXRS]; 95 #endif 96 97 static unsigned int smp_max_threads __initdata = -1U; 98 99 static int __init early_nosmt(char *s) 100 { 101 smp_max_threads = 1; 102 return 0; 103 } 104 early_param("nosmt", early_nosmt); 105 106 static int __init early_smt(char *s) 107 { 108 get_option(&s, &smp_max_threads); 109 return 0; 110 } 111 early_param("smt", early_smt); 112 113 /* 114 * The smp_cpu_state_mutex must be held when changing the state or polarization 115 * member of a pcpu data structure within the pcpu_devices arreay. 116 */ 117 DEFINE_MUTEX(smp_cpu_state_mutex); 118 119 /* 120 * Signal processor helper functions. 121 */ 122 static inline int __pcpu_sigp_relax(u16 addr, u8 order, unsigned long parm) 123 { 124 int cc; 125 126 while (1) { 127 cc = __pcpu_sigp(addr, order, parm, NULL); 128 if (cc != SIGP_CC_BUSY) 129 return cc; 130 cpu_relax(); 131 } 132 } 133 134 static int pcpu_sigp_retry(struct pcpu *pcpu, u8 order, u32 parm) 135 { 136 int cc, retry; 137 138 for (retry = 0; ; retry++) { 139 cc = __pcpu_sigp(pcpu->address, order, parm, NULL); 140 if (cc != SIGP_CC_BUSY) 141 break; 142 if (retry >= 3) 143 udelay(10); 144 } 145 return cc; 146 } 147 148 static inline int pcpu_stopped(struct pcpu *pcpu) 149 { 150 u32 status; 151 152 if (__pcpu_sigp(pcpu->address, SIGP_SENSE, 153 0, &status) != SIGP_CC_STATUS_STORED) 154 return 0; 155 return !!(status & (SIGP_STATUS_CHECK_STOP|SIGP_STATUS_STOPPED)); 156 } 157 158 static inline int pcpu_running(struct pcpu *pcpu) 159 { 160 if (__pcpu_sigp(pcpu->address, SIGP_SENSE_RUNNING, 161 0, NULL) != SIGP_CC_STATUS_STORED) 162 return 1; 163 /* Status stored condition code is equivalent to cpu not running. */ 164 return 0; 165 } 166 167 /* 168 * Find struct pcpu by cpu address. 169 */ 170 static struct pcpu *pcpu_find_address(const struct cpumask *mask, u16 address) 171 { 172 int cpu; 173 174 for_each_cpu(cpu, mask) 175 if (pcpu_devices[cpu].address == address) 176 return pcpu_devices + cpu; 177 return NULL; 178 } 179 180 static void pcpu_ec_call(struct pcpu *pcpu, int ec_bit) 181 { 182 int order; 183 184 if (test_and_set_bit(ec_bit, &pcpu->ec_mask)) 185 return; 186 order = pcpu_running(pcpu) ? SIGP_EXTERNAL_CALL : SIGP_EMERGENCY_SIGNAL; 187 pcpu->ec_clk = get_tod_clock_fast(); 188 pcpu_sigp_retry(pcpu, order, 0); 189 } 190 191 static int pcpu_alloc_lowcore(struct pcpu *pcpu, int cpu) 192 { 193 unsigned long async_stack, nodat_stack, mcck_stack; 194 struct lowcore *lc; 195 196 lc = (struct lowcore *) __get_free_pages(GFP_KERNEL | GFP_DMA, LC_ORDER); 197 nodat_stack = __get_free_pages(GFP_KERNEL, THREAD_SIZE_ORDER); 198 async_stack = stack_alloc(); 199 mcck_stack = stack_alloc(); 200 if (!lc || !nodat_stack || !async_stack || !mcck_stack) 201 goto out; 202 memcpy(lc, &S390_lowcore, 512); 203 memset((char *) lc + 512, 0, sizeof(*lc) - 512); 204 lc->async_stack = async_stack + STACK_INIT_OFFSET; 205 lc->nodat_stack = nodat_stack + STACK_INIT_OFFSET; 206 lc->mcck_stack = mcck_stack + STACK_INIT_OFFSET; 207 lc->cpu_nr = cpu; 208 lc->spinlock_lockval = arch_spin_lockval(cpu); 209 lc->spinlock_index = 0; 210 lc->br_r1_trampoline = 0x07f1; /* br %r1 */ 211 lc->return_lpswe = gen_lpswe(__LC_RETURN_PSW); 212 lc->return_mcck_lpswe = gen_lpswe(__LC_RETURN_MCCK_PSW); 213 if (nmi_alloc_per_cpu(lc)) 214 goto out; 215 lowcore_ptr[cpu] = lc; 216 pcpu_sigp_retry(pcpu, SIGP_SET_PREFIX, (u32)(unsigned long) lc); 217 return 0; 218 219 out: 220 stack_free(mcck_stack); 221 stack_free(async_stack); 222 free_pages(nodat_stack, THREAD_SIZE_ORDER); 223 free_pages((unsigned long) lc, LC_ORDER); 224 return -ENOMEM; 225 } 226 227 static void pcpu_free_lowcore(struct pcpu *pcpu) 228 { 229 unsigned long async_stack, nodat_stack, mcck_stack; 230 struct lowcore *lc; 231 int cpu; 232 233 cpu = pcpu - pcpu_devices; 234 lc = lowcore_ptr[cpu]; 235 nodat_stack = lc->nodat_stack - STACK_INIT_OFFSET; 236 async_stack = lc->async_stack - STACK_INIT_OFFSET; 237 mcck_stack = lc->mcck_stack - STACK_INIT_OFFSET; 238 pcpu_sigp_retry(pcpu, SIGP_SET_PREFIX, 0); 239 lowcore_ptr[cpu] = NULL; 240 nmi_free_per_cpu(lc); 241 stack_free(async_stack); 242 stack_free(mcck_stack); 243 free_pages(nodat_stack, THREAD_SIZE_ORDER); 244 free_pages((unsigned long) lc, LC_ORDER); 245 } 246 247 static void pcpu_prepare_secondary(struct pcpu *pcpu, int cpu) 248 { 249 struct lowcore *lc = lowcore_ptr[cpu]; 250 251 cpumask_set_cpu(cpu, &init_mm.context.cpu_attach_mask); 252 cpumask_set_cpu(cpu, mm_cpumask(&init_mm)); 253 lc->cpu_nr = cpu; 254 lc->spinlock_lockval = arch_spin_lockval(cpu); 255 lc->spinlock_index = 0; 256 lc->percpu_offset = __per_cpu_offset[cpu]; 257 lc->kernel_asce = S390_lowcore.kernel_asce; 258 lc->user_asce = s390_invalid_asce; 259 lc->machine_flags = S390_lowcore.machine_flags; 260 lc->user_timer = lc->system_timer = 261 lc->steal_timer = lc->avg_steal_timer = 0; 262 __ctl_store(lc->cregs_save_area, 0, 15); 263 lc->cregs_save_area[1] = lc->kernel_asce; 264 lc->cregs_save_area[7] = lc->user_asce; 265 save_access_regs((unsigned int *) lc->access_regs_save_area); 266 arch_spin_lock_setup(cpu); 267 } 268 269 static void pcpu_attach_task(struct pcpu *pcpu, struct task_struct *tsk) 270 { 271 struct lowcore *lc; 272 int cpu; 273 274 cpu = pcpu - pcpu_devices; 275 lc = lowcore_ptr[cpu]; 276 lc->kernel_stack = (unsigned long) task_stack_page(tsk) 277 + THREAD_SIZE - STACK_FRAME_OVERHEAD - sizeof(struct pt_regs); 278 lc->current_task = (unsigned long) tsk; 279 lc->lpp = LPP_MAGIC; 280 lc->current_pid = tsk->pid; 281 lc->user_timer = tsk->thread.user_timer; 282 lc->guest_timer = tsk->thread.guest_timer; 283 lc->system_timer = tsk->thread.system_timer; 284 lc->hardirq_timer = tsk->thread.hardirq_timer; 285 lc->softirq_timer = tsk->thread.softirq_timer; 286 lc->steal_timer = 0; 287 } 288 289 static void pcpu_start_fn(struct pcpu *pcpu, void (*func)(void *), void *data) 290 { 291 struct lowcore *lc; 292 int cpu; 293 294 cpu = pcpu - pcpu_devices; 295 lc = lowcore_ptr[cpu]; 296 lc->restart_stack = lc->nodat_stack; 297 lc->restart_fn = (unsigned long) func; 298 lc->restart_data = (unsigned long) data; 299 lc->restart_source = -1UL; 300 pcpu_sigp_retry(pcpu, SIGP_RESTART, 0); 301 } 302 303 /* 304 * Call function via PSW restart on pcpu and stop the current cpu. 305 */ 306 static void __pcpu_delegate(void (*func)(void*), void *data) 307 { 308 func(data); /* should not return */ 309 } 310 311 static void __no_sanitize_address pcpu_delegate(struct pcpu *pcpu, 312 void (*func)(void *), 313 void *data, unsigned long stack) 314 { 315 struct lowcore *lc = lowcore_ptr[pcpu - pcpu_devices]; 316 unsigned long source_cpu = stap(); 317 318 __load_psw_mask(PSW_KERNEL_BITS | PSW_MASK_DAT); 319 if (pcpu->address == source_cpu) 320 CALL_ON_STACK(__pcpu_delegate, stack, 2, func, data); 321 /* Stop target cpu (if func returns this stops the current cpu). */ 322 pcpu_sigp_retry(pcpu, SIGP_STOP, 0); 323 /* Restart func on the target cpu and stop the current cpu. */ 324 mem_assign_absolute(lc->restart_stack, stack); 325 mem_assign_absolute(lc->restart_fn, (unsigned long) func); 326 mem_assign_absolute(lc->restart_data, (unsigned long) data); 327 mem_assign_absolute(lc->restart_source, source_cpu); 328 __bpon(); 329 asm volatile( 330 "0: sigp 0,%0,%2 # sigp restart to target cpu\n" 331 " brc 2,0b # busy, try again\n" 332 "1: sigp 0,%1,%3 # sigp stop to current cpu\n" 333 " brc 2,1b # busy, try again\n" 334 : : "d" (pcpu->address), "d" (source_cpu), 335 "K" (SIGP_RESTART), "K" (SIGP_STOP) 336 : "0", "1", "cc"); 337 for (;;) ; 338 } 339 340 /* 341 * Enable additional logical cpus for multi-threading. 342 */ 343 static int pcpu_set_smt(unsigned int mtid) 344 { 345 int cc; 346 347 if (smp_cpu_mtid == mtid) 348 return 0; 349 cc = __pcpu_sigp(0, SIGP_SET_MULTI_THREADING, mtid, NULL); 350 if (cc == 0) { 351 smp_cpu_mtid = mtid; 352 smp_cpu_mt_shift = 0; 353 while (smp_cpu_mtid >= (1U << smp_cpu_mt_shift)) 354 smp_cpu_mt_shift++; 355 pcpu_devices[0].address = stap(); 356 } 357 return cc; 358 } 359 360 /* 361 * Call function on an online CPU. 362 */ 363 void smp_call_online_cpu(void (*func)(void *), void *data) 364 { 365 struct pcpu *pcpu; 366 367 /* Use the current cpu if it is online. */ 368 pcpu = pcpu_find_address(cpu_online_mask, stap()); 369 if (!pcpu) 370 /* Use the first online cpu. */ 371 pcpu = pcpu_devices + cpumask_first(cpu_online_mask); 372 pcpu_delegate(pcpu, func, data, (unsigned long) restart_stack); 373 } 374 375 /* 376 * Call function on the ipl CPU. 377 */ 378 void smp_call_ipl_cpu(void (*func)(void *), void *data) 379 { 380 struct lowcore *lc = lowcore_ptr[0]; 381 382 if (pcpu_devices[0].address == stap()) 383 lc = &S390_lowcore; 384 385 pcpu_delegate(&pcpu_devices[0], func, data, 386 lc->nodat_stack); 387 } 388 389 int smp_find_processor_id(u16 address) 390 { 391 int cpu; 392 393 for_each_present_cpu(cpu) 394 if (pcpu_devices[cpu].address == address) 395 return cpu; 396 return -1; 397 } 398 399 void schedule_mcck_handler(void) 400 { 401 pcpu_ec_call(pcpu_devices + smp_processor_id(), ec_mcck_pending); 402 } 403 404 bool notrace arch_vcpu_is_preempted(int cpu) 405 { 406 if (test_cpu_flag_of(CIF_ENABLED_WAIT, cpu)) 407 return false; 408 if (pcpu_running(pcpu_devices + cpu)) 409 return false; 410 return true; 411 } 412 EXPORT_SYMBOL(arch_vcpu_is_preempted); 413 414 void notrace smp_yield_cpu(int cpu) 415 { 416 if (!MACHINE_HAS_DIAG9C) 417 return; 418 diag_stat_inc_norecursion(DIAG_STAT_X09C); 419 asm volatile("diag %0,0,0x9c" 420 : : "d" (pcpu_devices[cpu].address)); 421 } 422 EXPORT_SYMBOL_GPL(smp_yield_cpu); 423 424 /* 425 * Send cpus emergency shutdown signal. This gives the cpus the 426 * opportunity to complete outstanding interrupts. 427 */ 428 void notrace smp_emergency_stop(void) 429 { 430 static arch_spinlock_t lock = __ARCH_SPIN_LOCK_UNLOCKED; 431 static cpumask_t cpumask; 432 u64 end; 433 int cpu; 434 435 arch_spin_lock(&lock); 436 cpumask_copy(&cpumask, cpu_online_mask); 437 cpumask_clear_cpu(smp_processor_id(), &cpumask); 438 439 end = get_tod_clock() + (1000000UL << 12); 440 for_each_cpu(cpu, &cpumask) { 441 struct pcpu *pcpu = pcpu_devices + cpu; 442 set_bit(ec_stop_cpu, &pcpu->ec_mask); 443 while (__pcpu_sigp(pcpu->address, SIGP_EMERGENCY_SIGNAL, 444 0, NULL) == SIGP_CC_BUSY && 445 get_tod_clock() < end) 446 cpu_relax(); 447 } 448 while (get_tod_clock() < end) { 449 for_each_cpu(cpu, &cpumask) 450 if (pcpu_stopped(pcpu_devices + cpu)) 451 cpumask_clear_cpu(cpu, &cpumask); 452 if (cpumask_empty(&cpumask)) 453 break; 454 cpu_relax(); 455 } 456 arch_spin_unlock(&lock); 457 } 458 NOKPROBE_SYMBOL(smp_emergency_stop); 459 460 /* 461 * Stop all cpus but the current one. 462 */ 463 void smp_send_stop(void) 464 { 465 int cpu; 466 467 /* Disable all interrupts/machine checks */ 468 __load_psw_mask(PSW_KERNEL_BITS | PSW_MASK_DAT); 469 trace_hardirqs_off(); 470 471 debug_set_critical(); 472 473 if (oops_in_progress) 474 smp_emergency_stop(); 475 476 /* stop all processors */ 477 for_each_online_cpu(cpu) { 478 if (cpu == smp_processor_id()) 479 continue; 480 pcpu_sigp_retry(pcpu_devices + cpu, SIGP_STOP, 0); 481 while (!pcpu_stopped(pcpu_devices + cpu)) 482 cpu_relax(); 483 } 484 } 485 486 /* 487 * This is the main routine where commands issued by other 488 * cpus are handled. 489 */ 490 static void smp_handle_ext_call(void) 491 { 492 unsigned long bits; 493 494 /* handle bit signal external calls */ 495 bits = xchg(&pcpu_devices[smp_processor_id()].ec_mask, 0); 496 if (test_bit(ec_stop_cpu, &bits)) 497 smp_stop_cpu(); 498 if (test_bit(ec_schedule, &bits)) 499 scheduler_ipi(); 500 if (test_bit(ec_call_function_single, &bits)) 501 generic_smp_call_function_single_interrupt(); 502 if (test_bit(ec_mcck_pending, &bits)) 503 __s390_handle_mcck(); 504 if (test_bit(ec_irq_work, &bits)) 505 irq_work_run(); 506 } 507 508 static void do_ext_call_interrupt(struct ext_code ext_code, 509 unsigned int param32, unsigned long param64) 510 { 511 inc_irq_stat(ext_code.code == 0x1202 ? IRQEXT_EXC : IRQEXT_EMS); 512 smp_handle_ext_call(); 513 } 514 515 void arch_send_call_function_ipi_mask(const struct cpumask *mask) 516 { 517 int cpu; 518 519 for_each_cpu(cpu, mask) 520 pcpu_ec_call(pcpu_devices + cpu, ec_call_function_single); 521 } 522 523 void arch_send_call_function_single_ipi(int cpu) 524 { 525 pcpu_ec_call(pcpu_devices + cpu, ec_call_function_single); 526 } 527 528 /* 529 * this function sends a 'reschedule' IPI to another CPU. 530 * it goes straight through and wastes no time serializing 531 * anything. Worst case is that we lose a reschedule ... 532 */ 533 void smp_send_reschedule(int cpu) 534 { 535 pcpu_ec_call(pcpu_devices + cpu, ec_schedule); 536 } 537 538 #ifdef CONFIG_IRQ_WORK 539 void arch_irq_work_raise(void) 540 { 541 pcpu_ec_call(pcpu_devices + smp_processor_id(), ec_irq_work); 542 } 543 #endif 544 545 /* 546 * parameter area for the set/clear control bit callbacks 547 */ 548 struct ec_creg_mask_parms { 549 unsigned long orval; 550 unsigned long andval; 551 int cr; 552 }; 553 554 /* 555 * callback for setting/clearing control bits 556 */ 557 static void smp_ctl_bit_callback(void *info) 558 { 559 struct ec_creg_mask_parms *pp = info; 560 unsigned long cregs[16]; 561 562 __ctl_store(cregs, 0, 15); 563 cregs[pp->cr] = (cregs[pp->cr] & pp->andval) | pp->orval; 564 __ctl_load(cregs, 0, 15); 565 } 566 567 /* 568 * Set a bit in a control register of all cpus 569 */ 570 void smp_ctl_set_bit(int cr, int bit) 571 { 572 struct ec_creg_mask_parms parms = { 1UL << bit, -1UL, cr }; 573 574 on_each_cpu(smp_ctl_bit_callback, &parms, 1); 575 } 576 EXPORT_SYMBOL(smp_ctl_set_bit); 577 578 /* 579 * Clear a bit in a control register of all cpus 580 */ 581 void smp_ctl_clear_bit(int cr, int bit) 582 { 583 struct ec_creg_mask_parms parms = { 0, ~(1UL << bit), cr }; 584 585 on_each_cpu(smp_ctl_bit_callback, &parms, 1); 586 } 587 EXPORT_SYMBOL(smp_ctl_clear_bit); 588 589 #ifdef CONFIG_CRASH_DUMP 590 591 int smp_store_status(int cpu) 592 { 593 struct lowcore *lc; 594 struct pcpu *pcpu; 595 unsigned long pa; 596 597 pcpu = pcpu_devices + cpu; 598 lc = lowcore_ptr[cpu]; 599 pa = __pa(&lc->floating_pt_save_area); 600 if (__pcpu_sigp_relax(pcpu->address, SIGP_STORE_STATUS_AT_ADDRESS, 601 pa) != SIGP_CC_ORDER_CODE_ACCEPTED) 602 return -EIO; 603 if (!MACHINE_HAS_VX && !MACHINE_HAS_GS) 604 return 0; 605 pa = __pa(lc->mcesad & MCESA_ORIGIN_MASK); 606 if (MACHINE_HAS_GS) 607 pa |= lc->mcesad & MCESA_LC_MASK; 608 if (__pcpu_sigp_relax(pcpu->address, SIGP_STORE_ADDITIONAL_STATUS, 609 pa) != SIGP_CC_ORDER_CODE_ACCEPTED) 610 return -EIO; 611 return 0; 612 } 613 614 /* 615 * Collect CPU state of the previous, crashed system. 616 * There are four cases: 617 * 1) standard zfcp/nvme dump 618 * condition: OLDMEM_BASE == NULL && is_ipl_type_dump() == true 619 * The state for all CPUs except the boot CPU needs to be collected 620 * with sigp stop-and-store-status. The boot CPU state is located in 621 * the absolute lowcore of the memory stored in the HSA. The zcore code 622 * will copy the boot CPU state from the HSA. 623 * 2) stand-alone kdump for SCSI/NVMe (zfcp/nvme dump with swapped memory) 624 * condition: OLDMEM_BASE != NULL && is_ipl_type_dump() == true 625 * The state for all CPUs except the boot CPU needs to be collected 626 * with sigp stop-and-store-status. The firmware or the boot-loader 627 * stored the registers of the boot CPU in the absolute lowcore in the 628 * memory of the old system. 629 * 3) kdump and the old kernel did not store the CPU state, 630 * or stand-alone kdump for DASD 631 * condition: OLDMEM_BASE != NULL && !is_kdump_kernel() 632 * The state for all CPUs except the boot CPU needs to be collected 633 * with sigp stop-and-store-status. The kexec code or the boot-loader 634 * stored the registers of the boot CPU in the memory of the old system. 635 * 4) kdump and the old kernel stored the CPU state 636 * condition: OLDMEM_BASE != NULL && is_kdump_kernel() 637 * This case does not exist for s390 anymore, setup_arch explicitly 638 * deactivates the elfcorehdr= kernel parameter 639 */ 640 static __init void smp_save_cpu_vxrs(struct save_area *sa, u16 addr, 641 bool is_boot_cpu, unsigned long page) 642 { 643 __vector128 *vxrs = (__vector128 *) page; 644 645 if (is_boot_cpu) 646 vxrs = boot_cpu_vector_save_area; 647 else 648 __pcpu_sigp_relax(addr, SIGP_STORE_ADDITIONAL_STATUS, page); 649 save_area_add_vxrs(sa, vxrs); 650 } 651 652 static __init void smp_save_cpu_regs(struct save_area *sa, u16 addr, 653 bool is_boot_cpu, unsigned long page) 654 { 655 void *regs = (void *) page; 656 657 if (is_boot_cpu) 658 copy_oldmem_kernel(regs, (void *) __LC_FPREGS_SAVE_AREA, 512); 659 else 660 __pcpu_sigp_relax(addr, SIGP_STORE_STATUS_AT_ADDRESS, page); 661 save_area_add_regs(sa, regs); 662 } 663 664 void __init smp_save_dump_cpus(void) 665 { 666 int addr, boot_cpu_addr, max_cpu_addr; 667 struct save_area *sa; 668 unsigned long page; 669 bool is_boot_cpu; 670 671 if (!(OLDMEM_BASE || is_ipl_type_dump())) 672 /* No previous system present, normal boot. */ 673 return; 674 /* Allocate a page as dumping area for the store status sigps */ 675 page = memblock_phys_alloc_range(PAGE_SIZE, PAGE_SIZE, 0, 1UL << 31); 676 if (!page) 677 panic("ERROR: Failed to allocate %lx bytes below %lx\n", 678 PAGE_SIZE, 1UL << 31); 679 680 /* Set multi-threading state to the previous system. */ 681 pcpu_set_smt(sclp.mtid_prev); 682 boot_cpu_addr = stap(); 683 max_cpu_addr = SCLP_MAX_CORES << sclp.mtid_prev; 684 for (addr = 0; addr <= max_cpu_addr; addr++) { 685 if (__pcpu_sigp_relax(addr, SIGP_SENSE, 0) == 686 SIGP_CC_NOT_OPERATIONAL) 687 continue; 688 is_boot_cpu = (addr == boot_cpu_addr); 689 /* Allocate save area */ 690 sa = save_area_alloc(is_boot_cpu); 691 if (!sa) 692 panic("could not allocate memory for save area\n"); 693 if (MACHINE_HAS_VX) 694 /* Get the vector registers */ 695 smp_save_cpu_vxrs(sa, addr, is_boot_cpu, page); 696 /* 697 * For a zfcp/nvme dump OLDMEM_BASE == NULL and the registers 698 * of the boot CPU are stored in the HSA. To retrieve 699 * these registers an SCLP request is required which is 700 * done by drivers/s390/char/zcore.c:init_cpu_info() 701 */ 702 if (!is_boot_cpu || OLDMEM_BASE) 703 /* Get the CPU registers */ 704 smp_save_cpu_regs(sa, addr, is_boot_cpu, page); 705 } 706 memblock_free(page, PAGE_SIZE); 707 diag_dma_ops.diag308_reset(); 708 pcpu_set_smt(0); 709 } 710 #endif /* CONFIG_CRASH_DUMP */ 711 712 void smp_cpu_set_polarization(int cpu, int val) 713 { 714 pcpu_devices[cpu].polarization = val; 715 } 716 717 int smp_cpu_get_polarization(int cpu) 718 { 719 return pcpu_devices[cpu].polarization; 720 } 721 722 int smp_cpu_get_cpu_address(int cpu) 723 { 724 return pcpu_devices[cpu].address; 725 } 726 727 static void __ref smp_get_core_info(struct sclp_core_info *info, int early) 728 { 729 static int use_sigp_detection; 730 int address; 731 732 if (use_sigp_detection || sclp_get_core_info(info, early)) { 733 use_sigp_detection = 1; 734 for (address = 0; 735 address < (SCLP_MAX_CORES << smp_cpu_mt_shift); 736 address += (1U << smp_cpu_mt_shift)) { 737 if (__pcpu_sigp_relax(address, SIGP_SENSE, 0) == 738 SIGP_CC_NOT_OPERATIONAL) 739 continue; 740 info->core[info->configured].core_id = 741 address >> smp_cpu_mt_shift; 742 info->configured++; 743 } 744 info->combined = info->configured; 745 } 746 } 747 748 static int smp_add_present_cpu(int cpu); 749 750 static int smp_add_core(struct sclp_core_entry *core, cpumask_t *avail, 751 bool configured, bool early) 752 { 753 struct pcpu *pcpu; 754 int cpu, nr, i; 755 u16 address; 756 757 nr = 0; 758 if (sclp.has_core_type && core->type != boot_core_type) 759 return nr; 760 cpu = cpumask_first(avail); 761 address = core->core_id << smp_cpu_mt_shift; 762 for (i = 0; (i <= smp_cpu_mtid) && (cpu < nr_cpu_ids); i++) { 763 if (pcpu_find_address(cpu_present_mask, address + i)) 764 continue; 765 pcpu = pcpu_devices + cpu; 766 pcpu->address = address + i; 767 if (configured) 768 pcpu->state = CPU_STATE_CONFIGURED; 769 else 770 pcpu->state = CPU_STATE_STANDBY; 771 smp_cpu_set_polarization(cpu, POLARIZATION_UNKNOWN); 772 set_cpu_present(cpu, true); 773 if (!early && smp_add_present_cpu(cpu) != 0) 774 set_cpu_present(cpu, false); 775 else 776 nr++; 777 cpumask_clear_cpu(cpu, avail); 778 cpu = cpumask_next(cpu, avail); 779 } 780 return nr; 781 } 782 783 static int __smp_rescan_cpus(struct sclp_core_info *info, bool early) 784 { 785 struct sclp_core_entry *core; 786 static cpumask_t avail; 787 bool configured; 788 u16 core_id; 789 int nr, i; 790 791 get_online_cpus(); 792 mutex_lock(&smp_cpu_state_mutex); 793 nr = 0; 794 cpumask_xor(&avail, cpu_possible_mask, cpu_present_mask); 795 /* 796 * Add IPL core first (which got logical CPU number 0) to make sure 797 * that all SMT threads get subsequent logical CPU numbers. 798 */ 799 if (early) { 800 core_id = pcpu_devices[0].address >> smp_cpu_mt_shift; 801 for (i = 0; i < info->configured; i++) { 802 core = &info->core[i]; 803 if (core->core_id == core_id) { 804 nr += smp_add_core(core, &avail, true, early); 805 break; 806 } 807 } 808 } 809 for (i = 0; i < info->combined; i++) { 810 configured = i < info->configured; 811 nr += smp_add_core(&info->core[i], &avail, configured, early); 812 } 813 mutex_unlock(&smp_cpu_state_mutex); 814 put_online_cpus(); 815 return nr; 816 } 817 818 void __init smp_detect_cpus(void) 819 { 820 unsigned int cpu, mtid, c_cpus, s_cpus; 821 struct sclp_core_info *info; 822 u16 address; 823 824 /* Get CPU information */ 825 info = memblock_alloc(sizeof(*info), 8); 826 if (!info) 827 panic("%s: Failed to allocate %zu bytes align=0x%x\n", 828 __func__, sizeof(*info), 8); 829 smp_get_core_info(info, 1); 830 /* Find boot CPU type */ 831 if (sclp.has_core_type) { 832 address = stap(); 833 for (cpu = 0; cpu < info->combined; cpu++) 834 if (info->core[cpu].core_id == address) { 835 /* The boot cpu dictates the cpu type. */ 836 boot_core_type = info->core[cpu].type; 837 break; 838 } 839 if (cpu >= info->combined) 840 panic("Could not find boot CPU type"); 841 } 842 843 /* Set multi-threading state for the current system */ 844 mtid = boot_core_type ? sclp.mtid : sclp.mtid_cp; 845 mtid = (mtid < smp_max_threads) ? mtid : smp_max_threads - 1; 846 pcpu_set_smt(mtid); 847 848 /* Print number of CPUs */ 849 c_cpus = s_cpus = 0; 850 for (cpu = 0; cpu < info->combined; cpu++) { 851 if (sclp.has_core_type && 852 info->core[cpu].type != boot_core_type) 853 continue; 854 if (cpu < info->configured) 855 c_cpus += smp_cpu_mtid + 1; 856 else 857 s_cpus += smp_cpu_mtid + 1; 858 } 859 pr_info("%d configured CPUs, %d standby CPUs\n", c_cpus, s_cpus); 860 861 /* Add CPUs present at boot */ 862 __smp_rescan_cpus(info, true); 863 memblock_free_early((unsigned long)info, sizeof(*info)); 864 } 865 866 static void smp_init_secondary(void) 867 { 868 int cpu = raw_smp_processor_id(); 869 870 S390_lowcore.last_update_clock = get_tod_clock(); 871 restore_access_regs(S390_lowcore.access_regs_save_area); 872 cpu_init(); 873 rcu_cpu_starting(cpu); 874 init_cpu_timer(); 875 vtime_init(); 876 vdso_getcpu_init(); 877 pfault_init(); 878 notify_cpu_starting(cpu); 879 if (topology_cpu_dedicated(cpu)) 880 set_cpu_flag(CIF_DEDICATED_CPU); 881 else 882 clear_cpu_flag(CIF_DEDICATED_CPU); 883 set_cpu_online(cpu, true); 884 update_cpu_masks(); 885 inc_irq_stat(CPU_RST); 886 local_irq_enable(); 887 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE); 888 } 889 890 /* 891 * Activate a secondary processor. 892 */ 893 static void __no_sanitize_address smp_start_secondary(void *cpuvoid) 894 { 895 S390_lowcore.restart_stack = (unsigned long) restart_stack; 896 S390_lowcore.restart_fn = (unsigned long) do_restart; 897 S390_lowcore.restart_data = 0; 898 S390_lowcore.restart_source = -1UL; 899 __ctl_load(S390_lowcore.cregs_save_area, 0, 15); 900 __load_psw_mask(PSW_KERNEL_BITS | PSW_MASK_DAT); 901 CALL_ON_STACK_NORETURN(smp_init_secondary, S390_lowcore.kernel_stack); 902 } 903 904 /* Upping and downing of CPUs */ 905 int __cpu_up(unsigned int cpu, struct task_struct *tidle) 906 { 907 struct pcpu *pcpu = pcpu_devices + cpu; 908 int rc; 909 910 if (pcpu->state != CPU_STATE_CONFIGURED) 911 return -EIO; 912 if (pcpu_sigp_retry(pcpu, SIGP_INITIAL_CPU_RESET, 0) != 913 SIGP_CC_ORDER_CODE_ACCEPTED) 914 return -EIO; 915 916 rc = pcpu_alloc_lowcore(pcpu, cpu); 917 if (rc) 918 return rc; 919 pcpu_prepare_secondary(pcpu, cpu); 920 pcpu_attach_task(pcpu, tidle); 921 pcpu_start_fn(pcpu, smp_start_secondary, NULL); 922 /* Wait until cpu puts itself in the online & active maps */ 923 while (!cpu_online(cpu)) 924 cpu_relax(); 925 return 0; 926 } 927 928 static unsigned int setup_possible_cpus __initdata; 929 930 static int __init _setup_possible_cpus(char *s) 931 { 932 get_option(&s, &setup_possible_cpus); 933 return 0; 934 } 935 early_param("possible_cpus", _setup_possible_cpus); 936 937 int __cpu_disable(void) 938 { 939 unsigned long cregs[16]; 940 941 /* Handle possible pending IPIs */ 942 smp_handle_ext_call(); 943 set_cpu_online(smp_processor_id(), false); 944 update_cpu_masks(); 945 /* Disable pseudo page faults on this cpu. */ 946 pfault_fini(); 947 /* Disable interrupt sources via control register. */ 948 __ctl_store(cregs, 0, 15); 949 cregs[0] &= ~0x0000ee70UL; /* disable all external interrupts */ 950 cregs[6] &= ~0xff000000UL; /* disable all I/O interrupts */ 951 cregs[14] &= ~0x1f000000UL; /* disable most machine checks */ 952 __ctl_load(cregs, 0, 15); 953 clear_cpu_flag(CIF_NOHZ_DELAY); 954 return 0; 955 } 956 957 void __cpu_die(unsigned int cpu) 958 { 959 struct pcpu *pcpu; 960 961 /* Wait until target cpu is down */ 962 pcpu = pcpu_devices + cpu; 963 while (!pcpu_stopped(pcpu)) 964 cpu_relax(); 965 pcpu_free_lowcore(pcpu); 966 cpumask_clear_cpu(cpu, mm_cpumask(&init_mm)); 967 cpumask_clear_cpu(cpu, &init_mm.context.cpu_attach_mask); 968 } 969 970 void __noreturn cpu_die(void) 971 { 972 idle_task_exit(); 973 __bpon(); 974 pcpu_sigp_retry(pcpu_devices + smp_processor_id(), SIGP_STOP, 0); 975 for (;;) ; 976 } 977 978 void __init smp_fill_possible_mask(void) 979 { 980 unsigned int possible, sclp_max, cpu; 981 982 sclp_max = max(sclp.mtid, sclp.mtid_cp) + 1; 983 sclp_max = min(smp_max_threads, sclp_max); 984 sclp_max = (sclp.max_cores * sclp_max) ?: nr_cpu_ids; 985 possible = setup_possible_cpus ?: nr_cpu_ids; 986 possible = min(possible, sclp_max); 987 for (cpu = 0; cpu < possible && cpu < nr_cpu_ids; cpu++) 988 set_cpu_possible(cpu, true); 989 } 990 991 void __init smp_prepare_cpus(unsigned int max_cpus) 992 { 993 /* request the 0x1201 emergency signal external interrupt */ 994 if (register_external_irq(EXT_IRQ_EMERGENCY_SIG, do_ext_call_interrupt)) 995 panic("Couldn't request external interrupt 0x1201"); 996 /* request the 0x1202 external call external interrupt */ 997 if (register_external_irq(EXT_IRQ_EXTERNAL_CALL, do_ext_call_interrupt)) 998 panic("Couldn't request external interrupt 0x1202"); 999 } 1000 1001 void __init smp_prepare_boot_cpu(void) 1002 { 1003 struct pcpu *pcpu = pcpu_devices; 1004 1005 WARN_ON(!cpu_present(0) || !cpu_online(0)); 1006 pcpu->state = CPU_STATE_CONFIGURED; 1007 S390_lowcore.percpu_offset = __per_cpu_offset[0]; 1008 smp_cpu_set_polarization(0, POLARIZATION_UNKNOWN); 1009 } 1010 1011 void __init smp_setup_processor_id(void) 1012 { 1013 pcpu_devices[0].address = stap(); 1014 S390_lowcore.cpu_nr = 0; 1015 S390_lowcore.spinlock_lockval = arch_spin_lockval(0); 1016 S390_lowcore.spinlock_index = 0; 1017 } 1018 1019 /* 1020 * the frequency of the profiling timer can be changed 1021 * by writing a multiplier value into /proc/profile. 1022 * 1023 * usually you want to run this on all CPUs ;) 1024 */ 1025 int setup_profiling_timer(unsigned int multiplier) 1026 { 1027 return 0; 1028 } 1029 1030 static ssize_t cpu_configure_show(struct device *dev, 1031 struct device_attribute *attr, char *buf) 1032 { 1033 ssize_t count; 1034 1035 mutex_lock(&smp_cpu_state_mutex); 1036 count = sprintf(buf, "%d\n", pcpu_devices[dev->id].state); 1037 mutex_unlock(&smp_cpu_state_mutex); 1038 return count; 1039 } 1040 1041 static ssize_t cpu_configure_store(struct device *dev, 1042 struct device_attribute *attr, 1043 const char *buf, size_t count) 1044 { 1045 struct pcpu *pcpu; 1046 int cpu, val, rc, i; 1047 char delim; 1048 1049 if (sscanf(buf, "%d %c", &val, &delim) != 1) 1050 return -EINVAL; 1051 if (val != 0 && val != 1) 1052 return -EINVAL; 1053 get_online_cpus(); 1054 mutex_lock(&smp_cpu_state_mutex); 1055 rc = -EBUSY; 1056 /* disallow configuration changes of online cpus and cpu 0 */ 1057 cpu = dev->id; 1058 cpu = smp_get_base_cpu(cpu); 1059 if (cpu == 0) 1060 goto out; 1061 for (i = 0; i <= smp_cpu_mtid; i++) 1062 if (cpu_online(cpu + i)) 1063 goto out; 1064 pcpu = pcpu_devices + cpu; 1065 rc = 0; 1066 switch (val) { 1067 case 0: 1068 if (pcpu->state != CPU_STATE_CONFIGURED) 1069 break; 1070 rc = sclp_core_deconfigure(pcpu->address >> smp_cpu_mt_shift); 1071 if (rc) 1072 break; 1073 for (i = 0; i <= smp_cpu_mtid; i++) { 1074 if (cpu + i >= nr_cpu_ids || !cpu_present(cpu + i)) 1075 continue; 1076 pcpu[i].state = CPU_STATE_STANDBY; 1077 smp_cpu_set_polarization(cpu + i, 1078 POLARIZATION_UNKNOWN); 1079 } 1080 topology_expect_change(); 1081 break; 1082 case 1: 1083 if (pcpu->state != CPU_STATE_STANDBY) 1084 break; 1085 rc = sclp_core_configure(pcpu->address >> smp_cpu_mt_shift); 1086 if (rc) 1087 break; 1088 for (i = 0; i <= smp_cpu_mtid; i++) { 1089 if (cpu + i >= nr_cpu_ids || !cpu_present(cpu + i)) 1090 continue; 1091 pcpu[i].state = CPU_STATE_CONFIGURED; 1092 smp_cpu_set_polarization(cpu + i, 1093 POLARIZATION_UNKNOWN); 1094 } 1095 topology_expect_change(); 1096 break; 1097 default: 1098 break; 1099 } 1100 out: 1101 mutex_unlock(&smp_cpu_state_mutex); 1102 put_online_cpus(); 1103 return rc ? rc : count; 1104 } 1105 static DEVICE_ATTR(configure, 0644, cpu_configure_show, cpu_configure_store); 1106 1107 static ssize_t show_cpu_address(struct device *dev, 1108 struct device_attribute *attr, char *buf) 1109 { 1110 return sprintf(buf, "%d\n", pcpu_devices[dev->id].address); 1111 } 1112 static DEVICE_ATTR(address, 0444, show_cpu_address, NULL); 1113 1114 static struct attribute *cpu_common_attrs[] = { 1115 &dev_attr_configure.attr, 1116 &dev_attr_address.attr, 1117 NULL, 1118 }; 1119 1120 static struct attribute_group cpu_common_attr_group = { 1121 .attrs = cpu_common_attrs, 1122 }; 1123 1124 static struct attribute *cpu_online_attrs[] = { 1125 &dev_attr_idle_count.attr, 1126 &dev_attr_idle_time_us.attr, 1127 NULL, 1128 }; 1129 1130 static struct attribute_group cpu_online_attr_group = { 1131 .attrs = cpu_online_attrs, 1132 }; 1133 1134 static int smp_cpu_online(unsigned int cpu) 1135 { 1136 struct device *s = &per_cpu(cpu_device, cpu)->dev; 1137 1138 return sysfs_create_group(&s->kobj, &cpu_online_attr_group); 1139 } 1140 1141 static int smp_cpu_pre_down(unsigned int cpu) 1142 { 1143 struct device *s = &per_cpu(cpu_device, cpu)->dev; 1144 1145 sysfs_remove_group(&s->kobj, &cpu_online_attr_group); 1146 return 0; 1147 } 1148 1149 static int smp_add_present_cpu(int cpu) 1150 { 1151 struct device *s; 1152 struct cpu *c; 1153 int rc; 1154 1155 c = kzalloc(sizeof(*c), GFP_KERNEL); 1156 if (!c) 1157 return -ENOMEM; 1158 per_cpu(cpu_device, cpu) = c; 1159 s = &c->dev; 1160 c->hotpluggable = 1; 1161 rc = register_cpu(c, cpu); 1162 if (rc) 1163 goto out; 1164 rc = sysfs_create_group(&s->kobj, &cpu_common_attr_group); 1165 if (rc) 1166 goto out_cpu; 1167 rc = topology_cpu_init(c); 1168 if (rc) 1169 goto out_topology; 1170 return 0; 1171 1172 out_topology: 1173 sysfs_remove_group(&s->kobj, &cpu_common_attr_group); 1174 out_cpu: 1175 unregister_cpu(c); 1176 out: 1177 return rc; 1178 } 1179 1180 int __ref smp_rescan_cpus(void) 1181 { 1182 struct sclp_core_info *info; 1183 int nr; 1184 1185 info = kzalloc(sizeof(*info), GFP_KERNEL); 1186 if (!info) 1187 return -ENOMEM; 1188 smp_get_core_info(info, 0); 1189 nr = __smp_rescan_cpus(info, false); 1190 kfree(info); 1191 if (nr) 1192 topology_schedule_update(); 1193 return 0; 1194 } 1195 1196 static ssize_t __ref rescan_store(struct device *dev, 1197 struct device_attribute *attr, 1198 const char *buf, 1199 size_t count) 1200 { 1201 int rc; 1202 1203 rc = lock_device_hotplug_sysfs(); 1204 if (rc) 1205 return rc; 1206 rc = smp_rescan_cpus(); 1207 unlock_device_hotplug(); 1208 return rc ? rc : count; 1209 } 1210 static DEVICE_ATTR_WO(rescan); 1211 1212 static int __init s390_smp_init(void) 1213 { 1214 int cpu, rc = 0; 1215 1216 rc = device_create_file(cpu_subsys.dev_root, &dev_attr_rescan); 1217 if (rc) 1218 return rc; 1219 for_each_present_cpu(cpu) { 1220 rc = smp_add_present_cpu(cpu); 1221 if (rc) 1222 goto out; 1223 } 1224 1225 rc = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "s390/smp:online", 1226 smp_cpu_online, smp_cpu_pre_down); 1227 rc = rc <= 0 ? rc : 0; 1228 out: 1229 return rc; 1230 } 1231 subsys_initcall(s390_smp_init); 1232 1233 static __always_inline void set_new_lowcore(struct lowcore *lc) 1234 { 1235 union register_pair dst, src; 1236 u32 pfx; 1237 1238 src.even = (unsigned long) &S390_lowcore; 1239 src.odd = sizeof(S390_lowcore); 1240 dst.even = (unsigned long) lc; 1241 dst.odd = sizeof(*lc); 1242 pfx = (unsigned long) lc; 1243 1244 asm volatile( 1245 " mvcl %[dst],%[src]\n" 1246 " spx %[pfx]\n" 1247 : [dst] "+&d" (dst.pair), [src] "+&d" (src.pair) 1248 : [pfx] "Q" (pfx) 1249 : "memory", "cc"); 1250 } 1251 1252 static int __init smp_reinit_ipl_cpu(void) 1253 { 1254 unsigned long async_stack, nodat_stack, mcck_stack; 1255 struct lowcore *lc, *lc_ipl; 1256 unsigned long flags; 1257 1258 lc_ipl = lowcore_ptr[0]; 1259 lc = (struct lowcore *) __get_free_pages(GFP_KERNEL | GFP_DMA, LC_ORDER); 1260 nodat_stack = __get_free_pages(GFP_KERNEL, THREAD_SIZE_ORDER); 1261 async_stack = stack_alloc(); 1262 mcck_stack = stack_alloc(); 1263 if (!lc || !nodat_stack || !async_stack || !mcck_stack) 1264 panic("Couldn't allocate memory"); 1265 1266 local_irq_save(flags); 1267 local_mcck_disable(); 1268 set_new_lowcore(lc); 1269 S390_lowcore.nodat_stack = nodat_stack + STACK_INIT_OFFSET; 1270 S390_lowcore.async_stack = async_stack + STACK_INIT_OFFSET; 1271 S390_lowcore.mcck_stack = mcck_stack + STACK_INIT_OFFSET; 1272 lowcore_ptr[0] = lc; 1273 local_mcck_enable(); 1274 local_irq_restore(flags); 1275 1276 free_pages(lc_ipl->async_stack - STACK_INIT_OFFSET, THREAD_SIZE_ORDER); 1277 memblock_free_late(lc_ipl->mcck_stack - STACK_INIT_OFFSET, THREAD_SIZE); 1278 memblock_free_late((unsigned long) lc_ipl, sizeof(*lc_ipl)); 1279 1280 return 0; 1281 } 1282 early_initcall(smp_reinit_ipl_cpu); 1283