xref: /openbmc/linux/arch/s390/kernel/smp.c (revision 1c0a0af5)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  *  SMP related functions
4  *
5  *    Copyright IBM Corp. 1999, 2012
6  *    Author(s): Denis Joseph Barrow,
7  *		 Martin Schwidefsky <schwidefsky@de.ibm.com>,
8  *
9  *  based on other smp stuff by
10  *    (c) 1995 Alan Cox, CymruNET Ltd  <alan@cymru.net>
11  *    (c) 1998 Ingo Molnar
12  *
13  * The code outside of smp.c uses logical cpu numbers, only smp.c does
14  * the translation of logical to physical cpu ids. All new code that
15  * operates on physical cpu numbers needs to go into smp.c.
16  */
17 
18 #define KMSG_COMPONENT "cpu"
19 #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
20 
21 #include <linux/workqueue.h>
22 #include <linux/memblock.h>
23 #include <linux/export.h>
24 #include <linux/init.h>
25 #include <linux/mm.h>
26 #include <linux/err.h>
27 #include <linux/spinlock.h>
28 #include <linux/kernel_stat.h>
29 #include <linux/delay.h>
30 #include <linux/interrupt.h>
31 #include <linux/irqflags.h>
32 #include <linux/irq_work.h>
33 #include <linux/cpu.h>
34 #include <linux/slab.h>
35 #include <linux/sched/hotplug.h>
36 #include <linux/sched/task_stack.h>
37 #include <linux/crash_dump.h>
38 #include <linux/kprobes.h>
39 #include <asm/asm-offsets.h>
40 #include <asm/diag.h>
41 #include <asm/switch_to.h>
42 #include <asm/facility.h>
43 #include <asm/ipl.h>
44 #include <asm/setup.h>
45 #include <asm/irq.h>
46 #include <asm/tlbflush.h>
47 #include <asm/vtimer.h>
48 #include <asm/abs_lowcore.h>
49 #include <asm/sclp.h>
50 #include <asm/debug.h>
51 #include <asm/os_info.h>
52 #include <asm/sigp.h>
53 #include <asm/idle.h>
54 #include <asm/nmi.h>
55 #include <asm/stacktrace.h>
56 #include <asm/topology.h>
57 #include <asm/vdso.h>
58 #include <asm/maccess.h>
59 #include "entry.h"
60 
61 enum {
62 	ec_schedule = 0,
63 	ec_call_function_single,
64 	ec_stop_cpu,
65 	ec_mcck_pending,
66 	ec_irq_work,
67 };
68 
69 enum {
70 	CPU_STATE_STANDBY,
71 	CPU_STATE_CONFIGURED,
72 };
73 
74 static DEFINE_PER_CPU(struct cpu *, cpu_device);
75 
76 struct pcpu {
77 	unsigned long ec_mask;		/* bit mask for ec_xxx functions */
78 	unsigned long ec_clk;		/* sigp timestamp for ec_xxx */
79 	signed char state;		/* physical cpu state */
80 	signed char polarization;	/* physical polarization */
81 	u16 address;			/* physical cpu address */
82 };
83 
84 static u8 boot_core_type;
85 static struct pcpu pcpu_devices[NR_CPUS];
86 
87 unsigned int smp_cpu_mt_shift;
88 EXPORT_SYMBOL(smp_cpu_mt_shift);
89 
90 unsigned int smp_cpu_mtid;
91 EXPORT_SYMBOL(smp_cpu_mtid);
92 
93 #ifdef CONFIG_CRASH_DUMP
94 __vector128 __initdata boot_cpu_vector_save_area[__NUM_VXRS];
95 #endif
96 
97 static unsigned int smp_max_threads __initdata = -1U;
98 cpumask_t cpu_setup_mask;
99 
100 static int __init early_nosmt(char *s)
101 {
102 	smp_max_threads = 1;
103 	return 0;
104 }
105 early_param("nosmt", early_nosmt);
106 
107 static int __init early_smt(char *s)
108 {
109 	get_option(&s, &smp_max_threads);
110 	return 0;
111 }
112 early_param("smt", early_smt);
113 
114 /*
115  * The smp_cpu_state_mutex must be held when changing the state or polarization
116  * member of a pcpu data structure within the pcpu_devices arreay.
117  */
118 DEFINE_MUTEX(smp_cpu_state_mutex);
119 
120 /*
121  * Signal processor helper functions.
122  */
123 static inline int __pcpu_sigp_relax(u16 addr, u8 order, unsigned long parm)
124 {
125 	int cc;
126 
127 	while (1) {
128 		cc = __pcpu_sigp(addr, order, parm, NULL);
129 		if (cc != SIGP_CC_BUSY)
130 			return cc;
131 		cpu_relax();
132 	}
133 }
134 
135 static int pcpu_sigp_retry(struct pcpu *pcpu, u8 order, u32 parm)
136 {
137 	int cc, retry;
138 
139 	for (retry = 0; ; retry++) {
140 		cc = __pcpu_sigp(pcpu->address, order, parm, NULL);
141 		if (cc != SIGP_CC_BUSY)
142 			break;
143 		if (retry >= 3)
144 			udelay(10);
145 	}
146 	return cc;
147 }
148 
149 static inline int pcpu_stopped(struct pcpu *pcpu)
150 {
151 	u32 status;
152 
153 	if (__pcpu_sigp(pcpu->address, SIGP_SENSE,
154 			0, &status) != SIGP_CC_STATUS_STORED)
155 		return 0;
156 	return !!(status & (SIGP_STATUS_CHECK_STOP|SIGP_STATUS_STOPPED));
157 }
158 
159 static inline int pcpu_running(struct pcpu *pcpu)
160 {
161 	if (__pcpu_sigp(pcpu->address, SIGP_SENSE_RUNNING,
162 			0, NULL) != SIGP_CC_STATUS_STORED)
163 		return 1;
164 	/* Status stored condition code is equivalent to cpu not running. */
165 	return 0;
166 }
167 
168 /*
169  * Find struct pcpu by cpu address.
170  */
171 static struct pcpu *pcpu_find_address(const struct cpumask *mask, u16 address)
172 {
173 	int cpu;
174 
175 	for_each_cpu(cpu, mask)
176 		if (pcpu_devices[cpu].address == address)
177 			return pcpu_devices + cpu;
178 	return NULL;
179 }
180 
181 static void pcpu_ec_call(struct pcpu *pcpu, int ec_bit)
182 {
183 	int order;
184 
185 	if (test_and_set_bit(ec_bit, &pcpu->ec_mask))
186 		return;
187 	order = pcpu_running(pcpu) ? SIGP_EXTERNAL_CALL : SIGP_EMERGENCY_SIGNAL;
188 	pcpu->ec_clk = get_tod_clock_fast();
189 	pcpu_sigp_retry(pcpu, order, 0);
190 }
191 
192 static int pcpu_alloc_lowcore(struct pcpu *pcpu, int cpu)
193 {
194 	unsigned long async_stack, nodat_stack, mcck_stack;
195 	struct lowcore *lc;
196 
197 	lc = (struct lowcore *) __get_free_pages(GFP_KERNEL | GFP_DMA, LC_ORDER);
198 	nodat_stack = __get_free_pages(GFP_KERNEL, THREAD_SIZE_ORDER);
199 	async_stack = stack_alloc();
200 	mcck_stack = stack_alloc();
201 	if (!lc || !nodat_stack || !async_stack || !mcck_stack)
202 		goto out;
203 	memcpy(lc, &S390_lowcore, 512);
204 	memset((char *) lc + 512, 0, sizeof(*lc) - 512);
205 	lc->async_stack = async_stack + STACK_INIT_OFFSET;
206 	lc->nodat_stack = nodat_stack + STACK_INIT_OFFSET;
207 	lc->mcck_stack = mcck_stack + STACK_INIT_OFFSET;
208 	lc->cpu_nr = cpu;
209 	lc->spinlock_lockval = arch_spin_lockval(cpu);
210 	lc->spinlock_index = 0;
211 	lc->return_lpswe = gen_lpswe(__LC_RETURN_PSW);
212 	lc->return_mcck_lpswe = gen_lpswe(__LC_RETURN_MCCK_PSW);
213 	lc->preempt_count = PREEMPT_DISABLED;
214 	if (nmi_alloc_mcesa(&lc->mcesad))
215 		goto out;
216 	if (abs_lowcore_map(cpu, lc, true))
217 		goto out_mcesa;
218 	lowcore_ptr[cpu] = lc;
219 	pcpu_sigp_retry(pcpu, SIGP_SET_PREFIX, __pa(lc));
220 	return 0;
221 
222 out_mcesa:
223 	nmi_free_mcesa(&lc->mcesad);
224 out:
225 	stack_free(mcck_stack);
226 	stack_free(async_stack);
227 	free_pages(nodat_stack, THREAD_SIZE_ORDER);
228 	free_pages((unsigned long) lc, LC_ORDER);
229 	return -ENOMEM;
230 }
231 
232 static void pcpu_free_lowcore(struct pcpu *pcpu)
233 {
234 	unsigned long async_stack, nodat_stack, mcck_stack;
235 	struct lowcore *lc;
236 	int cpu;
237 
238 	cpu = pcpu - pcpu_devices;
239 	lc = lowcore_ptr[cpu];
240 	nodat_stack = lc->nodat_stack - STACK_INIT_OFFSET;
241 	async_stack = lc->async_stack - STACK_INIT_OFFSET;
242 	mcck_stack = lc->mcck_stack - STACK_INIT_OFFSET;
243 	pcpu_sigp_retry(pcpu, SIGP_SET_PREFIX, 0);
244 	lowcore_ptr[cpu] = NULL;
245 	abs_lowcore_unmap(cpu);
246 	nmi_free_mcesa(&lc->mcesad);
247 	stack_free(async_stack);
248 	stack_free(mcck_stack);
249 	free_pages(nodat_stack, THREAD_SIZE_ORDER);
250 	free_pages((unsigned long) lc, LC_ORDER);
251 }
252 
253 static void pcpu_prepare_secondary(struct pcpu *pcpu, int cpu)
254 {
255 	struct lowcore *lc = lowcore_ptr[cpu];
256 
257 	cpumask_set_cpu(cpu, &init_mm.context.cpu_attach_mask);
258 	cpumask_set_cpu(cpu, mm_cpumask(&init_mm));
259 	lc->cpu_nr = cpu;
260 	lc->restart_flags = RESTART_FLAG_CTLREGS;
261 	lc->spinlock_lockval = arch_spin_lockval(cpu);
262 	lc->spinlock_index = 0;
263 	lc->percpu_offset = __per_cpu_offset[cpu];
264 	lc->kernel_asce = S390_lowcore.kernel_asce;
265 	lc->user_asce = s390_invalid_asce;
266 	lc->machine_flags = S390_lowcore.machine_flags;
267 	lc->user_timer = lc->system_timer =
268 		lc->steal_timer = lc->avg_steal_timer = 0;
269 	__ctl_store(lc->cregs_save_area, 0, 15);
270 	lc->cregs_save_area[1] = lc->kernel_asce;
271 	lc->cregs_save_area[7] = lc->user_asce;
272 	save_access_regs((unsigned int *) lc->access_regs_save_area);
273 	arch_spin_lock_setup(cpu);
274 }
275 
276 static void pcpu_attach_task(struct pcpu *pcpu, struct task_struct *tsk)
277 {
278 	struct lowcore *lc;
279 	int cpu;
280 
281 	cpu = pcpu - pcpu_devices;
282 	lc = lowcore_ptr[cpu];
283 	lc->kernel_stack = (unsigned long) task_stack_page(tsk)
284 		+ THREAD_SIZE - STACK_FRAME_OVERHEAD - sizeof(struct pt_regs);
285 	lc->current_task = (unsigned long) tsk;
286 	lc->lpp = LPP_MAGIC;
287 	lc->current_pid = tsk->pid;
288 	lc->user_timer = tsk->thread.user_timer;
289 	lc->guest_timer = tsk->thread.guest_timer;
290 	lc->system_timer = tsk->thread.system_timer;
291 	lc->hardirq_timer = tsk->thread.hardirq_timer;
292 	lc->softirq_timer = tsk->thread.softirq_timer;
293 	lc->steal_timer = 0;
294 }
295 
296 static void pcpu_start_fn(struct pcpu *pcpu, void (*func)(void *), void *data)
297 {
298 	struct lowcore *lc;
299 	int cpu;
300 
301 	cpu = pcpu - pcpu_devices;
302 	lc = lowcore_ptr[cpu];
303 	lc->restart_stack = lc->kernel_stack;
304 	lc->restart_fn = (unsigned long) func;
305 	lc->restart_data = (unsigned long) data;
306 	lc->restart_source = -1U;
307 	pcpu_sigp_retry(pcpu, SIGP_RESTART, 0);
308 }
309 
310 typedef void (pcpu_delegate_fn)(void *);
311 
312 /*
313  * Call function via PSW restart on pcpu and stop the current cpu.
314  */
315 static void __pcpu_delegate(pcpu_delegate_fn *func, void *data)
316 {
317 	func(data);	/* should not return */
318 }
319 
320 static void pcpu_delegate(struct pcpu *pcpu,
321 			  pcpu_delegate_fn *func,
322 			  void *data, unsigned long stack)
323 {
324 	struct lowcore *lc, *abs_lc;
325 	unsigned int source_cpu;
326 
327 	lc = lowcore_ptr[pcpu - pcpu_devices];
328 	source_cpu = stap();
329 
330 	if (pcpu->address == source_cpu) {
331 		call_on_stack(2, stack, void, __pcpu_delegate,
332 			      pcpu_delegate_fn *, func, void *, data);
333 	}
334 	/* Stop target cpu (if func returns this stops the current cpu). */
335 	pcpu_sigp_retry(pcpu, SIGP_STOP, 0);
336 	/* Restart func on the target cpu and stop the current cpu. */
337 	if (lc) {
338 		lc->restart_stack = stack;
339 		lc->restart_fn = (unsigned long)func;
340 		lc->restart_data = (unsigned long)data;
341 		lc->restart_source = source_cpu;
342 	} else {
343 		abs_lc = get_abs_lowcore();
344 		abs_lc->restart_stack = stack;
345 		abs_lc->restart_fn = (unsigned long)func;
346 		abs_lc->restart_data = (unsigned long)data;
347 		abs_lc->restart_source = source_cpu;
348 		put_abs_lowcore(abs_lc);
349 	}
350 	__bpon();
351 	asm volatile(
352 		"0:	sigp	0,%0,%2	# sigp restart to target cpu\n"
353 		"	brc	2,0b	# busy, try again\n"
354 		"1:	sigp	0,%1,%3	# sigp stop to current cpu\n"
355 		"	brc	2,1b	# busy, try again\n"
356 		: : "d" (pcpu->address), "d" (source_cpu),
357 		    "K" (SIGP_RESTART), "K" (SIGP_STOP)
358 		: "0", "1", "cc");
359 	for (;;) ;
360 }
361 
362 /*
363  * Enable additional logical cpus for multi-threading.
364  */
365 static int pcpu_set_smt(unsigned int mtid)
366 {
367 	int cc;
368 
369 	if (smp_cpu_mtid == mtid)
370 		return 0;
371 	cc = __pcpu_sigp(0, SIGP_SET_MULTI_THREADING, mtid, NULL);
372 	if (cc == 0) {
373 		smp_cpu_mtid = mtid;
374 		smp_cpu_mt_shift = 0;
375 		while (smp_cpu_mtid >= (1U << smp_cpu_mt_shift))
376 			smp_cpu_mt_shift++;
377 		pcpu_devices[0].address = stap();
378 	}
379 	return cc;
380 }
381 
382 /*
383  * Call function on an online CPU.
384  */
385 void smp_call_online_cpu(void (*func)(void *), void *data)
386 {
387 	struct pcpu *pcpu;
388 
389 	/* Use the current cpu if it is online. */
390 	pcpu = pcpu_find_address(cpu_online_mask, stap());
391 	if (!pcpu)
392 		/* Use the first online cpu. */
393 		pcpu = pcpu_devices + cpumask_first(cpu_online_mask);
394 	pcpu_delegate(pcpu, func, data, (unsigned long) restart_stack);
395 }
396 
397 /*
398  * Call function on the ipl CPU.
399  */
400 void smp_call_ipl_cpu(void (*func)(void *), void *data)
401 {
402 	struct lowcore *lc = lowcore_ptr[0];
403 
404 	if (pcpu_devices[0].address == stap())
405 		lc = &S390_lowcore;
406 
407 	pcpu_delegate(&pcpu_devices[0], func, data,
408 		      lc->nodat_stack);
409 }
410 
411 int smp_find_processor_id(u16 address)
412 {
413 	int cpu;
414 
415 	for_each_present_cpu(cpu)
416 		if (pcpu_devices[cpu].address == address)
417 			return cpu;
418 	return -1;
419 }
420 
421 void schedule_mcck_handler(void)
422 {
423 	pcpu_ec_call(pcpu_devices + smp_processor_id(), ec_mcck_pending);
424 }
425 
426 bool notrace arch_vcpu_is_preempted(int cpu)
427 {
428 	if (test_cpu_flag_of(CIF_ENABLED_WAIT, cpu))
429 		return false;
430 	if (pcpu_running(pcpu_devices + cpu))
431 		return false;
432 	return true;
433 }
434 EXPORT_SYMBOL(arch_vcpu_is_preempted);
435 
436 void notrace smp_yield_cpu(int cpu)
437 {
438 	if (!MACHINE_HAS_DIAG9C)
439 		return;
440 	diag_stat_inc_norecursion(DIAG_STAT_X09C);
441 	asm volatile("diag %0,0,0x9c"
442 		     : : "d" (pcpu_devices[cpu].address));
443 }
444 EXPORT_SYMBOL_GPL(smp_yield_cpu);
445 
446 /*
447  * Send cpus emergency shutdown signal. This gives the cpus the
448  * opportunity to complete outstanding interrupts.
449  */
450 void notrace smp_emergency_stop(void)
451 {
452 	static arch_spinlock_t lock = __ARCH_SPIN_LOCK_UNLOCKED;
453 	static cpumask_t cpumask;
454 	u64 end;
455 	int cpu;
456 
457 	arch_spin_lock(&lock);
458 	cpumask_copy(&cpumask, cpu_online_mask);
459 	cpumask_clear_cpu(smp_processor_id(), &cpumask);
460 
461 	end = get_tod_clock() + (1000000UL << 12);
462 	for_each_cpu(cpu, &cpumask) {
463 		struct pcpu *pcpu = pcpu_devices + cpu;
464 		set_bit(ec_stop_cpu, &pcpu->ec_mask);
465 		while (__pcpu_sigp(pcpu->address, SIGP_EMERGENCY_SIGNAL,
466 				   0, NULL) == SIGP_CC_BUSY &&
467 		       get_tod_clock() < end)
468 			cpu_relax();
469 	}
470 	while (get_tod_clock() < end) {
471 		for_each_cpu(cpu, &cpumask)
472 			if (pcpu_stopped(pcpu_devices + cpu))
473 				cpumask_clear_cpu(cpu, &cpumask);
474 		if (cpumask_empty(&cpumask))
475 			break;
476 		cpu_relax();
477 	}
478 	arch_spin_unlock(&lock);
479 }
480 NOKPROBE_SYMBOL(smp_emergency_stop);
481 
482 /*
483  * Stop all cpus but the current one.
484  */
485 void smp_send_stop(void)
486 {
487 	int cpu;
488 
489 	/* Disable all interrupts/machine checks */
490 	__load_psw_mask(PSW_KERNEL_BITS);
491 	trace_hardirqs_off();
492 
493 	debug_set_critical();
494 
495 	if (oops_in_progress)
496 		smp_emergency_stop();
497 
498 	/* stop all processors */
499 	for_each_online_cpu(cpu) {
500 		if (cpu == smp_processor_id())
501 			continue;
502 		pcpu_sigp_retry(pcpu_devices + cpu, SIGP_STOP, 0);
503 		while (!pcpu_stopped(pcpu_devices + cpu))
504 			cpu_relax();
505 	}
506 }
507 
508 /*
509  * This is the main routine where commands issued by other
510  * cpus are handled.
511  */
512 static void smp_handle_ext_call(void)
513 {
514 	unsigned long bits;
515 
516 	/* handle bit signal external calls */
517 	bits = xchg(&pcpu_devices[smp_processor_id()].ec_mask, 0);
518 	if (test_bit(ec_stop_cpu, &bits))
519 		smp_stop_cpu();
520 	if (test_bit(ec_schedule, &bits))
521 		scheduler_ipi();
522 	if (test_bit(ec_call_function_single, &bits))
523 		generic_smp_call_function_single_interrupt();
524 	if (test_bit(ec_mcck_pending, &bits))
525 		__s390_handle_mcck();
526 	if (test_bit(ec_irq_work, &bits))
527 		irq_work_run();
528 }
529 
530 static void do_ext_call_interrupt(struct ext_code ext_code,
531 				  unsigned int param32, unsigned long param64)
532 {
533 	inc_irq_stat(ext_code.code == 0x1202 ? IRQEXT_EXC : IRQEXT_EMS);
534 	smp_handle_ext_call();
535 }
536 
537 void arch_send_call_function_ipi_mask(const struct cpumask *mask)
538 {
539 	int cpu;
540 
541 	for_each_cpu(cpu, mask)
542 		pcpu_ec_call(pcpu_devices + cpu, ec_call_function_single);
543 }
544 
545 void arch_send_call_function_single_ipi(int cpu)
546 {
547 	pcpu_ec_call(pcpu_devices + cpu, ec_call_function_single);
548 }
549 
550 /*
551  * this function sends a 'reschedule' IPI to another CPU.
552  * it goes straight through and wastes no time serializing
553  * anything. Worst case is that we lose a reschedule ...
554  */
555 void smp_send_reschedule(int cpu)
556 {
557 	pcpu_ec_call(pcpu_devices + cpu, ec_schedule);
558 }
559 
560 #ifdef CONFIG_IRQ_WORK
561 void arch_irq_work_raise(void)
562 {
563 	pcpu_ec_call(pcpu_devices + smp_processor_id(), ec_irq_work);
564 }
565 #endif
566 
567 /*
568  * parameter area for the set/clear control bit callbacks
569  */
570 struct ec_creg_mask_parms {
571 	unsigned long orval;
572 	unsigned long andval;
573 	int cr;
574 };
575 
576 /*
577  * callback for setting/clearing control bits
578  */
579 static void smp_ctl_bit_callback(void *info)
580 {
581 	struct ec_creg_mask_parms *pp = info;
582 	unsigned long cregs[16];
583 
584 	__ctl_store(cregs, 0, 15);
585 	cregs[pp->cr] = (cregs[pp->cr] & pp->andval) | pp->orval;
586 	__ctl_load(cregs, 0, 15);
587 }
588 
589 static DEFINE_SPINLOCK(ctl_lock);
590 
591 void smp_ctl_set_clear_bit(int cr, int bit, bool set)
592 {
593 	struct ec_creg_mask_parms parms = { .cr = cr, };
594 	struct lowcore *abs_lc;
595 	u64 ctlreg;
596 
597 	if (set) {
598 		parms.orval = 1UL << bit;
599 		parms.andval = -1UL;
600 	} else {
601 		parms.orval = 0;
602 		parms.andval = ~(1UL << bit);
603 	}
604 	spin_lock(&ctl_lock);
605 	abs_lc = get_abs_lowcore();
606 	ctlreg = abs_lc->cregs_save_area[cr];
607 	ctlreg = (ctlreg & parms.andval) | parms.orval;
608 	abs_lc->cregs_save_area[cr] = ctlreg;
609 	put_abs_lowcore(abs_lc);
610 	spin_unlock(&ctl_lock);
611 	on_each_cpu(smp_ctl_bit_callback, &parms, 1);
612 }
613 EXPORT_SYMBOL(smp_ctl_set_clear_bit);
614 
615 #ifdef CONFIG_CRASH_DUMP
616 
617 int smp_store_status(int cpu)
618 {
619 	struct lowcore *lc;
620 	struct pcpu *pcpu;
621 	unsigned long pa;
622 
623 	pcpu = pcpu_devices + cpu;
624 	lc = lowcore_ptr[cpu];
625 	pa = __pa(&lc->floating_pt_save_area);
626 	if (__pcpu_sigp_relax(pcpu->address, SIGP_STORE_STATUS_AT_ADDRESS,
627 			      pa) != SIGP_CC_ORDER_CODE_ACCEPTED)
628 		return -EIO;
629 	if (!MACHINE_HAS_VX && !MACHINE_HAS_GS)
630 		return 0;
631 	pa = lc->mcesad & MCESA_ORIGIN_MASK;
632 	if (MACHINE_HAS_GS)
633 		pa |= lc->mcesad & MCESA_LC_MASK;
634 	if (__pcpu_sigp_relax(pcpu->address, SIGP_STORE_ADDITIONAL_STATUS,
635 			      pa) != SIGP_CC_ORDER_CODE_ACCEPTED)
636 		return -EIO;
637 	return 0;
638 }
639 
640 /*
641  * Collect CPU state of the previous, crashed system.
642  * There are four cases:
643  * 1) standard zfcp/nvme dump
644  *    condition: OLDMEM_BASE == NULL && is_ipl_type_dump() == true
645  *    The state for all CPUs except the boot CPU needs to be collected
646  *    with sigp stop-and-store-status. The boot CPU state is located in
647  *    the absolute lowcore of the memory stored in the HSA. The zcore code
648  *    will copy the boot CPU state from the HSA.
649  * 2) stand-alone kdump for SCSI/NVMe (zfcp/nvme dump with swapped memory)
650  *    condition: OLDMEM_BASE != NULL && is_ipl_type_dump() == true
651  *    The state for all CPUs except the boot CPU needs to be collected
652  *    with sigp stop-and-store-status. The firmware or the boot-loader
653  *    stored the registers of the boot CPU in the absolute lowcore in the
654  *    memory of the old system.
655  * 3) kdump and the old kernel did not store the CPU state,
656  *    or stand-alone kdump for DASD
657  *    condition: OLDMEM_BASE != NULL && !is_kdump_kernel()
658  *    The state for all CPUs except the boot CPU needs to be collected
659  *    with sigp stop-and-store-status. The kexec code or the boot-loader
660  *    stored the registers of the boot CPU in the memory of the old system.
661  * 4) kdump and the old kernel stored the CPU state
662  *    condition: OLDMEM_BASE != NULL && is_kdump_kernel()
663  *    This case does not exist for s390 anymore, setup_arch explicitly
664  *    deactivates the elfcorehdr= kernel parameter
665  */
666 static bool dump_available(void)
667 {
668 	return oldmem_data.start || is_ipl_type_dump();
669 }
670 
671 void __init smp_save_dump_ipl_cpu(void)
672 {
673 	struct save_area *sa;
674 	void *regs;
675 
676 	if (!dump_available())
677 		return;
678 	sa = save_area_alloc(true);
679 	regs = memblock_alloc(512, 8);
680 	if (!sa || !regs)
681 		panic("could not allocate memory for boot CPU save area\n");
682 	copy_oldmem_kernel(regs, __LC_FPREGS_SAVE_AREA, 512);
683 	save_area_add_regs(sa, regs);
684 	memblock_free(regs, 512);
685 	if (MACHINE_HAS_VX)
686 		save_area_add_vxrs(sa, boot_cpu_vector_save_area);
687 }
688 
689 void __init smp_save_dump_secondary_cpus(void)
690 {
691 	int addr, boot_cpu_addr, max_cpu_addr;
692 	struct save_area *sa;
693 	void *page;
694 
695 	if (!dump_available())
696 		return;
697 	/* Allocate a page as dumping area for the store status sigps */
698 	page = memblock_alloc_low(PAGE_SIZE, PAGE_SIZE);
699 	if (!page)
700 		panic("ERROR: Failed to allocate %lx bytes below %lx\n",
701 		      PAGE_SIZE, 1UL << 31);
702 
703 	/* Set multi-threading state to the previous system. */
704 	pcpu_set_smt(sclp.mtid_prev);
705 	boot_cpu_addr = stap();
706 	max_cpu_addr = SCLP_MAX_CORES << sclp.mtid_prev;
707 	for (addr = 0; addr <= max_cpu_addr; addr++) {
708 		if (addr == boot_cpu_addr)
709 			continue;
710 		if (__pcpu_sigp_relax(addr, SIGP_SENSE, 0) ==
711 		    SIGP_CC_NOT_OPERATIONAL)
712 			continue;
713 		sa = save_area_alloc(false);
714 		if (!sa)
715 			panic("could not allocate memory for save area\n");
716 		__pcpu_sigp_relax(addr, SIGP_STORE_STATUS_AT_ADDRESS, __pa(page));
717 		save_area_add_regs(sa, page);
718 		if (MACHINE_HAS_VX) {
719 			__pcpu_sigp_relax(addr, SIGP_STORE_ADDITIONAL_STATUS, __pa(page));
720 			save_area_add_vxrs(sa, page);
721 		}
722 	}
723 	memblock_free(page, PAGE_SIZE);
724 	diag_amode31_ops.diag308_reset();
725 	pcpu_set_smt(0);
726 }
727 #endif /* CONFIG_CRASH_DUMP */
728 
729 void smp_cpu_set_polarization(int cpu, int val)
730 {
731 	pcpu_devices[cpu].polarization = val;
732 }
733 
734 int smp_cpu_get_polarization(int cpu)
735 {
736 	return pcpu_devices[cpu].polarization;
737 }
738 
739 int smp_cpu_get_cpu_address(int cpu)
740 {
741 	return pcpu_devices[cpu].address;
742 }
743 
744 static void __ref smp_get_core_info(struct sclp_core_info *info, int early)
745 {
746 	static int use_sigp_detection;
747 	int address;
748 
749 	if (use_sigp_detection || sclp_get_core_info(info, early)) {
750 		use_sigp_detection = 1;
751 		for (address = 0;
752 		     address < (SCLP_MAX_CORES << smp_cpu_mt_shift);
753 		     address += (1U << smp_cpu_mt_shift)) {
754 			if (__pcpu_sigp_relax(address, SIGP_SENSE, 0) ==
755 			    SIGP_CC_NOT_OPERATIONAL)
756 				continue;
757 			info->core[info->configured].core_id =
758 				address >> smp_cpu_mt_shift;
759 			info->configured++;
760 		}
761 		info->combined = info->configured;
762 	}
763 }
764 
765 static int smp_add_present_cpu(int cpu);
766 
767 static int smp_add_core(struct sclp_core_entry *core, cpumask_t *avail,
768 			bool configured, bool early)
769 {
770 	struct pcpu *pcpu;
771 	int cpu, nr, i;
772 	u16 address;
773 
774 	nr = 0;
775 	if (sclp.has_core_type && core->type != boot_core_type)
776 		return nr;
777 	cpu = cpumask_first(avail);
778 	address = core->core_id << smp_cpu_mt_shift;
779 	for (i = 0; (i <= smp_cpu_mtid) && (cpu < nr_cpu_ids); i++) {
780 		if (pcpu_find_address(cpu_present_mask, address + i))
781 			continue;
782 		pcpu = pcpu_devices + cpu;
783 		pcpu->address = address + i;
784 		if (configured)
785 			pcpu->state = CPU_STATE_CONFIGURED;
786 		else
787 			pcpu->state = CPU_STATE_STANDBY;
788 		smp_cpu_set_polarization(cpu, POLARIZATION_UNKNOWN);
789 		set_cpu_present(cpu, true);
790 		if (!early && smp_add_present_cpu(cpu) != 0)
791 			set_cpu_present(cpu, false);
792 		else
793 			nr++;
794 		cpumask_clear_cpu(cpu, avail);
795 		cpu = cpumask_next(cpu, avail);
796 	}
797 	return nr;
798 }
799 
800 static int __smp_rescan_cpus(struct sclp_core_info *info, bool early)
801 {
802 	struct sclp_core_entry *core;
803 	static cpumask_t avail;
804 	bool configured;
805 	u16 core_id;
806 	int nr, i;
807 
808 	cpus_read_lock();
809 	mutex_lock(&smp_cpu_state_mutex);
810 	nr = 0;
811 	cpumask_xor(&avail, cpu_possible_mask, cpu_present_mask);
812 	/*
813 	 * Add IPL core first (which got logical CPU number 0) to make sure
814 	 * that all SMT threads get subsequent logical CPU numbers.
815 	 */
816 	if (early) {
817 		core_id = pcpu_devices[0].address >> smp_cpu_mt_shift;
818 		for (i = 0; i < info->configured; i++) {
819 			core = &info->core[i];
820 			if (core->core_id == core_id) {
821 				nr += smp_add_core(core, &avail, true, early);
822 				break;
823 			}
824 		}
825 	}
826 	for (i = 0; i < info->combined; i++) {
827 		configured = i < info->configured;
828 		nr += smp_add_core(&info->core[i], &avail, configured, early);
829 	}
830 	mutex_unlock(&smp_cpu_state_mutex);
831 	cpus_read_unlock();
832 	return nr;
833 }
834 
835 void __init smp_detect_cpus(void)
836 {
837 	unsigned int cpu, mtid, c_cpus, s_cpus;
838 	struct sclp_core_info *info;
839 	u16 address;
840 
841 	/* Get CPU information */
842 	info = memblock_alloc(sizeof(*info), 8);
843 	if (!info)
844 		panic("%s: Failed to allocate %zu bytes align=0x%x\n",
845 		      __func__, sizeof(*info), 8);
846 	smp_get_core_info(info, 1);
847 	/* Find boot CPU type */
848 	if (sclp.has_core_type) {
849 		address = stap();
850 		for (cpu = 0; cpu < info->combined; cpu++)
851 			if (info->core[cpu].core_id == address) {
852 				/* The boot cpu dictates the cpu type. */
853 				boot_core_type = info->core[cpu].type;
854 				break;
855 			}
856 		if (cpu >= info->combined)
857 			panic("Could not find boot CPU type");
858 	}
859 
860 	/* Set multi-threading state for the current system */
861 	mtid = boot_core_type ? sclp.mtid : sclp.mtid_cp;
862 	mtid = (mtid < smp_max_threads) ? mtid : smp_max_threads - 1;
863 	pcpu_set_smt(mtid);
864 
865 	/* Print number of CPUs */
866 	c_cpus = s_cpus = 0;
867 	for (cpu = 0; cpu < info->combined; cpu++) {
868 		if (sclp.has_core_type &&
869 		    info->core[cpu].type != boot_core_type)
870 			continue;
871 		if (cpu < info->configured)
872 			c_cpus += smp_cpu_mtid + 1;
873 		else
874 			s_cpus += smp_cpu_mtid + 1;
875 	}
876 	pr_info("%d configured CPUs, %d standby CPUs\n", c_cpus, s_cpus);
877 
878 	/* Add CPUs present at boot */
879 	__smp_rescan_cpus(info, true);
880 	memblock_free(info, sizeof(*info));
881 }
882 
883 /*
884  *	Activate a secondary processor.
885  */
886 static void smp_start_secondary(void *cpuvoid)
887 {
888 	int cpu = raw_smp_processor_id();
889 
890 	S390_lowcore.last_update_clock = get_tod_clock();
891 	S390_lowcore.restart_stack = (unsigned long)restart_stack;
892 	S390_lowcore.restart_fn = (unsigned long)do_restart;
893 	S390_lowcore.restart_data = 0;
894 	S390_lowcore.restart_source = -1U;
895 	S390_lowcore.restart_flags = 0;
896 	restore_access_regs(S390_lowcore.access_regs_save_area);
897 	cpu_init();
898 	rcu_cpu_starting(cpu);
899 	init_cpu_timer();
900 	vtime_init();
901 	vdso_getcpu_init();
902 	pfault_init();
903 	cpumask_set_cpu(cpu, &cpu_setup_mask);
904 	update_cpu_masks();
905 	notify_cpu_starting(cpu);
906 	if (topology_cpu_dedicated(cpu))
907 		set_cpu_flag(CIF_DEDICATED_CPU);
908 	else
909 		clear_cpu_flag(CIF_DEDICATED_CPU);
910 	set_cpu_online(cpu, true);
911 	inc_irq_stat(CPU_RST);
912 	local_irq_enable();
913 	cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
914 }
915 
916 /* Upping and downing of CPUs */
917 int __cpu_up(unsigned int cpu, struct task_struct *tidle)
918 {
919 	struct pcpu *pcpu = pcpu_devices + cpu;
920 	int rc;
921 
922 	if (pcpu->state != CPU_STATE_CONFIGURED)
923 		return -EIO;
924 	if (pcpu_sigp_retry(pcpu, SIGP_INITIAL_CPU_RESET, 0) !=
925 	    SIGP_CC_ORDER_CODE_ACCEPTED)
926 		return -EIO;
927 
928 	rc = pcpu_alloc_lowcore(pcpu, cpu);
929 	if (rc)
930 		return rc;
931 	pcpu_prepare_secondary(pcpu, cpu);
932 	pcpu_attach_task(pcpu, tidle);
933 	pcpu_start_fn(pcpu, smp_start_secondary, NULL);
934 	/* Wait until cpu puts itself in the online & active maps */
935 	while (!cpu_online(cpu))
936 		cpu_relax();
937 	return 0;
938 }
939 
940 static unsigned int setup_possible_cpus __initdata;
941 
942 static int __init _setup_possible_cpus(char *s)
943 {
944 	get_option(&s, &setup_possible_cpus);
945 	return 0;
946 }
947 early_param("possible_cpus", _setup_possible_cpus);
948 
949 int __cpu_disable(void)
950 {
951 	unsigned long cregs[16];
952 	int cpu;
953 
954 	/* Handle possible pending IPIs */
955 	smp_handle_ext_call();
956 	cpu = smp_processor_id();
957 	set_cpu_online(cpu, false);
958 	cpumask_clear_cpu(cpu, &cpu_setup_mask);
959 	update_cpu_masks();
960 	/* Disable pseudo page faults on this cpu. */
961 	pfault_fini();
962 	/* Disable interrupt sources via control register. */
963 	__ctl_store(cregs, 0, 15);
964 	cregs[0]  &= ~0x0000ee70UL;	/* disable all external interrupts */
965 	cregs[6]  &= ~0xff000000UL;	/* disable all I/O interrupts */
966 	cregs[14] &= ~0x1f000000UL;	/* disable most machine checks */
967 	__ctl_load(cregs, 0, 15);
968 	clear_cpu_flag(CIF_NOHZ_DELAY);
969 	return 0;
970 }
971 
972 void __cpu_die(unsigned int cpu)
973 {
974 	struct pcpu *pcpu;
975 
976 	/* Wait until target cpu is down */
977 	pcpu = pcpu_devices + cpu;
978 	while (!pcpu_stopped(pcpu))
979 		cpu_relax();
980 	pcpu_free_lowcore(pcpu);
981 	cpumask_clear_cpu(cpu, mm_cpumask(&init_mm));
982 	cpumask_clear_cpu(cpu, &init_mm.context.cpu_attach_mask);
983 }
984 
985 void __noreturn cpu_die(void)
986 {
987 	idle_task_exit();
988 	__bpon();
989 	pcpu_sigp_retry(pcpu_devices + smp_processor_id(), SIGP_STOP, 0);
990 	for (;;) ;
991 }
992 
993 void __init smp_fill_possible_mask(void)
994 {
995 	unsigned int possible, sclp_max, cpu;
996 
997 	sclp_max = max(sclp.mtid, sclp.mtid_cp) + 1;
998 	sclp_max = min(smp_max_threads, sclp_max);
999 	sclp_max = (sclp.max_cores * sclp_max) ?: nr_cpu_ids;
1000 	possible = setup_possible_cpus ?: nr_cpu_ids;
1001 	possible = min(possible, sclp_max);
1002 	for (cpu = 0; cpu < possible && cpu < nr_cpu_ids; cpu++)
1003 		set_cpu_possible(cpu, true);
1004 }
1005 
1006 void __init smp_prepare_cpus(unsigned int max_cpus)
1007 {
1008 	/* request the 0x1201 emergency signal external interrupt */
1009 	if (register_external_irq(EXT_IRQ_EMERGENCY_SIG, do_ext_call_interrupt))
1010 		panic("Couldn't request external interrupt 0x1201");
1011 	/* request the 0x1202 external call external interrupt */
1012 	if (register_external_irq(EXT_IRQ_EXTERNAL_CALL, do_ext_call_interrupt))
1013 		panic("Couldn't request external interrupt 0x1202");
1014 }
1015 
1016 void __init smp_prepare_boot_cpu(void)
1017 {
1018 	struct pcpu *pcpu = pcpu_devices;
1019 
1020 	WARN_ON(!cpu_present(0) || !cpu_online(0));
1021 	pcpu->state = CPU_STATE_CONFIGURED;
1022 	S390_lowcore.percpu_offset = __per_cpu_offset[0];
1023 	smp_cpu_set_polarization(0, POLARIZATION_UNKNOWN);
1024 }
1025 
1026 void __init smp_setup_processor_id(void)
1027 {
1028 	pcpu_devices[0].address = stap();
1029 	S390_lowcore.cpu_nr = 0;
1030 	S390_lowcore.spinlock_lockval = arch_spin_lockval(0);
1031 	S390_lowcore.spinlock_index = 0;
1032 }
1033 
1034 /*
1035  * the frequency of the profiling timer can be changed
1036  * by writing a multiplier value into /proc/profile.
1037  *
1038  * usually you want to run this on all CPUs ;)
1039  */
1040 int setup_profiling_timer(unsigned int multiplier)
1041 {
1042 	return 0;
1043 }
1044 
1045 static ssize_t cpu_configure_show(struct device *dev,
1046 				  struct device_attribute *attr, char *buf)
1047 {
1048 	ssize_t count;
1049 
1050 	mutex_lock(&smp_cpu_state_mutex);
1051 	count = sprintf(buf, "%d\n", pcpu_devices[dev->id].state);
1052 	mutex_unlock(&smp_cpu_state_mutex);
1053 	return count;
1054 }
1055 
1056 static ssize_t cpu_configure_store(struct device *dev,
1057 				   struct device_attribute *attr,
1058 				   const char *buf, size_t count)
1059 {
1060 	struct pcpu *pcpu;
1061 	int cpu, val, rc, i;
1062 	char delim;
1063 
1064 	if (sscanf(buf, "%d %c", &val, &delim) != 1)
1065 		return -EINVAL;
1066 	if (val != 0 && val != 1)
1067 		return -EINVAL;
1068 	cpus_read_lock();
1069 	mutex_lock(&smp_cpu_state_mutex);
1070 	rc = -EBUSY;
1071 	/* disallow configuration changes of online cpus and cpu 0 */
1072 	cpu = dev->id;
1073 	cpu = smp_get_base_cpu(cpu);
1074 	if (cpu == 0)
1075 		goto out;
1076 	for (i = 0; i <= smp_cpu_mtid; i++)
1077 		if (cpu_online(cpu + i))
1078 			goto out;
1079 	pcpu = pcpu_devices + cpu;
1080 	rc = 0;
1081 	switch (val) {
1082 	case 0:
1083 		if (pcpu->state != CPU_STATE_CONFIGURED)
1084 			break;
1085 		rc = sclp_core_deconfigure(pcpu->address >> smp_cpu_mt_shift);
1086 		if (rc)
1087 			break;
1088 		for (i = 0; i <= smp_cpu_mtid; i++) {
1089 			if (cpu + i >= nr_cpu_ids || !cpu_present(cpu + i))
1090 				continue;
1091 			pcpu[i].state = CPU_STATE_STANDBY;
1092 			smp_cpu_set_polarization(cpu + i,
1093 						 POLARIZATION_UNKNOWN);
1094 		}
1095 		topology_expect_change();
1096 		break;
1097 	case 1:
1098 		if (pcpu->state != CPU_STATE_STANDBY)
1099 			break;
1100 		rc = sclp_core_configure(pcpu->address >> smp_cpu_mt_shift);
1101 		if (rc)
1102 			break;
1103 		for (i = 0; i <= smp_cpu_mtid; i++) {
1104 			if (cpu + i >= nr_cpu_ids || !cpu_present(cpu + i))
1105 				continue;
1106 			pcpu[i].state = CPU_STATE_CONFIGURED;
1107 			smp_cpu_set_polarization(cpu + i,
1108 						 POLARIZATION_UNKNOWN);
1109 		}
1110 		topology_expect_change();
1111 		break;
1112 	default:
1113 		break;
1114 	}
1115 out:
1116 	mutex_unlock(&smp_cpu_state_mutex);
1117 	cpus_read_unlock();
1118 	return rc ? rc : count;
1119 }
1120 static DEVICE_ATTR(configure, 0644, cpu_configure_show, cpu_configure_store);
1121 
1122 static ssize_t show_cpu_address(struct device *dev,
1123 				struct device_attribute *attr, char *buf)
1124 {
1125 	return sprintf(buf, "%d\n", pcpu_devices[dev->id].address);
1126 }
1127 static DEVICE_ATTR(address, 0444, show_cpu_address, NULL);
1128 
1129 static struct attribute *cpu_common_attrs[] = {
1130 	&dev_attr_configure.attr,
1131 	&dev_attr_address.attr,
1132 	NULL,
1133 };
1134 
1135 static struct attribute_group cpu_common_attr_group = {
1136 	.attrs = cpu_common_attrs,
1137 };
1138 
1139 static struct attribute *cpu_online_attrs[] = {
1140 	&dev_attr_idle_count.attr,
1141 	&dev_attr_idle_time_us.attr,
1142 	NULL,
1143 };
1144 
1145 static struct attribute_group cpu_online_attr_group = {
1146 	.attrs = cpu_online_attrs,
1147 };
1148 
1149 static int smp_cpu_online(unsigned int cpu)
1150 {
1151 	struct device *s = &per_cpu(cpu_device, cpu)->dev;
1152 
1153 	return sysfs_create_group(&s->kobj, &cpu_online_attr_group);
1154 }
1155 
1156 static int smp_cpu_pre_down(unsigned int cpu)
1157 {
1158 	struct device *s = &per_cpu(cpu_device, cpu)->dev;
1159 
1160 	sysfs_remove_group(&s->kobj, &cpu_online_attr_group);
1161 	return 0;
1162 }
1163 
1164 static int smp_add_present_cpu(int cpu)
1165 {
1166 	struct device *s;
1167 	struct cpu *c;
1168 	int rc;
1169 
1170 	c = kzalloc(sizeof(*c), GFP_KERNEL);
1171 	if (!c)
1172 		return -ENOMEM;
1173 	per_cpu(cpu_device, cpu) = c;
1174 	s = &c->dev;
1175 	c->hotpluggable = 1;
1176 	rc = register_cpu(c, cpu);
1177 	if (rc)
1178 		goto out;
1179 	rc = sysfs_create_group(&s->kobj, &cpu_common_attr_group);
1180 	if (rc)
1181 		goto out_cpu;
1182 	rc = topology_cpu_init(c);
1183 	if (rc)
1184 		goto out_topology;
1185 	return 0;
1186 
1187 out_topology:
1188 	sysfs_remove_group(&s->kobj, &cpu_common_attr_group);
1189 out_cpu:
1190 	unregister_cpu(c);
1191 out:
1192 	return rc;
1193 }
1194 
1195 int __ref smp_rescan_cpus(void)
1196 {
1197 	struct sclp_core_info *info;
1198 	int nr;
1199 
1200 	info = kzalloc(sizeof(*info), GFP_KERNEL);
1201 	if (!info)
1202 		return -ENOMEM;
1203 	smp_get_core_info(info, 0);
1204 	nr = __smp_rescan_cpus(info, false);
1205 	kfree(info);
1206 	if (nr)
1207 		topology_schedule_update();
1208 	return 0;
1209 }
1210 
1211 static ssize_t __ref rescan_store(struct device *dev,
1212 				  struct device_attribute *attr,
1213 				  const char *buf,
1214 				  size_t count)
1215 {
1216 	int rc;
1217 
1218 	rc = lock_device_hotplug_sysfs();
1219 	if (rc)
1220 		return rc;
1221 	rc = smp_rescan_cpus();
1222 	unlock_device_hotplug();
1223 	return rc ? rc : count;
1224 }
1225 static DEVICE_ATTR_WO(rescan);
1226 
1227 static int __init s390_smp_init(void)
1228 {
1229 	int cpu, rc = 0;
1230 
1231 	rc = device_create_file(cpu_subsys.dev_root, &dev_attr_rescan);
1232 	if (rc)
1233 		return rc;
1234 	for_each_present_cpu(cpu) {
1235 		rc = smp_add_present_cpu(cpu);
1236 		if (rc)
1237 			goto out;
1238 	}
1239 
1240 	rc = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "s390/smp:online",
1241 			       smp_cpu_online, smp_cpu_pre_down);
1242 	rc = rc <= 0 ? rc : 0;
1243 out:
1244 	return rc;
1245 }
1246 subsys_initcall(s390_smp_init);
1247 
1248 static __always_inline void set_new_lowcore(struct lowcore *lc)
1249 {
1250 	union register_pair dst, src;
1251 	u32 pfx;
1252 
1253 	src.even = (unsigned long) &S390_lowcore;
1254 	src.odd  = sizeof(S390_lowcore);
1255 	dst.even = (unsigned long) lc;
1256 	dst.odd  = sizeof(*lc);
1257 	pfx = __pa(lc);
1258 
1259 	asm volatile(
1260 		"	mvcl	%[dst],%[src]\n"
1261 		"	spx	%[pfx]\n"
1262 		: [dst] "+&d" (dst.pair), [src] "+&d" (src.pair)
1263 		: [pfx] "Q" (pfx)
1264 		: "memory", "cc");
1265 }
1266 
1267 int __init smp_reinit_ipl_cpu(void)
1268 {
1269 	unsigned long async_stack, nodat_stack, mcck_stack;
1270 	struct lowcore *lc, *lc_ipl;
1271 	unsigned long flags, cr0;
1272 	u64 mcesad;
1273 
1274 	lc_ipl = lowcore_ptr[0];
1275 	lc = (struct lowcore *)	__get_free_pages(GFP_KERNEL | GFP_DMA, LC_ORDER);
1276 	nodat_stack = __get_free_pages(GFP_KERNEL, THREAD_SIZE_ORDER);
1277 	async_stack = stack_alloc();
1278 	mcck_stack = stack_alloc();
1279 	if (!lc || !nodat_stack || !async_stack || !mcck_stack || nmi_alloc_mcesa(&mcesad))
1280 		panic("Couldn't allocate memory");
1281 
1282 	local_irq_save(flags);
1283 	local_mcck_disable();
1284 	set_new_lowcore(lc);
1285 	S390_lowcore.nodat_stack = nodat_stack + STACK_INIT_OFFSET;
1286 	S390_lowcore.async_stack = async_stack + STACK_INIT_OFFSET;
1287 	S390_lowcore.mcck_stack = mcck_stack + STACK_INIT_OFFSET;
1288 	__ctl_store(cr0, 0, 0);
1289 	__ctl_clear_bit(0, 28); /* disable lowcore protection */
1290 	S390_lowcore.mcesad = mcesad;
1291 	__ctl_load(cr0, 0, 0);
1292 	if (abs_lowcore_map(0, lc, false))
1293 		panic("Couldn't remap absolute lowcore");
1294 	lowcore_ptr[0] = lc;
1295 	local_mcck_enable();
1296 	local_irq_restore(flags);
1297 
1298 	free_pages(lc_ipl->async_stack - STACK_INIT_OFFSET, THREAD_SIZE_ORDER);
1299 	memblock_free_late(__pa(lc_ipl->mcck_stack - STACK_INIT_OFFSET), THREAD_SIZE);
1300 	memblock_free_late(__pa(lc_ipl), sizeof(*lc_ipl));
1301 
1302 	return 0;
1303 }
1304