1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Perf PMU sysfs events attributes for available CPU-measurement counters 4 * 5 */ 6 7 #include <linux/slab.h> 8 #include <linux/perf_event.h> 9 #include <asm/cpu_mf.h> 10 11 12 /* BEGIN: CPUM_CF COUNTER DEFINITIONS =================================== */ 13 14 CPUMF_EVENT_ATTR(cf_fvn1, CPU_CYCLES, 0x0000); 15 CPUMF_EVENT_ATTR(cf_fvn1, INSTRUCTIONS, 0x0001); 16 CPUMF_EVENT_ATTR(cf_fvn1, L1I_DIR_WRITES, 0x0002); 17 CPUMF_EVENT_ATTR(cf_fvn1, L1I_PENALTY_CYCLES, 0x0003); 18 CPUMF_EVENT_ATTR(cf_fvn1, PROBLEM_STATE_CPU_CYCLES, 0x0020); 19 CPUMF_EVENT_ATTR(cf_fvn1, PROBLEM_STATE_INSTRUCTIONS, 0x0021); 20 CPUMF_EVENT_ATTR(cf_fvn1, PROBLEM_STATE_L1I_DIR_WRITES, 0x0022); 21 CPUMF_EVENT_ATTR(cf_fvn1, PROBLEM_STATE_L1I_PENALTY_CYCLES, 0x0023); 22 CPUMF_EVENT_ATTR(cf_fvn1, PROBLEM_STATE_L1D_DIR_WRITES, 0x0024); 23 CPUMF_EVENT_ATTR(cf_fvn1, PROBLEM_STATE_L1D_PENALTY_CYCLES, 0x0025); 24 CPUMF_EVENT_ATTR(cf_fvn1, L1D_DIR_WRITES, 0x0004); 25 CPUMF_EVENT_ATTR(cf_fvn1, L1D_PENALTY_CYCLES, 0x0005); 26 CPUMF_EVENT_ATTR(cf_fvn3, CPU_CYCLES, 0x0000); 27 CPUMF_EVENT_ATTR(cf_fvn3, INSTRUCTIONS, 0x0001); 28 CPUMF_EVENT_ATTR(cf_fvn3, L1I_DIR_WRITES, 0x0002); 29 CPUMF_EVENT_ATTR(cf_fvn3, L1I_PENALTY_CYCLES, 0x0003); 30 CPUMF_EVENT_ATTR(cf_fvn3, PROBLEM_STATE_CPU_CYCLES, 0x0020); 31 CPUMF_EVENT_ATTR(cf_fvn3, PROBLEM_STATE_INSTRUCTIONS, 0x0021); 32 CPUMF_EVENT_ATTR(cf_fvn3, L1D_DIR_WRITES, 0x0004); 33 CPUMF_EVENT_ATTR(cf_fvn3, L1D_PENALTY_CYCLES, 0x0005); 34 CPUMF_EVENT_ATTR(cf_svn_generic, PRNG_FUNCTIONS, 0x0040); 35 CPUMF_EVENT_ATTR(cf_svn_generic, PRNG_CYCLES, 0x0041); 36 CPUMF_EVENT_ATTR(cf_svn_generic, PRNG_BLOCKED_FUNCTIONS, 0x0042); 37 CPUMF_EVENT_ATTR(cf_svn_generic, PRNG_BLOCKED_CYCLES, 0x0043); 38 CPUMF_EVENT_ATTR(cf_svn_generic, SHA_FUNCTIONS, 0x0044); 39 CPUMF_EVENT_ATTR(cf_svn_generic, SHA_CYCLES, 0x0045); 40 CPUMF_EVENT_ATTR(cf_svn_generic, SHA_BLOCKED_FUNCTIONS, 0x0046); 41 CPUMF_EVENT_ATTR(cf_svn_generic, SHA_BLOCKED_CYCLES, 0x0047); 42 CPUMF_EVENT_ATTR(cf_svn_generic, DEA_FUNCTIONS, 0x0048); 43 CPUMF_EVENT_ATTR(cf_svn_generic, DEA_CYCLES, 0x0049); 44 CPUMF_EVENT_ATTR(cf_svn_generic, DEA_BLOCKED_FUNCTIONS, 0x004a); 45 CPUMF_EVENT_ATTR(cf_svn_generic, DEA_BLOCKED_CYCLES, 0x004b); 46 CPUMF_EVENT_ATTR(cf_svn_generic, AES_FUNCTIONS, 0x004c); 47 CPUMF_EVENT_ATTR(cf_svn_generic, AES_CYCLES, 0x004d); 48 CPUMF_EVENT_ATTR(cf_svn_generic, AES_BLOCKED_FUNCTIONS, 0x004e); 49 CPUMF_EVENT_ATTR(cf_svn_generic, AES_BLOCKED_CYCLES, 0x004f); 50 CPUMF_EVENT_ATTR(cf_z10, L1I_L2_SOURCED_WRITES, 0x0080); 51 CPUMF_EVENT_ATTR(cf_z10, L1D_L2_SOURCED_WRITES, 0x0081); 52 CPUMF_EVENT_ATTR(cf_z10, L1I_L3_LOCAL_WRITES, 0x0082); 53 CPUMF_EVENT_ATTR(cf_z10, L1D_L3_LOCAL_WRITES, 0x0083); 54 CPUMF_EVENT_ATTR(cf_z10, L1I_L3_REMOTE_WRITES, 0x0084); 55 CPUMF_EVENT_ATTR(cf_z10, L1D_L3_REMOTE_WRITES, 0x0085); 56 CPUMF_EVENT_ATTR(cf_z10, L1D_LMEM_SOURCED_WRITES, 0x0086); 57 CPUMF_EVENT_ATTR(cf_z10, L1I_LMEM_SOURCED_WRITES, 0x0087); 58 CPUMF_EVENT_ATTR(cf_z10, L1D_RO_EXCL_WRITES, 0x0088); 59 CPUMF_EVENT_ATTR(cf_z10, L1I_CACHELINE_INVALIDATES, 0x0089); 60 CPUMF_EVENT_ATTR(cf_z10, ITLB1_WRITES, 0x008a); 61 CPUMF_EVENT_ATTR(cf_z10, DTLB1_WRITES, 0x008b); 62 CPUMF_EVENT_ATTR(cf_z10, TLB2_PTE_WRITES, 0x008c); 63 CPUMF_EVENT_ATTR(cf_z10, TLB2_CRSTE_WRITES, 0x008d); 64 CPUMF_EVENT_ATTR(cf_z10, TLB2_CRSTE_HPAGE_WRITES, 0x008e); 65 CPUMF_EVENT_ATTR(cf_z10, ITLB1_MISSES, 0x0091); 66 CPUMF_EVENT_ATTR(cf_z10, DTLB1_MISSES, 0x0092); 67 CPUMF_EVENT_ATTR(cf_z10, L2C_STORES_SENT, 0x0093); 68 CPUMF_EVENT_ATTR(cf_z196, L1D_L2_SOURCED_WRITES, 0x0080); 69 CPUMF_EVENT_ATTR(cf_z196, L1I_L2_SOURCED_WRITES, 0x0081); 70 CPUMF_EVENT_ATTR(cf_z196, DTLB1_MISSES, 0x0082); 71 CPUMF_EVENT_ATTR(cf_z196, ITLB1_MISSES, 0x0083); 72 CPUMF_EVENT_ATTR(cf_z196, L2C_STORES_SENT, 0x0085); 73 CPUMF_EVENT_ATTR(cf_z196, L1D_OFFBOOK_L3_SOURCED_WRITES, 0x0086); 74 CPUMF_EVENT_ATTR(cf_z196, L1D_ONBOOK_L4_SOURCED_WRITES, 0x0087); 75 CPUMF_EVENT_ATTR(cf_z196, L1I_ONBOOK_L4_SOURCED_WRITES, 0x0088); 76 CPUMF_EVENT_ATTR(cf_z196, L1D_RO_EXCL_WRITES, 0x0089); 77 CPUMF_EVENT_ATTR(cf_z196, L1D_OFFBOOK_L4_SOURCED_WRITES, 0x008a); 78 CPUMF_EVENT_ATTR(cf_z196, L1I_OFFBOOK_L4_SOURCED_WRITES, 0x008b); 79 CPUMF_EVENT_ATTR(cf_z196, DTLB1_HPAGE_WRITES, 0x008c); 80 CPUMF_EVENT_ATTR(cf_z196, L1D_LMEM_SOURCED_WRITES, 0x008d); 81 CPUMF_EVENT_ATTR(cf_z196, L1I_LMEM_SOURCED_WRITES, 0x008e); 82 CPUMF_EVENT_ATTR(cf_z196, L1I_OFFBOOK_L3_SOURCED_WRITES, 0x008f); 83 CPUMF_EVENT_ATTR(cf_z196, DTLB1_WRITES, 0x0090); 84 CPUMF_EVENT_ATTR(cf_z196, ITLB1_WRITES, 0x0091); 85 CPUMF_EVENT_ATTR(cf_z196, TLB2_PTE_WRITES, 0x0092); 86 CPUMF_EVENT_ATTR(cf_z196, TLB2_CRSTE_HPAGE_WRITES, 0x0093); 87 CPUMF_EVENT_ATTR(cf_z196, TLB2_CRSTE_WRITES, 0x0094); 88 CPUMF_EVENT_ATTR(cf_z196, L1D_ONCHIP_L3_SOURCED_WRITES, 0x0096); 89 CPUMF_EVENT_ATTR(cf_z196, L1D_OFFCHIP_L3_SOURCED_WRITES, 0x0098); 90 CPUMF_EVENT_ATTR(cf_z196, L1I_ONCHIP_L3_SOURCED_WRITES, 0x0099); 91 CPUMF_EVENT_ATTR(cf_z196, L1I_OFFCHIP_L3_SOURCED_WRITES, 0x009b); 92 CPUMF_EVENT_ATTR(cf_zec12, DTLB1_MISSES, 0x0080); 93 CPUMF_EVENT_ATTR(cf_zec12, ITLB1_MISSES, 0x0081); 94 CPUMF_EVENT_ATTR(cf_zec12, L1D_L2I_SOURCED_WRITES, 0x0082); 95 CPUMF_EVENT_ATTR(cf_zec12, L1I_L2I_SOURCED_WRITES, 0x0083); 96 CPUMF_EVENT_ATTR(cf_zec12, L1D_L2D_SOURCED_WRITES, 0x0084); 97 CPUMF_EVENT_ATTR(cf_zec12, DTLB1_WRITES, 0x0085); 98 CPUMF_EVENT_ATTR(cf_zec12, L1D_LMEM_SOURCED_WRITES, 0x0087); 99 CPUMF_EVENT_ATTR(cf_zec12, L1I_LMEM_SOURCED_WRITES, 0x0089); 100 CPUMF_EVENT_ATTR(cf_zec12, L1D_RO_EXCL_WRITES, 0x008a); 101 CPUMF_EVENT_ATTR(cf_zec12, DTLB1_HPAGE_WRITES, 0x008b); 102 CPUMF_EVENT_ATTR(cf_zec12, ITLB1_WRITES, 0x008c); 103 CPUMF_EVENT_ATTR(cf_zec12, TLB2_PTE_WRITES, 0x008d); 104 CPUMF_EVENT_ATTR(cf_zec12, TLB2_CRSTE_HPAGE_WRITES, 0x008e); 105 CPUMF_EVENT_ATTR(cf_zec12, TLB2_CRSTE_WRITES, 0x008f); 106 CPUMF_EVENT_ATTR(cf_zec12, L1D_ONCHIP_L3_SOURCED_WRITES, 0x0090); 107 CPUMF_EVENT_ATTR(cf_zec12, L1D_OFFCHIP_L3_SOURCED_WRITES, 0x0091); 108 CPUMF_EVENT_ATTR(cf_zec12, L1D_OFFBOOK_L3_SOURCED_WRITES, 0x0092); 109 CPUMF_EVENT_ATTR(cf_zec12, L1D_ONBOOK_L4_SOURCED_WRITES, 0x0093); 110 CPUMF_EVENT_ATTR(cf_zec12, L1D_OFFBOOK_L4_SOURCED_WRITES, 0x0094); 111 CPUMF_EVENT_ATTR(cf_zec12, TX_NC_TEND, 0x0095); 112 CPUMF_EVENT_ATTR(cf_zec12, L1D_ONCHIP_L3_SOURCED_WRITES_IV, 0x0096); 113 CPUMF_EVENT_ATTR(cf_zec12, L1D_OFFCHIP_L3_SOURCED_WRITES_IV, 0x0097); 114 CPUMF_EVENT_ATTR(cf_zec12, L1D_OFFBOOK_L3_SOURCED_WRITES_IV, 0x0098); 115 CPUMF_EVENT_ATTR(cf_zec12, L1I_ONCHIP_L3_SOURCED_WRITES, 0x0099); 116 CPUMF_EVENT_ATTR(cf_zec12, L1I_OFFCHIP_L3_SOURCED_WRITES, 0x009a); 117 CPUMF_EVENT_ATTR(cf_zec12, L1I_OFFBOOK_L3_SOURCED_WRITES, 0x009b); 118 CPUMF_EVENT_ATTR(cf_zec12, L1I_ONBOOK_L4_SOURCED_WRITES, 0x009c); 119 CPUMF_EVENT_ATTR(cf_zec12, L1I_OFFBOOK_L4_SOURCED_WRITES, 0x009d); 120 CPUMF_EVENT_ATTR(cf_zec12, TX_C_TEND, 0x009e); 121 CPUMF_EVENT_ATTR(cf_zec12, L1I_ONCHIP_L3_SOURCED_WRITES_IV, 0x009f); 122 CPUMF_EVENT_ATTR(cf_zec12, L1I_OFFCHIP_L3_SOURCED_WRITES_IV, 0x00a0); 123 CPUMF_EVENT_ATTR(cf_zec12, L1I_OFFBOOK_L3_SOURCED_WRITES_IV, 0x00a1); 124 CPUMF_EVENT_ATTR(cf_zec12, TX_NC_TABORT, 0x00b1); 125 CPUMF_EVENT_ATTR(cf_zec12, TX_C_TABORT_NO_SPECIAL, 0x00b2); 126 CPUMF_EVENT_ATTR(cf_zec12, TX_C_TABORT_SPECIAL, 0x00b3); 127 CPUMF_EVENT_ATTR(cf_z13, L1D_RO_EXCL_WRITES, 0x0080); 128 CPUMF_EVENT_ATTR(cf_z13, DTLB1_WRITES, 0x0081); 129 CPUMF_EVENT_ATTR(cf_z13, DTLB1_MISSES, 0x0082); 130 CPUMF_EVENT_ATTR(cf_z13, DTLB1_HPAGE_WRITES, 0x0083); 131 CPUMF_EVENT_ATTR(cf_z13, DTLB1_GPAGE_WRITES, 0x0084); 132 CPUMF_EVENT_ATTR(cf_z13, L1D_L2D_SOURCED_WRITES, 0x0085); 133 CPUMF_EVENT_ATTR(cf_z13, ITLB1_WRITES, 0x0086); 134 CPUMF_EVENT_ATTR(cf_z13, ITLB1_MISSES, 0x0087); 135 CPUMF_EVENT_ATTR(cf_z13, L1I_L2I_SOURCED_WRITES, 0x0088); 136 CPUMF_EVENT_ATTR(cf_z13, TLB2_PTE_WRITES, 0x0089); 137 CPUMF_EVENT_ATTR(cf_z13, TLB2_CRSTE_HPAGE_WRITES, 0x008a); 138 CPUMF_EVENT_ATTR(cf_z13, TLB2_CRSTE_WRITES, 0x008b); 139 CPUMF_EVENT_ATTR(cf_z13, TX_C_TEND, 0x008c); 140 CPUMF_EVENT_ATTR(cf_z13, TX_NC_TEND, 0x008d); 141 CPUMF_EVENT_ATTR(cf_z13, L1C_TLB1_MISSES, 0x008f); 142 CPUMF_EVENT_ATTR(cf_z13, L1D_ONCHIP_L3_SOURCED_WRITES, 0x0090); 143 CPUMF_EVENT_ATTR(cf_z13, L1D_ONCHIP_L3_SOURCED_WRITES_IV, 0x0091); 144 CPUMF_EVENT_ATTR(cf_z13, L1D_ONNODE_L4_SOURCED_WRITES, 0x0092); 145 CPUMF_EVENT_ATTR(cf_z13, L1D_ONNODE_L3_SOURCED_WRITES_IV, 0x0093); 146 CPUMF_EVENT_ATTR(cf_z13, L1D_ONNODE_L3_SOURCED_WRITES, 0x0094); 147 CPUMF_EVENT_ATTR(cf_z13, L1D_ONDRAWER_L4_SOURCED_WRITES, 0x0095); 148 CPUMF_EVENT_ATTR(cf_z13, L1D_ONDRAWER_L3_SOURCED_WRITES_IV, 0x0096); 149 CPUMF_EVENT_ATTR(cf_z13, L1D_ONDRAWER_L3_SOURCED_WRITES, 0x0097); 150 CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_SCOL_L4_SOURCED_WRITES, 0x0098); 151 CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV, 0x0099); 152 CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES, 0x009a); 153 CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_FCOL_L4_SOURCED_WRITES, 0x009b); 154 CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV, 0x009c); 155 CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES, 0x009d); 156 CPUMF_EVENT_ATTR(cf_z13, L1D_ONNODE_MEM_SOURCED_WRITES, 0x009e); 157 CPUMF_EVENT_ATTR(cf_z13, L1D_ONDRAWER_MEM_SOURCED_WRITES, 0x009f); 158 CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_MEM_SOURCED_WRITES, 0x00a0); 159 CPUMF_EVENT_ATTR(cf_z13, L1D_ONCHIP_MEM_SOURCED_WRITES, 0x00a1); 160 CPUMF_EVENT_ATTR(cf_z13, L1I_ONCHIP_L3_SOURCED_WRITES, 0x00a2); 161 CPUMF_EVENT_ATTR(cf_z13, L1I_ONCHIP_L3_SOURCED_WRITES_IV, 0x00a3); 162 CPUMF_EVENT_ATTR(cf_z13, L1I_ONNODE_L4_SOURCED_WRITES, 0x00a4); 163 CPUMF_EVENT_ATTR(cf_z13, L1I_ONNODE_L3_SOURCED_WRITES_IV, 0x00a5); 164 CPUMF_EVENT_ATTR(cf_z13, L1I_ONNODE_L3_SOURCED_WRITES, 0x00a6); 165 CPUMF_EVENT_ATTR(cf_z13, L1I_ONDRAWER_L4_SOURCED_WRITES, 0x00a7); 166 CPUMF_EVENT_ATTR(cf_z13, L1I_ONDRAWER_L3_SOURCED_WRITES_IV, 0x00a8); 167 CPUMF_EVENT_ATTR(cf_z13, L1I_ONDRAWER_L3_SOURCED_WRITES, 0x00a9); 168 CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_SCOL_L4_SOURCED_WRITES, 0x00aa); 169 CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV, 0x00ab); 170 CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES, 0x00ac); 171 CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_FCOL_L4_SOURCED_WRITES, 0x00ad); 172 CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV, 0x00ae); 173 CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES, 0x00af); 174 CPUMF_EVENT_ATTR(cf_z13, L1I_ONNODE_MEM_SOURCED_WRITES, 0x00b0); 175 CPUMF_EVENT_ATTR(cf_z13, L1I_ONDRAWER_MEM_SOURCED_WRITES, 0x00b1); 176 CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_MEM_SOURCED_WRITES, 0x00b2); 177 CPUMF_EVENT_ATTR(cf_z13, L1I_ONCHIP_MEM_SOURCED_WRITES, 0x00b3); 178 CPUMF_EVENT_ATTR(cf_z13, TX_NC_TABORT, 0x00da); 179 CPUMF_EVENT_ATTR(cf_z13, TX_C_TABORT_NO_SPECIAL, 0x00db); 180 CPUMF_EVENT_ATTR(cf_z13, TX_C_TABORT_SPECIAL, 0x00dc); 181 CPUMF_EVENT_ATTR(cf_z13, MT_DIAG_CYCLES_ONE_THR_ACTIVE, 0x01c0); 182 CPUMF_EVENT_ATTR(cf_z13, MT_DIAG_CYCLES_TWO_THR_ACTIVE, 0x01c1); 183 CPUMF_EVENT_ATTR(cf_z14, L1D_RO_EXCL_WRITES, 0x0080); 184 CPUMF_EVENT_ATTR(cf_z14, DTLB2_WRITES, 0x0081); 185 CPUMF_EVENT_ATTR(cf_z14, DTLB2_MISSES, 0x0082); 186 CPUMF_EVENT_ATTR(cf_z14, DTLB2_HPAGE_WRITES, 0x0083); 187 CPUMF_EVENT_ATTR(cf_z14, DTLB2_GPAGE_WRITES, 0x0084); 188 CPUMF_EVENT_ATTR(cf_z14, L1D_L2D_SOURCED_WRITES, 0x0085); 189 CPUMF_EVENT_ATTR(cf_z14, ITLB2_WRITES, 0x0086); 190 CPUMF_EVENT_ATTR(cf_z14, ITLB2_MISSES, 0x0087); 191 CPUMF_EVENT_ATTR(cf_z14, L1I_L2I_SOURCED_WRITES, 0x0088); 192 CPUMF_EVENT_ATTR(cf_z14, TLB2_PTE_WRITES, 0x0089); 193 CPUMF_EVENT_ATTR(cf_z14, TLB2_CRSTE_WRITES, 0x008a); 194 CPUMF_EVENT_ATTR(cf_z14, TLB2_ENGINES_BUSY, 0x008b); 195 CPUMF_EVENT_ATTR(cf_z14, TX_C_TEND, 0x008c); 196 CPUMF_EVENT_ATTR(cf_z14, TX_NC_TEND, 0x008d); 197 CPUMF_EVENT_ATTR(cf_z14, L1C_TLB2_MISSES, 0x008f); 198 CPUMF_EVENT_ATTR(cf_z14, L1D_ONCHIP_L3_SOURCED_WRITES, 0x0090); 199 CPUMF_EVENT_ATTR(cf_z14, L1D_ONCHIP_MEMORY_SOURCED_WRITES, 0x0091); 200 CPUMF_EVENT_ATTR(cf_z14, L1D_ONCHIP_L3_SOURCED_WRITES_IV, 0x0092); 201 CPUMF_EVENT_ATTR(cf_z14, L1D_ONCLUSTER_L3_SOURCED_WRITES, 0x0093); 202 CPUMF_EVENT_ATTR(cf_z14, L1D_ONCLUSTER_MEMORY_SOURCED_WRITES, 0x0094); 203 CPUMF_EVENT_ATTR(cf_z14, L1D_ONCLUSTER_L3_SOURCED_WRITES_IV, 0x0095); 204 CPUMF_EVENT_ATTR(cf_z14, L1D_OFFCLUSTER_L3_SOURCED_WRITES, 0x0096); 205 CPUMF_EVENT_ATTR(cf_z14, L1D_OFFCLUSTER_MEMORY_SOURCED_WRITES, 0x0097); 206 CPUMF_EVENT_ATTR(cf_z14, L1D_OFFCLUSTER_L3_SOURCED_WRITES_IV, 0x0098); 207 CPUMF_EVENT_ATTR(cf_z14, L1D_OFFDRAWER_L3_SOURCED_WRITES, 0x0099); 208 CPUMF_EVENT_ATTR(cf_z14, L1D_OFFDRAWER_MEMORY_SOURCED_WRITES, 0x009a); 209 CPUMF_EVENT_ATTR(cf_z14, L1D_OFFDRAWER_L3_SOURCED_WRITES_IV, 0x009b); 210 CPUMF_EVENT_ATTR(cf_z14, L1D_ONDRAWER_L4_SOURCED_WRITES, 0x009c); 211 CPUMF_EVENT_ATTR(cf_z14, L1D_OFFDRAWER_L4_SOURCED_WRITES, 0x009d); 212 CPUMF_EVENT_ATTR(cf_z14, L1D_ONCHIP_L3_SOURCED_WRITES_RO, 0x009e); 213 CPUMF_EVENT_ATTR(cf_z14, L1I_ONCHIP_L3_SOURCED_WRITES, 0x00a2); 214 CPUMF_EVENT_ATTR(cf_z14, L1I_ONCHIP_MEMORY_SOURCED_WRITES, 0x00a3); 215 CPUMF_EVENT_ATTR(cf_z14, L1I_ONCHIP_L3_SOURCED_WRITES_IV, 0x00a4); 216 CPUMF_EVENT_ATTR(cf_z14, L1I_ONCLUSTER_L3_SOURCED_WRITES, 0x00a5); 217 CPUMF_EVENT_ATTR(cf_z14, L1I_ONCLUSTER_MEMORY_SOURCED_WRITES, 0x00a6); 218 CPUMF_EVENT_ATTR(cf_z14, L1I_ONCLUSTER_L3_SOURCED_WRITES_IV, 0x00a7); 219 CPUMF_EVENT_ATTR(cf_z14, L1I_OFFCLUSTER_L3_SOURCED_WRITES, 0x00a8); 220 CPUMF_EVENT_ATTR(cf_z14, L1I_OFFCLUSTER_MEMORY_SOURCED_WRITES, 0x00a9); 221 CPUMF_EVENT_ATTR(cf_z14, L1I_OFFCLUSTER_L3_SOURCED_WRITES_IV, 0x00aa); 222 CPUMF_EVENT_ATTR(cf_z14, L1I_OFFDRAWER_L3_SOURCED_WRITES, 0x00ab); 223 CPUMF_EVENT_ATTR(cf_z14, L1I_OFFDRAWER_MEMORY_SOURCED_WRITES, 0x00ac); 224 CPUMF_EVENT_ATTR(cf_z14, L1I_OFFDRAWER_L3_SOURCED_WRITES_IV, 0x00ad); 225 CPUMF_EVENT_ATTR(cf_z14, L1I_ONDRAWER_L4_SOURCED_WRITES, 0x00ae); 226 CPUMF_EVENT_ATTR(cf_z14, L1I_OFFDRAWER_L4_SOURCED_WRITES, 0x00af); 227 CPUMF_EVENT_ATTR(cf_z14, BCD_DFP_EXECUTION_SLOTS, 0x00e0); 228 CPUMF_EVENT_ATTR(cf_z14, VX_BCD_EXECUTION_SLOTS, 0x00e1); 229 CPUMF_EVENT_ATTR(cf_z14, DECIMAL_INSTRUCTIONS, 0x00e2); 230 CPUMF_EVENT_ATTR(cf_z14, LAST_HOST_TRANSLATIONS, 0x00e8); 231 CPUMF_EVENT_ATTR(cf_z14, TX_NC_TABORT, 0x00f3); 232 CPUMF_EVENT_ATTR(cf_z14, TX_C_TABORT_NO_SPECIAL, 0x00f4); 233 CPUMF_EVENT_ATTR(cf_z14, TX_C_TABORT_SPECIAL, 0x00f5); 234 CPUMF_EVENT_ATTR(cf_z14, MT_DIAG_CYCLES_ONE_THR_ACTIVE, 0x01c0); 235 CPUMF_EVENT_ATTR(cf_z14, MT_DIAG_CYCLES_TWO_THR_ACTIVE, 0x01c1); 236 237 static struct attribute *cpumcf_fvn1_pmu_event_attr[] __initdata = { 238 CPUMF_EVENT_PTR(cf_fvn1, CPU_CYCLES), 239 CPUMF_EVENT_PTR(cf_fvn1, INSTRUCTIONS), 240 CPUMF_EVENT_PTR(cf_fvn1, L1I_DIR_WRITES), 241 CPUMF_EVENT_PTR(cf_fvn1, L1I_PENALTY_CYCLES), 242 CPUMF_EVENT_PTR(cf_fvn1, PROBLEM_STATE_CPU_CYCLES), 243 CPUMF_EVENT_PTR(cf_fvn1, PROBLEM_STATE_INSTRUCTIONS), 244 CPUMF_EVENT_PTR(cf_fvn1, PROBLEM_STATE_L1I_DIR_WRITES), 245 CPUMF_EVENT_PTR(cf_fvn1, PROBLEM_STATE_L1I_PENALTY_CYCLES), 246 CPUMF_EVENT_PTR(cf_fvn1, PROBLEM_STATE_L1D_DIR_WRITES), 247 CPUMF_EVENT_PTR(cf_fvn1, PROBLEM_STATE_L1D_PENALTY_CYCLES), 248 CPUMF_EVENT_PTR(cf_fvn1, L1D_DIR_WRITES), 249 CPUMF_EVENT_PTR(cf_fvn1, L1D_PENALTY_CYCLES), 250 NULL, 251 }; 252 253 static struct attribute *cpumcf_fvn3_pmu_event_attr[] __initdata = { 254 CPUMF_EVENT_PTR(cf_fvn3, CPU_CYCLES), 255 CPUMF_EVENT_PTR(cf_fvn3, INSTRUCTIONS), 256 CPUMF_EVENT_PTR(cf_fvn3, L1I_DIR_WRITES), 257 CPUMF_EVENT_PTR(cf_fvn3, L1I_PENALTY_CYCLES), 258 CPUMF_EVENT_PTR(cf_fvn3, PROBLEM_STATE_CPU_CYCLES), 259 CPUMF_EVENT_PTR(cf_fvn3, PROBLEM_STATE_INSTRUCTIONS), 260 CPUMF_EVENT_PTR(cf_fvn3, L1D_DIR_WRITES), 261 CPUMF_EVENT_PTR(cf_fvn3, L1D_PENALTY_CYCLES), 262 NULL, 263 }; 264 265 static struct attribute *cpumcf_svn_generic_pmu_event_attr[] __initdata = { 266 CPUMF_EVENT_PTR(cf_svn_generic, PRNG_FUNCTIONS), 267 CPUMF_EVENT_PTR(cf_svn_generic, PRNG_CYCLES), 268 CPUMF_EVENT_PTR(cf_svn_generic, PRNG_BLOCKED_FUNCTIONS), 269 CPUMF_EVENT_PTR(cf_svn_generic, PRNG_BLOCKED_CYCLES), 270 CPUMF_EVENT_PTR(cf_svn_generic, SHA_FUNCTIONS), 271 CPUMF_EVENT_PTR(cf_svn_generic, SHA_CYCLES), 272 CPUMF_EVENT_PTR(cf_svn_generic, SHA_BLOCKED_FUNCTIONS), 273 CPUMF_EVENT_PTR(cf_svn_generic, SHA_BLOCKED_CYCLES), 274 CPUMF_EVENT_PTR(cf_svn_generic, DEA_FUNCTIONS), 275 CPUMF_EVENT_PTR(cf_svn_generic, DEA_CYCLES), 276 CPUMF_EVENT_PTR(cf_svn_generic, DEA_BLOCKED_FUNCTIONS), 277 CPUMF_EVENT_PTR(cf_svn_generic, DEA_BLOCKED_CYCLES), 278 CPUMF_EVENT_PTR(cf_svn_generic, AES_FUNCTIONS), 279 CPUMF_EVENT_PTR(cf_svn_generic, AES_CYCLES), 280 CPUMF_EVENT_PTR(cf_svn_generic, AES_BLOCKED_FUNCTIONS), 281 CPUMF_EVENT_PTR(cf_svn_generic, AES_BLOCKED_CYCLES), 282 NULL, 283 }; 284 285 static struct attribute *cpumcf_z10_pmu_event_attr[] __initdata = { 286 CPUMF_EVENT_PTR(cf_z10, L1I_L2_SOURCED_WRITES), 287 CPUMF_EVENT_PTR(cf_z10, L1D_L2_SOURCED_WRITES), 288 CPUMF_EVENT_PTR(cf_z10, L1I_L3_LOCAL_WRITES), 289 CPUMF_EVENT_PTR(cf_z10, L1D_L3_LOCAL_WRITES), 290 CPUMF_EVENT_PTR(cf_z10, L1I_L3_REMOTE_WRITES), 291 CPUMF_EVENT_PTR(cf_z10, L1D_L3_REMOTE_WRITES), 292 CPUMF_EVENT_PTR(cf_z10, L1D_LMEM_SOURCED_WRITES), 293 CPUMF_EVENT_PTR(cf_z10, L1I_LMEM_SOURCED_WRITES), 294 CPUMF_EVENT_PTR(cf_z10, L1D_RO_EXCL_WRITES), 295 CPUMF_EVENT_PTR(cf_z10, L1I_CACHELINE_INVALIDATES), 296 CPUMF_EVENT_PTR(cf_z10, ITLB1_WRITES), 297 CPUMF_EVENT_PTR(cf_z10, DTLB1_WRITES), 298 CPUMF_EVENT_PTR(cf_z10, TLB2_PTE_WRITES), 299 CPUMF_EVENT_PTR(cf_z10, TLB2_CRSTE_WRITES), 300 CPUMF_EVENT_PTR(cf_z10, TLB2_CRSTE_HPAGE_WRITES), 301 CPUMF_EVENT_PTR(cf_z10, ITLB1_MISSES), 302 CPUMF_EVENT_PTR(cf_z10, DTLB1_MISSES), 303 CPUMF_EVENT_PTR(cf_z10, L2C_STORES_SENT), 304 NULL, 305 }; 306 307 static struct attribute *cpumcf_z196_pmu_event_attr[] __initdata = { 308 CPUMF_EVENT_PTR(cf_z196, L1D_L2_SOURCED_WRITES), 309 CPUMF_EVENT_PTR(cf_z196, L1I_L2_SOURCED_WRITES), 310 CPUMF_EVENT_PTR(cf_z196, DTLB1_MISSES), 311 CPUMF_EVENT_PTR(cf_z196, ITLB1_MISSES), 312 CPUMF_EVENT_PTR(cf_z196, L2C_STORES_SENT), 313 CPUMF_EVENT_PTR(cf_z196, L1D_OFFBOOK_L3_SOURCED_WRITES), 314 CPUMF_EVENT_PTR(cf_z196, L1D_ONBOOK_L4_SOURCED_WRITES), 315 CPUMF_EVENT_PTR(cf_z196, L1I_ONBOOK_L4_SOURCED_WRITES), 316 CPUMF_EVENT_PTR(cf_z196, L1D_RO_EXCL_WRITES), 317 CPUMF_EVENT_PTR(cf_z196, L1D_OFFBOOK_L4_SOURCED_WRITES), 318 CPUMF_EVENT_PTR(cf_z196, L1I_OFFBOOK_L4_SOURCED_WRITES), 319 CPUMF_EVENT_PTR(cf_z196, DTLB1_HPAGE_WRITES), 320 CPUMF_EVENT_PTR(cf_z196, L1D_LMEM_SOURCED_WRITES), 321 CPUMF_EVENT_PTR(cf_z196, L1I_LMEM_SOURCED_WRITES), 322 CPUMF_EVENT_PTR(cf_z196, L1I_OFFBOOK_L3_SOURCED_WRITES), 323 CPUMF_EVENT_PTR(cf_z196, DTLB1_WRITES), 324 CPUMF_EVENT_PTR(cf_z196, ITLB1_WRITES), 325 CPUMF_EVENT_PTR(cf_z196, TLB2_PTE_WRITES), 326 CPUMF_EVENT_PTR(cf_z196, TLB2_CRSTE_HPAGE_WRITES), 327 CPUMF_EVENT_PTR(cf_z196, TLB2_CRSTE_WRITES), 328 CPUMF_EVENT_PTR(cf_z196, L1D_ONCHIP_L3_SOURCED_WRITES), 329 CPUMF_EVENT_PTR(cf_z196, L1D_OFFCHIP_L3_SOURCED_WRITES), 330 CPUMF_EVENT_PTR(cf_z196, L1I_ONCHIP_L3_SOURCED_WRITES), 331 CPUMF_EVENT_PTR(cf_z196, L1I_OFFCHIP_L3_SOURCED_WRITES), 332 NULL, 333 }; 334 335 static struct attribute *cpumcf_zec12_pmu_event_attr[] __initdata = { 336 CPUMF_EVENT_PTR(cf_zec12, DTLB1_MISSES), 337 CPUMF_EVENT_PTR(cf_zec12, ITLB1_MISSES), 338 CPUMF_EVENT_PTR(cf_zec12, L1D_L2I_SOURCED_WRITES), 339 CPUMF_EVENT_PTR(cf_zec12, L1I_L2I_SOURCED_WRITES), 340 CPUMF_EVENT_PTR(cf_zec12, L1D_L2D_SOURCED_WRITES), 341 CPUMF_EVENT_PTR(cf_zec12, DTLB1_WRITES), 342 CPUMF_EVENT_PTR(cf_zec12, L1D_LMEM_SOURCED_WRITES), 343 CPUMF_EVENT_PTR(cf_zec12, L1I_LMEM_SOURCED_WRITES), 344 CPUMF_EVENT_PTR(cf_zec12, L1D_RO_EXCL_WRITES), 345 CPUMF_EVENT_PTR(cf_zec12, DTLB1_HPAGE_WRITES), 346 CPUMF_EVENT_PTR(cf_zec12, ITLB1_WRITES), 347 CPUMF_EVENT_PTR(cf_zec12, TLB2_PTE_WRITES), 348 CPUMF_EVENT_PTR(cf_zec12, TLB2_CRSTE_HPAGE_WRITES), 349 CPUMF_EVENT_PTR(cf_zec12, TLB2_CRSTE_WRITES), 350 CPUMF_EVENT_PTR(cf_zec12, L1D_ONCHIP_L3_SOURCED_WRITES), 351 CPUMF_EVENT_PTR(cf_zec12, L1D_OFFCHIP_L3_SOURCED_WRITES), 352 CPUMF_EVENT_PTR(cf_zec12, L1D_OFFBOOK_L3_SOURCED_WRITES), 353 CPUMF_EVENT_PTR(cf_zec12, L1D_ONBOOK_L4_SOURCED_WRITES), 354 CPUMF_EVENT_PTR(cf_zec12, L1D_OFFBOOK_L4_SOURCED_WRITES), 355 CPUMF_EVENT_PTR(cf_zec12, TX_NC_TEND), 356 CPUMF_EVENT_PTR(cf_zec12, L1D_ONCHIP_L3_SOURCED_WRITES_IV), 357 CPUMF_EVENT_PTR(cf_zec12, L1D_OFFCHIP_L3_SOURCED_WRITES_IV), 358 CPUMF_EVENT_PTR(cf_zec12, L1D_OFFBOOK_L3_SOURCED_WRITES_IV), 359 CPUMF_EVENT_PTR(cf_zec12, L1I_ONCHIP_L3_SOURCED_WRITES), 360 CPUMF_EVENT_PTR(cf_zec12, L1I_OFFCHIP_L3_SOURCED_WRITES), 361 CPUMF_EVENT_PTR(cf_zec12, L1I_OFFBOOK_L3_SOURCED_WRITES), 362 CPUMF_EVENT_PTR(cf_zec12, L1I_ONBOOK_L4_SOURCED_WRITES), 363 CPUMF_EVENT_PTR(cf_zec12, L1I_OFFBOOK_L4_SOURCED_WRITES), 364 CPUMF_EVENT_PTR(cf_zec12, TX_C_TEND), 365 CPUMF_EVENT_PTR(cf_zec12, L1I_ONCHIP_L3_SOURCED_WRITES_IV), 366 CPUMF_EVENT_PTR(cf_zec12, L1I_OFFCHIP_L3_SOURCED_WRITES_IV), 367 CPUMF_EVENT_PTR(cf_zec12, L1I_OFFBOOK_L3_SOURCED_WRITES_IV), 368 CPUMF_EVENT_PTR(cf_zec12, TX_NC_TABORT), 369 CPUMF_EVENT_PTR(cf_zec12, TX_C_TABORT_NO_SPECIAL), 370 CPUMF_EVENT_PTR(cf_zec12, TX_C_TABORT_SPECIAL), 371 NULL, 372 }; 373 374 static struct attribute *cpumcf_z13_pmu_event_attr[] __initdata = { 375 CPUMF_EVENT_PTR(cf_z13, L1D_RO_EXCL_WRITES), 376 CPUMF_EVENT_PTR(cf_z13, DTLB1_WRITES), 377 CPUMF_EVENT_PTR(cf_z13, DTLB1_MISSES), 378 CPUMF_EVENT_PTR(cf_z13, DTLB1_HPAGE_WRITES), 379 CPUMF_EVENT_PTR(cf_z13, DTLB1_GPAGE_WRITES), 380 CPUMF_EVENT_PTR(cf_z13, L1D_L2D_SOURCED_WRITES), 381 CPUMF_EVENT_PTR(cf_z13, ITLB1_WRITES), 382 CPUMF_EVENT_PTR(cf_z13, ITLB1_MISSES), 383 CPUMF_EVENT_PTR(cf_z13, L1I_L2I_SOURCED_WRITES), 384 CPUMF_EVENT_PTR(cf_z13, TLB2_PTE_WRITES), 385 CPUMF_EVENT_PTR(cf_z13, TLB2_CRSTE_HPAGE_WRITES), 386 CPUMF_EVENT_PTR(cf_z13, TLB2_CRSTE_WRITES), 387 CPUMF_EVENT_PTR(cf_z13, TX_C_TEND), 388 CPUMF_EVENT_PTR(cf_z13, TX_NC_TEND), 389 CPUMF_EVENT_PTR(cf_z13, L1C_TLB1_MISSES), 390 CPUMF_EVENT_PTR(cf_z13, L1D_ONCHIP_L3_SOURCED_WRITES), 391 CPUMF_EVENT_PTR(cf_z13, L1D_ONCHIP_L3_SOURCED_WRITES_IV), 392 CPUMF_EVENT_PTR(cf_z13, L1D_ONNODE_L4_SOURCED_WRITES), 393 CPUMF_EVENT_PTR(cf_z13, L1D_ONNODE_L3_SOURCED_WRITES_IV), 394 CPUMF_EVENT_PTR(cf_z13, L1D_ONNODE_L3_SOURCED_WRITES), 395 CPUMF_EVENT_PTR(cf_z13, L1D_ONDRAWER_L4_SOURCED_WRITES), 396 CPUMF_EVENT_PTR(cf_z13, L1D_ONDRAWER_L3_SOURCED_WRITES_IV), 397 CPUMF_EVENT_PTR(cf_z13, L1D_ONDRAWER_L3_SOURCED_WRITES), 398 CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_SCOL_L4_SOURCED_WRITES), 399 CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV), 400 CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES), 401 CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_FCOL_L4_SOURCED_WRITES), 402 CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV), 403 CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES), 404 CPUMF_EVENT_PTR(cf_z13, L1D_ONNODE_MEM_SOURCED_WRITES), 405 CPUMF_EVENT_PTR(cf_z13, L1D_ONDRAWER_MEM_SOURCED_WRITES), 406 CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_MEM_SOURCED_WRITES), 407 CPUMF_EVENT_PTR(cf_z13, L1D_ONCHIP_MEM_SOURCED_WRITES), 408 CPUMF_EVENT_PTR(cf_z13, L1I_ONCHIP_L3_SOURCED_WRITES), 409 CPUMF_EVENT_PTR(cf_z13, L1I_ONCHIP_L3_SOURCED_WRITES_IV), 410 CPUMF_EVENT_PTR(cf_z13, L1I_ONNODE_L4_SOURCED_WRITES), 411 CPUMF_EVENT_PTR(cf_z13, L1I_ONNODE_L3_SOURCED_WRITES_IV), 412 CPUMF_EVENT_PTR(cf_z13, L1I_ONNODE_L3_SOURCED_WRITES), 413 CPUMF_EVENT_PTR(cf_z13, L1I_ONDRAWER_L4_SOURCED_WRITES), 414 CPUMF_EVENT_PTR(cf_z13, L1I_ONDRAWER_L3_SOURCED_WRITES_IV), 415 CPUMF_EVENT_PTR(cf_z13, L1I_ONDRAWER_L3_SOURCED_WRITES), 416 CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_SCOL_L4_SOURCED_WRITES), 417 CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV), 418 CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES), 419 CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_FCOL_L4_SOURCED_WRITES), 420 CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV), 421 CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES), 422 CPUMF_EVENT_PTR(cf_z13, L1I_ONNODE_MEM_SOURCED_WRITES), 423 CPUMF_EVENT_PTR(cf_z13, L1I_ONDRAWER_MEM_SOURCED_WRITES), 424 CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_MEM_SOURCED_WRITES), 425 CPUMF_EVENT_PTR(cf_z13, L1I_ONCHIP_MEM_SOURCED_WRITES), 426 CPUMF_EVENT_PTR(cf_z13, TX_NC_TABORT), 427 CPUMF_EVENT_PTR(cf_z13, TX_C_TABORT_NO_SPECIAL), 428 CPUMF_EVENT_PTR(cf_z13, TX_C_TABORT_SPECIAL), 429 CPUMF_EVENT_PTR(cf_z13, MT_DIAG_CYCLES_ONE_THR_ACTIVE), 430 CPUMF_EVENT_PTR(cf_z13, MT_DIAG_CYCLES_TWO_THR_ACTIVE), 431 NULL, 432 }; 433 434 static struct attribute *cpumcf_z14_pmu_event_attr[] __initdata = { 435 CPUMF_EVENT_PTR(cf_z14, L1D_RO_EXCL_WRITES), 436 CPUMF_EVENT_PTR(cf_z14, DTLB2_WRITES), 437 CPUMF_EVENT_PTR(cf_z14, DTLB2_MISSES), 438 CPUMF_EVENT_PTR(cf_z14, DTLB2_HPAGE_WRITES), 439 CPUMF_EVENT_PTR(cf_z14, DTLB2_GPAGE_WRITES), 440 CPUMF_EVENT_PTR(cf_z14, L1D_L2D_SOURCED_WRITES), 441 CPUMF_EVENT_PTR(cf_z14, ITLB2_WRITES), 442 CPUMF_EVENT_PTR(cf_z14, ITLB2_MISSES), 443 CPUMF_EVENT_PTR(cf_z14, L1I_L2I_SOURCED_WRITES), 444 CPUMF_EVENT_PTR(cf_z14, TLB2_PTE_WRITES), 445 CPUMF_EVENT_PTR(cf_z14, TLB2_CRSTE_WRITES), 446 CPUMF_EVENT_PTR(cf_z14, TLB2_ENGINES_BUSY), 447 CPUMF_EVENT_PTR(cf_z14, TX_C_TEND), 448 CPUMF_EVENT_PTR(cf_z14, TX_NC_TEND), 449 CPUMF_EVENT_PTR(cf_z14, L1C_TLB2_MISSES), 450 CPUMF_EVENT_PTR(cf_z14, L1D_ONCHIP_L3_SOURCED_WRITES), 451 CPUMF_EVENT_PTR(cf_z14, L1D_ONCHIP_MEMORY_SOURCED_WRITES), 452 CPUMF_EVENT_PTR(cf_z14, L1D_ONCHIP_L3_SOURCED_WRITES_IV), 453 CPUMF_EVENT_PTR(cf_z14, L1D_ONCLUSTER_L3_SOURCED_WRITES), 454 CPUMF_EVENT_PTR(cf_z14, L1D_ONCLUSTER_MEMORY_SOURCED_WRITES), 455 CPUMF_EVENT_PTR(cf_z14, L1D_ONCLUSTER_L3_SOURCED_WRITES_IV), 456 CPUMF_EVENT_PTR(cf_z14, L1D_OFFCLUSTER_L3_SOURCED_WRITES), 457 CPUMF_EVENT_PTR(cf_z14, L1D_OFFCLUSTER_MEMORY_SOURCED_WRITES), 458 CPUMF_EVENT_PTR(cf_z14, L1D_OFFCLUSTER_L3_SOURCED_WRITES_IV), 459 CPUMF_EVENT_PTR(cf_z14, L1D_OFFDRAWER_L3_SOURCED_WRITES), 460 CPUMF_EVENT_PTR(cf_z14, L1D_OFFDRAWER_MEMORY_SOURCED_WRITES), 461 CPUMF_EVENT_PTR(cf_z14, L1D_OFFDRAWER_L3_SOURCED_WRITES_IV), 462 CPUMF_EVENT_PTR(cf_z14, L1D_ONDRAWER_L4_SOURCED_WRITES), 463 CPUMF_EVENT_PTR(cf_z14, L1D_OFFDRAWER_L4_SOURCED_WRITES), 464 CPUMF_EVENT_PTR(cf_z14, L1D_ONCHIP_L3_SOURCED_WRITES_RO), 465 CPUMF_EVENT_PTR(cf_z14, L1I_ONCHIP_L3_SOURCED_WRITES), 466 CPUMF_EVENT_PTR(cf_z14, L1I_ONCHIP_MEMORY_SOURCED_WRITES), 467 CPUMF_EVENT_PTR(cf_z14, L1I_ONCHIP_L3_SOURCED_WRITES_IV), 468 CPUMF_EVENT_PTR(cf_z14, L1I_ONCLUSTER_L3_SOURCED_WRITES), 469 CPUMF_EVENT_PTR(cf_z14, L1I_ONCLUSTER_MEMORY_SOURCED_WRITES), 470 CPUMF_EVENT_PTR(cf_z14, L1I_ONCLUSTER_L3_SOURCED_WRITES_IV), 471 CPUMF_EVENT_PTR(cf_z14, L1I_OFFCLUSTER_L3_SOURCED_WRITES), 472 CPUMF_EVENT_PTR(cf_z14, L1I_OFFCLUSTER_MEMORY_SOURCED_WRITES), 473 CPUMF_EVENT_PTR(cf_z14, L1I_OFFCLUSTER_L3_SOURCED_WRITES_IV), 474 CPUMF_EVENT_PTR(cf_z14, L1I_OFFDRAWER_L3_SOURCED_WRITES), 475 CPUMF_EVENT_PTR(cf_z14, L1I_OFFDRAWER_MEMORY_SOURCED_WRITES), 476 CPUMF_EVENT_PTR(cf_z14, L1I_OFFDRAWER_L3_SOURCED_WRITES_IV), 477 CPUMF_EVENT_PTR(cf_z14, L1I_ONDRAWER_L4_SOURCED_WRITES), 478 CPUMF_EVENT_PTR(cf_z14, L1I_OFFDRAWER_L4_SOURCED_WRITES), 479 CPUMF_EVENT_PTR(cf_z14, BCD_DFP_EXECUTION_SLOTS), 480 CPUMF_EVENT_PTR(cf_z14, VX_BCD_EXECUTION_SLOTS), 481 CPUMF_EVENT_PTR(cf_z14, DECIMAL_INSTRUCTIONS), 482 CPUMF_EVENT_PTR(cf_z14, LAST_HOST_TRANSLATIONS), 483 CPUMF_EVENT_PTR(cf_z14, TX_NC_TABORT), 484 CPUMF_EVENT_PTR(cf_z14, TX_C_TABORT_NO_SPECIAL), 485 CPUMF_EVENT_PTR(cf_z14, TX_C_TABORT_SPECIAL), 486 CPUMF_EVENT_PTR(cf_z14, MT_DIAG_CYCLES_ONE_THR_ACTIVE), 487 CPUMF_EVENT_PTR(cf_z14, MT_DIAG_CYCLES_TWO_THR_ACTIVE), 488 NULL, 489 }; 490 491 /* END: CPUM_CF COUNTER DEFINITIONS ===================================== */ 492 493 static struct attribute_group cpumcf_pmu_events_group = { 494 .name = "events", 495 }; 496 497 PMU_FORMAT_ATTR(event, "config:0-63"); 498 499 static struct attribute *cpumcf_pmu_format_attr[] = { 500 &format_attr_event.attr, 501 NULL, 502 }; 503 504 static struct attribute_group cpumcf_pmu_format_group = { 505 .name = "format", 506 .attrs = cpumcf_pmu_format_attr, 507 }; 508 509 static const struct attribute_group *cpumcf_pmu_attr_groups[] = { 510 &cpumcf_pmu_events_group, 511 &cpumcf_pmu_format_group, 512 NULL, 513 }; 514 515 516 static __init struct attribute **merge_attr(struct attribute **a, 517 struct attribute **b, 518 struct attribute **c) 519 { 520 struct attribute **new; 521 int j, i; 522 523 for (j = 0; a[j]; j++) 524 ; 525 for (i = 0; b[i]; i++) 526 j++; 527 for (i = 0; c[i]; i++) 528 j++; 529 j++; 530 531 new = kmalloc_array(j, sizeof(struct attribute *), GFP_KERNEL); 532 if (!new) 533 return NULL; 534 j = 0; 535 for (i = 0; a[i]; i++) 536 new[j++] = a[i]; 537 for (i = 0; b[i]; i++) 538 new[j++] = b[i]; 539 for (i = 0; c[i]; i++) 540 new[j++] = c[i]; 541 new[j] = NULL; 542 543 return new; 544 } 545 546 __init const struct attribute_group **cpumf_cf_event_group(void) 547 { 548 struct attribute **combined, **model, **cfvn, **csvn; 549 struct attribute *none[] = { NULL }; 550 struct cpumf_ctr_info ci; 551 struct cpuid cpu_id; 552 553 /* Determine generic counters set(s) */ 554 qctri(&ci); 555 switch (ci.cfvn) { 556 case 1: 557 cfvn = cpumcf_fvn1_pmu_event_attr; 558 break; 559 case 3: 560 cfvn = cpumcf_fvn3_pmu_event_attr; 561 break; 562 default: 563 cfvn = none; 564 } 565 csvn = cpumcf_svn_generic_pmu_event_attr; 566 567 /* Determine model-specific counter set(s) */ 568 get_cpu_id(&cpu_id); 569 switch (cpu_id.machine) { 570 case 0x2097: 571 case 0x2098: 572 model = cpumcf_z10_pmu_event_attr; 573 break; 574 case 0x2817: 575 case 0x2818: 576 model = cpumcf_z196_pmu_event_attr; 577 break; 578 case 0x2827: 579 case 0x2828: 580 model = cpumcf_zec12_pmu_event_attr; 581 break; 582 case 0x2964: 583 case 0x2965: 584 model = cpumcf_z13_pmu_event_attr; 585 break; 586 case 0x3906: 587 case 0x3907: 588 model = cpumcf_z14_pmu_event_attr; 589 break; 590 default: 591 model = none; 592 break; 593 } 594 595 combined = merge_attr(cfvn, csvn, model); 596 if (combined) 597 cpumcf_pmu_events_group.attrs = combined; 598 return cpumcf_pmu_attr_groups; 599 } 600