1 /* 2 * Perf PMU sysfs events attributes for available CPU-measurement counters 3 * 4 */ 5 6 #include <linux/slab.h> 7 #include <linux/perf_event.h> 8 9 10 /* BEGIN: CPUM_CF COUNTER DEFINITIONS =================================== */ 11 12 CPUMF_EVENT_ATTR(cf, CPU_CYCLES, 0x0000); 13 CPUMF_EVENT_ATTR(cf, INSTRUCTIONS, 0x0001); 14 CPUMF_EVENT_ATTR(cf, L1I_DIR_WRITES, 0x0002); 15 CPUMF_EVENT_ATTR(cf, L1I_PENALTY_CYCLES, 0x0003); 16 CPUMF_EVENT_ATTR(cf, PROBLEM_STATE_CPU_CYCLES, 0x0020); 17 CPUMF_EVENT_ATTR(cf, PROBLEM_STATE_INSTRUCTIONS, 0x0021); 18 CPUMF_EVENT_ATTR(cf, PROBLEM_STATE_L1I_DIR_WRITES, 0x0022); 19 CPUMF_EVENT_ATTR(cf, PROBLEM_STATE_L1I_PENALTY_CYCLES, 0x0023); 20 CPUMF_EVENT_ATTR(cf, PROBLEM_STATE_L1D_DIR_WRITES, 0x0024); 21 CPUMF_EVENT_ATTR(cf, PROBLEM_STATE_L1D_PENALTY_CYCLES, 0x0025); 22 CPUMF_EVENT_ATTR(cf, L1D_DIR_WRITES, 0x0004); 23 CPUMF_EVENT_ATTR(cf, L1D_PENALTY_CYCLES, 0x0005); 24 CPUMF_EVENT_ATTR(cf, PRNG_FUNCTIONS, 0x0040); 25 CPUMF_EVENT_ATTR(cf, PRNG_CYCLES, 0x0041); 26 CPUMF_EVENT_ATTR(cf, PRNG_BLOCKED_FUNCTIONS, 0x0042); 27 CPUMF_EVENT_ATTR(cf, PRNG_BLOCKED_CYCLES, 0x0043); 28 CPUMF_EVENT_ATTR(cf, SHA_FUNCTIONS, 0x0044); 29 CPUMF_EVENT_ATTR(cf, SHA_CYCLES, 0x0045); 30 CPUMF_EVENT_ATTR(cf, SHA_BLOCKED_FUNCTIONS, 0x0046); 31 CPUMF_EVENT_ATTR(cf, SHA_BLOCKED_CYCLES, 0x0047); 32 CPUMF_EVENT_ATTR(cf, DEA_FUNCTIONS, 0x0048); 33 CPUMF_EVENT_ATTR(cf, DEA_CYCLES, 0x0049); 34 CPUMF_EVENT_ATTR(cf, DEA_BLOCKED_FUNCTIONS, 0x004a); 35 CPUMF_EVENT_ATTR(cf, DEA_BLOCKED_CYCLES, 0x004b); 36 CPUMF_EVENT_ATTR(cf, AES_FUNCTIONS, 0x004c); 37 CPUMF_EVENT_ATTR(cf, AES_CYCLES, 0x004d); 38 CPUMF_EVENT_ATTR(cf, AES_BLOCKED_FUNCTIONS, 0x004e); 39 CPUMF_EVENT_ATTR(cf, AES_BLOCKED_CYCLES, 0x004f); 40 CPUMF_EVENT_ATTR(cf_z10, L1I_L2_SOURCED_WRITES, 0x0080); 41 CPUMF_EVENT_ATTR(cf_z10, L1D_L2_SOURCED_WRITES, 0x0081); 42 CPUMF_EVENT_ATTR(cf_z10, L1I_L3_LOCAL_WRITES, 0x0082); 43 CPUMF_EVENT_ATTR(cf_z10, L1D_L3_LOCAL_WRITES, 0x0083); 44 CPUMF_EVENT_ATTR(cf_z10, L1I_L3_REMOTE_WRITES, 0x0084); 45 CPUMF_EVENT_ATTR(cf_z10, L1D_L3_REMOTE_WRITES, 0x0085); 46 CPUMF_EVENT_ATTR(cf_z10, L1D_LMEM_SOURCED_WRITES, 0x0086); 47 CPUMF_EVENT_ATTR(cf_z10, L1I_LMEM_SOURCED_WRITES, 0x0087); 48 CPUMF_EVENT_ATTR(cf_z10, L1D_RO_EXCL_WRITES, 0x0088); 49 CPUMF_EVENT_ATTR(cf_z10, L1I_CACHELINE_INVALIDATES, 0x0089); 50 CPUMF_EVENT_ATTR(cf_z10, ITLB1_WRITES, 0x008a); 51 CPUMF_EVENT_ATTR(cf_z10, DTLB1_WRITES, 0x008b); 52 CPUMF_EVENT_ATTR(cf_z10, TLB2_PTE_WRITES, 0x008c); 53 CPUMF_EVENT_ATTR(cf_z10, TLB2_CRSTE_WRITES, 0x008d); 54 CPUMF_EVENT_ATTR(cf_z10, TLB2_CRSTE_HPAGE_WRITES, 0x008e); 55 CPUMF_EVENT_ATTR(cf_z10, ITLB1_MISSES, 0x0091); 56 CPUMF_EVENT_ATTR(cf_z10, DTLB1_MISSES, 0x0092); 57 CPUMF_EVENT_ATTR(cf_z10, L2C_STORES_SENT, 0x0093); 58 CPUMF_EVENT_ATTR(cf_z196, L1D_L2_SOURCED_WRITES, 0x0080); 59 CPUMF_EVENT_ATTR(cf_z196, L1I_L2_SOURCED_WRITES, 0x0081); 60 CPUMF_EVENT_ATTR(cf_z196, DTLB1_MISSES, 0x0082); 61 CPUMF_EVENT_ATTR(cf_z196, ITLB1_MISSES, 0x0083); 62 CPUMF_EVENT_ATTR(cf_z196, L2C_STORES_SENT, 0x0085); 63 CPUMF_EVENT_ATTR(cf_z196, L1D_OFFBOOK_L3_SOURCED_WRITES, 0x0086); 64 CPUMF_EVENT_ATTR(cf_z196, L1D_ONBOOK_L4_SOURCED_WRITES, 0x0087); 65 CPUMF_EVENT_ATTR(cf_z196, L1I_ONBOOK_L4_SOURCED_WRITES, 0x0088); 66 CPUMF_EVENT_ATTR(cf_z196, L1D_RO_EXCL_WRITES, 0x0089); 67 CPUMF_EVENT_ATTR(cf_z196, L1D_OFFBOOK_L4_SOURCED_WRITES, 0x008a); 68 CPUMF_EVENT_ATTR(cf_z196, L1I_OFFBOOK_L4_SOURCED_WRITES, 0x008b); 69 CPUMF_EVENT_ATTR(cf_z196, DTLB1_HPAGE_WRITES, 0x008c); 70 CPUMF_EVENT_ATTR(cf_z196, L1D_LMEM_SOURCED_WRITES, 0x008d); 71 CPUMF_EVENT_ATTR(cf_z196, L1I_LMEM_SOURCED_WRITES, 0x008e); 72 CPUMF_EVENT_ATTR(cf_z196, L1I_OFFBOOK_L3_SOURCED_WRITES, 0x008f); 73 CPUMF_EVENT_ATTR(cf_z196, DTLB1_WRITES, 0x0090); 74 CPUMF_EVENT_ATTR(cf_z196, ITLB1_WRITES, 0x0091); 75 CPUMF_EVENT_ATTR(cf_z196, TLB2_PTE_WRITES, 0x0092); 76 CPUMF_EVENT_ATTR(cf_z196, TLB2_CRSTE_HPAGE_WRITES, 0x0093); 77 CPUMF_EVENT_ATTR(cf_z196, TLB2_CRSTE_WRITES, 0x0094); 78 CPUMF_EVENT_ATTR(cf_z196, L1D_ONCHIP_L3_SOURCED_WRITES, 0x0096); 79 CPUMF_EVENT_ATTR(cf_z196, L1D_OFFCHIP_L3_SOURCED_WRITES, 0x0098); 80 CPUMF_EVENT_ATTR(cf_z196, L1I_ONCHIP_L3_SOURCED_WRITES, 0x0099); 81 CPUMF_EVENT_ATTR(cf_z196, L1I_OFFCHIP_L3_SOURCED_WRITES, 0x009b); 82 CPUMF_EVENT_ATTR(cf_zec12, DTLB1_MISSES, 0x0080); 83 CPUMF_EVENT_ATTR(cf_zec12, ITLB1_MISSES, 0x0081); 84 CPUMF_EVENT_ATTR(cf_zec12, L1D_L2I_SOURCED_WRITES, 0x0082); 85 CPUMF_EVENT_ATTR(cf_zec12, L1I_L2I_SOURCED_WRITES, 0x0083); 86 CPUMF_EVENT_ATTR(cf_zec12, L1D_L2D_SOURCED_WRITES, 0x0084); 87 CPUMF_EVENT_ATTR(cf_zec12, DTLB1_WRITES, 0x0085); 88 CPUMF_EVENT_ATTR(cf_zec12, L1D_LMEM_SOURCED_WRITES, 0x0087); 89 CPUMF_EVENT_ATTR(cf_zec12, L1I_LMEM_SOURCED_WRITES, 0x0089); 90 CPUMF_EVENT_ATTR(cf_zec12, L1D_RO_EXCL_WRITES, 0x008a); 91 CPUMF_EVENT_ATTR(cf_zec12, DTLB1_HPAGE_WRITES, 0x008b); 92 CPUMF_EVENT_ATTR(cf_zec12, ITLB1_WRITES, 0x008c); 93 CPUMF_EVENT_ATTR(cf_zec12, TLB2_PTE_WRITES, 0x008d); 94 CPUMF_EVENT_ATTR(cf_zec12, TLB2_CRSTE_HPAGE_WRITES, 0x008e); 95 CPUMF_EVENT_ATTR(cf_zec12, TLB2_CRSTE_WRITES, 0x008f); 96 CPUMF_EVENT_ATTR(cf_zec12, L1D_ONCHIP_L3_SOURCED_WRITES, 0x0090); 97 CPUMF_EVENT_ATTR(cf_zec12, L1D_OFFCHIP_L3_SOURCED_WRITES, 0x0091); 98 CPUMF_EVENT_ATTR(cf_zec12, L1D_OFFBOOK_L3_SOURCED_WRITES, 0x0092); 99 CPUMF_EVENT_ATTR(cf_zec12, L1D_ONBOOK_L4_SOURCED_WRITES, 0x0093); 100 CPUMF_EVENT_ATTR(cf_zec12, L1D_OFFBOOK_L4_SOURCED_WRITES, 0x0094); 101 CPUMF_EVENT_ATTR(cf_zec12, TX_NC_TEND, 0x0095); 102 CPUMF_EVENT_ATTR(cf_zec12, L1D_ONCHIP_L3_SOURCED_WRITES_IV, 0x0096); 103 CPUMF_EVENT_ATTR(cf_zec12, L1D_OFFCHIP_L3_SOURCED_WRITES_IV, 0x0097); 104 CPUMF_EVENT_ATTR(cf_zec12, L1D_OFFBOOK_L3_SOURCED_WRITES_IV, 0x0098); 105 CPUMF_EVENT_ATTR(cf_zec12, L1I_ONCHIP_L3_SOURCED_WRITES, 0x0099); 106 CPUMF_EVENT_ATTR(cf_zec12, L1I_OFFCHIP_L3_SOURCED_WRITES, 0x009a); 107 CPUMF_EVENT_ATTR(cf_zec12, L1I_OFFBOOK_L3_SOURCED_WRITES, 0x009b); 108 CPUMF_EVENT_ATTR(cf_zec12, L1I_ONBOOK_L4_SOURCED_WRITES, 0x009c); 109 CPUMF_EVENT_ATTR(cf_zec12, L1I_OFFBOOK_L4_SOURCED_WRITES, 0x009d); 110 CPUMF_EVENT_ATTR(cf_zec12, TX_C_TEND, 0x009e); 111 CPUMF_EVENT_ATTR(cf_zec12, L1I_ONCHIP_L3_SOURCED_WRITES_IV, 0x009f); 112 CPUMF_EVENT_ATTR(cf_zec12, L1I_OFFCHIP_L3_SOURCED_WRITES_IV, 0x00a0); 113 CPUMF_EVENT_ATTR(cf_zec12, L1I_OFFBOOK_L3_SOURCED_WRITES_IV, 0x00a1); 114 CPUMF_EVENT_ATTR(cf_zec12, TX_NC_TABORT, 0x00b1); 115 CPUMF_EVENT_ATTR(cf_zec12, TX_C_TABORT_NO_SPECIAL, 0x00b2); 116 CPUMF_EVENT_ATTR(cf_zec12, TX_C_TABORT_SPECIAL, 0x00b3); 117 CPUMF_EVENT_ATTR(cf_z13, L1D_WRITES_RO_EXCL, 0x0080); 118 CPUMF_EVENT_ATTR(cf_z13, DTLB1_WRITES, 0x0081); 119 CPUMF_EVENT_ATTR(cf_z13, DTLB1_MISSES, 0x0082); 120 CPUMF_EVENT_ATTR(cf_z13, DTLB1_HPAGE_WRITES, 0x0083); 121 CPUMF_EVENT_ATTR(cf_z13, DTLB1_GPAGE_WRITES, 0x0084); 122 CPUMF_EVENT_ATTR(cf_z13, L1D_L2D_SOURCED_WRITES, 0x0085); 123 CPUMF_EVENT_ATTR(cf_z13, ITLB1_WRITES, 0x0086); 124 CPUMF_EVENT_ATTR(cf_z13, ITLB1_MISSES, 0x0087); 125 CPUMF_EVENT_ATTR(cf_z13, L1I_L2I_SOURCED_WRITES, 0x0088); 126 CPUMF_EVENT_ATTR(cf_z13, TLB2_PTE_WRITES, 0x0089); 127 CPUMF_EVENT_ATTR(cf_z13, TLB2_CRSTE_HPAGE_WRITES, 0x008a); 128 CPUMF_EVENT_ATTR(cf_z13, TLB2_CRSTE_WRITES, 0x008b); 129 CPUMF_EVENT_ATTR(cf_z13, TX_C_TEND, 0x008c); 130 CPUMF_EVENT_ATTR(cf_z13, TX_NC_TEND, 0x008d); 131 CPUMF_EVENT_ATTR(cf_z13, L1C_TLB1_MISSES, 0x008f); 132 CPUMF_EVENT_ATTR(cf_z13, L1D_ONCHIP_L3_SOURCED_WRITES, 0x0090); 133 CPUMF_EVENT_ATTR(cf_z13, L1D_ONCHIP_L3_SOURCED_WRITES_IV, 0x0091); 134 CPUMF_EVENT_ATTR(cf_z13, L1D_ONNODE_L4_SOURCED_WRITES, 0x0092); 135 CPUMF_EVENT_ATTR(cf_z13, L1D_ONNODE_L3_SOURCED_WRITES_IV, 0x0093); 136 CPUMF_EVENT_ATTR(cf_z13, L1D_ONNODE_L3_SOURCED_WRITES, 0x0094); 137 CPUMF_EVENT_ATTR(cf_z13, L1D_ONDRAWER_L4_SOURCED_WRITES, 0x0095); 138 CPUMF_EVENT_ATTR(cf_z13, L1D_ONDRAWER_L3_SOURCED_WRITES_IV, 0x0096); 139 CPUMF_EVENT_ATTR(cf_z13, L1D_ONDRAWER_L3_SOURCED_WRITES, 0x0097); 140 CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_SCOL_L4_SOURCED_WRITES, 0x0098); 141 CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV, 0x0099); 142 CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES, 0x009a); 143 CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_FCOL_L4_SOURCED_WRITES, 0x009b); 144 CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV, 0x009c); 145 CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES, 0x009d); 146 CPUMF_EVENT_ATTR(cf_z13, L1D_ONNODE_MEM_SOURCED_WRITES, 0x009e); 147 CPUMF_EVENT_ATTR(cf_z13, L1D_ONDRAWER_MEM_SOURCED_WRITES, 0x009f); 148 CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_MEM_SOURCED_WRITES, 0x00a0); 149 CPUMF_EVENT_ATTR(cf_z13, L1D_ONCHIP_MEM_SOURCED_WRITES, 0x00a1); 150 CPUMF_EVENT_ATTR(cf_z13, L1I_ONCHIP_L3_SOURCED_WRITES, 0x00a2); 151 CPUMF_EVENT_ATTR(cf_z13, L1I_ONCHIP_L3_SOURCED_WRITES_IV, 0x00a3); 152 CPUMF_EVENT_ATTR(cf_z13, L1I_ONNODE_L4_SOURCED_WRITES, 0x00a4); 153 CPUMF_EVENT_ATTR(cf_z13, L1I_ONNODE_L3_SOURCED_WRITES_IV, 0x00a5); 154 CPUMF_EVENT_ATTR(cf_z13, L1I_ONNODE_L3_SOURCED_WRITES, 0x00a6); 155 CPUMF_EVENT_ATTR(cf_z13, L1I_ONDRAWER_L4_SOURCED_WRITES, 0x00a7); 156 CPUMF_EVENT_ATTR(cf_z13, L1I_ONDRAWER_L3_SOURCED_WRITES_IV, 0x00a8); 157 CPUMF_EVENT_ATTR(cf_z13, L1I_ONDRAWER_L3_SOURCED_WRITES, 0x00a9); 158 CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_SCOL_L4_SOURCED_WRITES, 0x00aa); 159 CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV, 0x00ab); 160 CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES, 0x00ac); 161 CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_FCOL_L4_SOURCED_WRITES, 0x00ad); 162 CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV, 0x00ae); 163 CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES, 0x00af); 164 CPUMF_EVENT_ATTR(cf_z13, L1I_ONNODE_MEM_SOURCED_WRITES, 0x00b0); 165 CPUMF_EVENT_ATTR(cf_z13, L1I_ONDRAWER_MEM_SOURCED_WRITES, 0x00b1); 166 CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_MEM_SOURCED_WRITES, 0x00b2); 167 CPUMF_EVENT_ATTR(cf_z13, L1I_ONCHIP_MEM_SOURCED_WRITES, 0x00b3); 168 CPUMF_EVENT_ATTR(cf_z13, TX_NC_TABORT, 0x00da); 169 CPUMF_EVENT_ATTR(cf_z13, TX_C_TABORT_NO_SPECIAL, 0x00db); 170 CPUMF_EVENT_ATTR(cf_z13, TX_C_TABORT_SPECIAL, 0x00dc); 171 CPUMF_EVENT_ATTR(cf_z13, MT_DIAG_CYCLES_ONE_THR_ACTIVE, 0x01c0); 172 CPUMF_EVENT_ATTR(cf_z13, MT_DIAG_CYCLES_TWO_THR_ACTIVE, 0x01c1); 173 174 static struct attribute *cpumcf_pmu_event_attr[] __initdata = { 175 CPUMF_EVENT_PTR(cf, CPU_CYCLES), 176 CPUMF_EVENT_PTR(cf, INSTRUCTIONS), 177 CPUMF_EVENT_PTR(cf, L1I_DIR_WRITES), 178 CPUMF_EVENT_PTR(cf, L1I_PENALTY_CYCLES), 179 CPUMF_EVENT_PTR(cf, PROBLEM_STATE_CPU_CYCLES), 180 CPUMF_EVENT_PTR(cf, PROBLEM_STATE_INSTRUCTIONS), 181 CPUMF_EVENT_PTR(cf, PROBLEM_STATE_L1I_DIR_WRITES), 182 CPUMF_EVENT_PTR(cf, PROBLEM_STATE_L1I_PENALTY_CYCLES), 183 CPUMF_EVENT_PTR(cf, PROBLEM_STATE_L1D_DIR_WRITES), 184 CPUMF_EVENT_PTR(cf, PROBLEM_STATE_L1D_PENALTY_CYCLES), 185 CPUMF_EVENT_PTR(cf, L1D_DIR_WRITES), 186 CPUMF_EVENT_PTR(cf, L1D_PENALTY_CYCLES), 187 CPUMF_EVENT_PTR(cf, PRNG_FUNCTIONS), 188 CPUMF_EVENT_PTR(cf, PRNG_CYCLES), 189 CPUMF_EVENT_PTR(cf, PRNG_BLOCKED_FUNCTIONS), 190 CPUMF_EVENT_PTR(cf, PRNG_BLOCKED_CYCLES), 191 CPUMF_EVENT_PTR(cf, SHA_FUNCTIONS), 192 CPUMF_EVENT_PTR(cf, SHA_CYCLES), 193 CPUMF_EVENT_PTR(cf, SHA_BLOCKED_FUNCTIONS), 194 CPUMF_EVENT_PTR(cf, SHA_BLOCKED_CYCLES), 195 CPUMF_EVENT_PTR(cf, DEA_FUNCTIONS), 196 CPUMF_EVENT_PTR(cf, DEA_CYCLES), 197 CPUMF_EVENT_PTR(cf, DEA_BLOCKED_FUNCTIONS), 198 CPUMF_EVENT_PTR(cf, DEA_BLOCKED_CYCLES), 199 CPUMF_EVENT_PTR(cf, AES_FUNCTIONS), 200 CPUMF_EVENT_PTR(cf, AES_CYCLES), 201 CPUMF_EVENT_PTR(cf, AES_BLOCKED_FUNCTIONS), 202 CPUMF_EVENT_PTR(cf, AES_BLOCKED_CYCLES), 203 NULL, 204 }; 205 206 static struct attribute *cpumcf_z10_pmu_event_attr[] __initdata = { 207 CPUMF_EVENT_PTR(cf_z10, L1I_L2_SOURCED_WRITES), 208 CPUMF_EVENT_PTR(cf_z10, L1D_L2_SOURCED_WRITES), 209 CPUMF_EVENT_PTR(cf_z10, L1I_L3_LOCAL_WRITES), 210 CPUMF_EVENT_PTR(cf_z10, L1D_L3_LOCAL_WRITES), 211 CPUMF_EVENT_PTR(cf_z10, L1I_L3_REMOTE_WRITES), 212 CPUMF_EVENT_PTR(cf_z10, L1D_L3_REMOTE_WRITES), 213 CPUMF_EVENT_PTR(cf_z10, L1D_LMEM_SOURCED_WRITES), 214 CPUMF_EVENT_PTR(cf_z10, L1I_LMEM_SOURCED_WRITES), 215 CPUMF_EVENT_PTR(cf_z10, L1D_RO_EXCL_WRITES), 216 CPUMF_EVENT_PTR(cf_z10, L1I_CACHELINE_INVALIDATES), 217 CPUMF_EVENT_PTR(cf_z10, ITLB1_WRITES), 218 CPUMF_EVENT_PTR(cf_z10, DTLB1_WRITES), 219 CPUMF_EVENT_PTR(cf_z10, TLB2_PTE_WRITES), 220 CPUMF_EVENT_PTR(cf_z10, TLB2_CRSTE_WRITES), 221 CPUMF_EVENT_PTR(cf_z10, TLB2_CRSTE_HPAGE_WRITES), 222 CPUMF_EVENT_PTR(cf_z10, ITLB1_MISSES), 223 CPUMF_EVENT_PTR(cf_z10, DTLB1_MISSES), 224 CPUMF_EVENT_PTR(cf_z10, L2C_STORES_SENT), 225 NULL, 226 }; 227 228 static struct attribute *cpumcf_z196_pmu_event_attr[] __initdata = { 229 CPUMF_EVENT_PTR(cf_z196, L1D_L2_SOURCED_WRITES), 230 CPUMF_EVENT_PTR(cf_z196, L1I_L2_SOURCED_WRITES), 231 CPUMF_EVENT_PTR(cf_z196, DTLB1_MISSES), 232 CPUMF_EVENT_PTR(cf_z196, ITLB1_MISSES), 233 CPUMF_EVENT_PTR(cf_z196, L2C_STORES_SENT), 234 CPUMF_EVENT_PTR(cf_z196, L1D_OFFBOOK_L3_SOURCED_WRITES), 235 CPUMF_EVENT_PTR(cf_z196, L1D_ONBOOK_L4_SOURCED_WRITES), 236 CPUMF_EVENT_PTR(cf_z196, L1I_ONBOOK_L4_SOURCED_WRITES), 237 CPUMF_EVENT_PTR(cf_z196, L1D_RO_EXCL_WRITES), 238 CPUMF_EVENT_PTR(cf_z196, L1D_OFFBOOK_L4_SOURCED_WRITES), 239 CPUMF_EVENT_PTR(cf_z196, L1I_OFFBOOK_L4_SOURCED_WRITES), 240 CPUMF_EVENT_PTR(cf_z196, DTLB1_HPAGE_WRITES), 241 CPUMF_EVENT_PTR(cf_z196, L1D_LMEM_SOURCED_WRITES), 242 CPUMF_EVENT_PTR(cf_z196, L1I_LMEM_SOURCED_WRITES), 243 CPUMF_EVENT_PTR(cf_z196, L1I_OFFBOOK_L3_SOURCED_WRITES), 244 CPUMF_EVENT_PTR(cf_z196, DTLB1_WRITES), 245 CPUMF_EVENT_PTR(cf_z196, ITLB1_WRITES), 246 CPUMF_EVENT_PTR(cf_z196, TLB2_PTE_WRITES), 247 CPUMF_EVENT_PTR(cf_z196, TLB2_CRSTE_HPAGE_WRITES), 248 CPUMF_EVENT_PTR(cf_z196, TLB2_CRSTE_WRITES), 249 CPUMF_EVENT_PTR(cf_z196, L1D_ONCHIP_L3_SOURCED_WRITES), 250 CPUMF_EVENT_PTR(cf_z196, L1D_OFFCHIP_L3_SOURCED_WRITES), 251 CPUMF_EVENT_PTR(cf_z196, L1I_ONCHIP_L3_SOURCED_WRITES), 252 CPUMF_EVENT_PTR(cf_z196, L1I_OFFCHIP_L3_SOURCED_WRITES), 253 NULL, 254 }; 255 256 static struct attribute *cpumcf_zec12_pmu_event_attr[] __initdata = { 257 CPUMF_EVENT_PTR(cf_zec12, DTLB1_MISSES), 258 CPUMF_EVENT_PTR(cf_zec12, ITLB1_MISSES), 259 CPUMF_EVENT_PTR(cf_zec12, L1D_L2I_SOURCED_WRITES), 260 CPUMF_EVENT_PTR(cf_zec12, L1I_L2I_SOURCED_WRITES), 261 CPUMF_EVENT_PTR(cf_zec12, L1D_L2D_SOURCED_WRITES), 262 CPUMF_EVENT_PTR(cf_zec12, DTLB1_WRITES), 263 CPUMF_EVENT_PTR(cf_zec12, L1D_LMEM_SOURCED_WRITES), 264 CPUMF_EVENT_PTR(cf_zec12, L1I_LMEM_SOURCED_WRITES), 265 CPUMF_EVENT_PTR(cf_zec12, L1D_RO_EXCL_WRITES), 266 CPUMF_EVENT_PTR(cf_zec12, DTLB1_HPAGE_WRITES), 267 CPUMF_EVENT_PTR(cf_zec12, ITLB1_WRITES), 268 CPUMF_EVENT_PTR(cf_zec12, TLB2_PTE_WRITES), 269 CPUMF_EVENT_PTR(cf_zec12, TLB2_CRSTE_HPAGE_WRITES), 270 CPUMF_EVENT_PTR(cf_zec12, TLB2_CRSTE_WRITES), 271 CPUMF_EVENT_PTR(cf_zec12, L1D_ONCHIP_L3_SOURCED_WRITES), 272 CPUMF_EVENT_PTR(cf_zec12, L1D_OFFCHIP_L3_SOURCED_WRITES), 273 CPUMF_EVENT_PTR(cf_zec12, L1D_OFFBOOK_L3_SOURCED_WRITES), 274 CPUMF_EVENT_PTR(cf_zec12, L1D_ONBOOK_L4_SOURCED_WRITES), 275 CPUMF_EVENT_PTR(cf_zec12, L1D_OFFBOOK_L4_SOURCED_WRITES), 276 CPUMF_EVENT_PTR(cf_zec12, TX_NC_TEND), 277 CPUMF_EVENT_PTR(cf_zec12, L1D_ONCHIP_L3_SOURCED_WRITES_IV), 278 CPUMF_EVENT_PTR(cf_zec12, L1D_OFFCHIP_L3_SOURCED_WRITES_IV), 279 CPUMF_EVENT_PTR(cf_zec12, L1D_OFFBOOK_L3_SOURCED_WRITES_IV), 280 CPUMF_EVENT_PTR(cf_zec12, L1I_ONCHIP_L3_SOURCED_WRITES), 281 CPUMF_EVENT_PTR(cf_zec12, L1I_OFFCHIP_L3_SOURCED_WRITES), 282 CPUMF_EVENT_PTR(cf_zec12, L1I_OFFBOOK_L3_SOURCED_WRITES), 283 CPUMF_EVENT_PTR(cf_zec12, L1I_ONBOOK_L4_SOURCED_WRITES), 284 CPUMF_EVENT_PTR(cf_zec12, L1I_OFFBOOK_L4_SOURCED_WRITES), 285 CPUMF_EVENT_PTR(cf_zec12, TX_C_TEND), 286 CPUMF_EVENT_PTR(cf_zec12, L1I_ONCHIP_L3_SOURCED_WRITES_IV), 287 CPUMF_EVENT_PTR(cf_zec12, L1I_OFFCHIP_L3_SOURCED_WRITES_IV), 288 CPUMF_EVENT_PTR(cf_zec12, L1I_OFFBOOK_L3_SOURCED_WRITES_IV), 289 CPUMF_EVENT_PTR(cf_zec12, TX_NC_TABORT), 290 CPUMF_EVENT_PTR(cf_zec12, TX_C_TABORT_NO_SPECIAL), 291 CPUMF_EVENT_PTR(cf_zec12, TX_C_TABORT_SPECIAL), 292 NULL, 293 }; 294 295 static struct attribute *cpumcf_z13_pmu_event_attr[] __initdata = { 296 CPUMF_EVENT_PTR(cf_z13, L1D_WRITES_RO_EXCL), 297 CPUMF_EVENT_PTR(cf_z13, DTLB1_WRITES), 298 CPUMF_EVENT_PTR(cf_z13, DTLB1_MISSES), 299 CPUMF_EVENT_PTR(cf_z13, DTLB1_HPAGE_WRITES), 300 CPUMF_EVENT_PTR(cf_z13, DTLB1_GPAGE_WRITES), 301 CPUMF_EVENT_PTR(cf_z13, L1D_L2D_SOURCED_WRITES), 302 CPUMF_EVENT_PTR(cf_z13, ITLB1_WRITES), 303 CPUMF_EVENT_PTR(cf_z13, ITLB1_MISSES), 304 CPUMF_EVENT_PTR(cf_z13, L1I_L2I_SOURCED_WRITES), 305 CPUMF_EVENT_PTR(cf_z13, TLB2_PTE_WRITES), 306 CPUMF_EVENT_PTR(cf_z13, TLB2_CRSTE_HPAGE_WRITES), 307 CPUMF_EVENT_PTR(cf_z13, TLB2_CRSTE_WRITES), 308 CPUMF_EVENT_PTR(cf_z13, TX_C_TEND), 309 CPUMF_EVENT_PTR(cf_z13, TX_NC_TEND), 310 CPUMF_EVENT_PTR(cf_z13, L1C_TLB1_MISSES), 311 CPUMF_EVENT_PTR(cf_z13, L1D_ONCHIP_L3_SOURCED_WRITES), 312 CPUMF_EVENT_PTR(cf_z13, L1D_ONCHIP_L3_SOURCED_WRITES_IV), 313 CPUMF_EVENT_PTR(cf_z13, L1D_ONNODE_L4_SOURCED_WRITES), 314 CPUMF_EVENT_PTR(cf_z13, L1D_ONNODE_L3_SOURCED_WRITES_IV), 315 CPUMF_EVENT_PTR(cf_z13, L1D_ONNODE_L3_SOURCED_WRITES), 316 CPUMF_EVENT_PTR(cf_z13, L1D_ONDRAWER_L4_SOURCED_WRITES), 317 CPUMF_EVENT_PTR(cf_z13, L1D_ONDRAWER_L3_SOURCED_WRITES_IV), 318 CPUMF_EVENT_PTR(cf_z13, L1D_ONDRAWER_L3_SOURCED_WRITES), 319 CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_SCOL_L4_SOURCED_WRITES), 320 CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV), 321 CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES), 322 CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_FCOL_L4_SOURCED_WRITES), 323 CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV), 324 CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES), 325 CPUMF_EVENT_PTR(cf_z13, L1D_ONNODE_MEM_SOURCED_WRITES), 326 CPUMF_EVENT_PTR(cf_z13, L1D_ONDRAWER_MEM_SOURCED_WRITES), 327 CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_MEM_SOURCED_WRITES), 328 CPUMF_EVENT_PTR(cf_z13, L1D_ONCHIP_MEM_SOURCED_WRITES), 329 CPUMF_EVENT_PTR(cf_z13, L1I_ONCHIP_L3_SOURCED_WRITES), 330 CPUMF_EVENT_PTR(cf_z13, L1I_ONCHIP_L3_SOURCED_WRITES_IV), 331 CPUMF_EVENT_PTR(cf_z13, L1I_ONNODE_L4_SOURCED_WRITES), 332 CPUMF_EVENT_PTR(cf_z13, L1I_ONNODE_L3_SOURCED_WRITES_IV), 333 CPUMF_EVENT_PTR(cf_z13, L1I_ONNODE_L3_SOURCED_WRITES), 334 CPUMF_EVENT_PTR(cf_z13, L1I_ONDRAWER_L4_SOURCED_WRITES), 335 CPUMF_EVENT_PTR(cf_z13, L1I_ONDRAWER_L3_SOURCED_WRITES_IV), 336 CPUMF_EVENT_PTR(cf_z13, L1I_ONDRAWER_L3_SOURCED_WRITES), 337 CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_SCOL_L4_SOURCED_WRITES), 338 CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV), 339 CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES), 340 CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_FCOL_L4_SOURCED_WRITES), 341 CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV), 342 CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES), 343 CPUMF_EVENT_PTR(cf_z13, L1I_ONNODE_MEM_SOURCED_WRITES), 344 CPUMF_EVENT_PTR(cf_z13, L1I_ONDRAWER_MEM_SOURCED_WRITES), 345 CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_MEM_SOURCED_WRITES), 346 CPUMF_EVENT_PTR(cf_z13, L1I_ONCHIP_MEM_SOURCED_WRITES), 347 CPUMF_EVENT_PTR(cf_z13, TX_NC_TABORT), 348 CPUMF_EVENT_PTR(cf_z13, TX_C_TABORT_NO_SPECIAL), 349 CPUMF_EVENT_PTR(cf_z13, TX_C_TABORT_SPECIAL), 350 CPUMF_EVENT_PTR(cf_z13, MT_DIAG_CYCLES_ONE_THR_ACTIVE), 351 CPUMF_EVENT_PTR(cf_z13, MT_DIAG_CYCLES_TWO_THR_ACTIVE), 352 NULL, 353 }; 354 355 /* END: CPUM_CF COUNTER DEFINITIONS ===================================== */ 356 357 static struct attribute_group cpumcf_pmu_events_group = { 358 .name = "events", 359 }; 360 361 PMU_FORMAT_ATTR(event, "config:0-63"); 362 363 static struct attribute *cpumcf_pmu_format_attr[] = { 364 &format_attr_event.attr, 365 NULL, 366 }; 367 368 static struct attribute_group cpumcf_pmu_format_group = { 369 .name = "format", 370 .attrs = cpumcf_pmu_format_attr, 371 }; 372 373 static const struct attribute_group *cpumcf_pmu_attr_groups[] = { 374 &cpumcf_pmu_events_group, 375 &cpumcf_pmu_format_group, 376 NULL, 377 }; 378 379 380 static __init struct attribute **merge_attr(struct attribute **a, 381 struct attribute **b) 382 { 383 struct attribute **new; 384 int j, i; 385 386 for (j = 0; a[j]; j++) 387 ; 388 for (i = 0; b[i]; i++) 389 j++; 390 j++; 391 392 new = kmalloc(sizeof(struct attribute *) * j, GFP_KERNEL); 393 if (!new) 394 return NULL; 395 j = 0; 396 for (i = 0; a[i]; i++) 397 new[j++] = a[i]; 398 for (i = 0; b[i]; i++) 399 new[j++] = b[i]; 400 new[j] = NULL; 401 402 return new; 403 } 404 405 __init const struct attribute_group **cpumf_cf_event_group(void) 406 { 407 struct attribute **combined, **model; 408 struct attribute *none[] = { NULL }; 409 struct cpuid cpu_id; 410 411 get_cpu_id(&cpu_id); 412 switch (cpu_id.machine) { 413 case 0x2097: 414 case 0x2098: 415 model = cpumcf_z10_pmu_event_attr; 416 break; 417 case 0x2817: 418 case 0x2818: 419 model = cpumcf_z196_pmu_event_attr; 420 break; 421 case 0x2827: 422 case 0x2828: 423 model = cpumcf_zec12_pmu_event_attr; 424 break; 425 case 0x2964: 426 case 0x2965: 427 model = cpumcf_z13_pmu_event_attr; 428 break; 429 default: 430 model = none; 431 break; 432 } 433 434 combined = merge_attr(cpumcf_pmu_event_attr, model); 435 if (combined) 436 cpumcf_pmu_events_group.attrs = combined; 437 return cpumcf_pmu_attr_groups; 438 } 439