1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Perf PMU sysfs events attributes for available CPU-measurement counters 4 * 5 */ 6 7 #include <linux/slab.h> 8 #include <linux/perf_event.h> 9 #include <asm/cpu_mf.h> 10 11 12 /* BEGIN: CPUM_CF COUNTER DEFINITIONS =================================== */ 13 14 CPUMF_EVENT_ATTR(cf_fvn1, CPU_CYCLES, 0x0000); 15 CPUMF_EVENT_ATTR(cf_fvn1, INSTRUCTIONS, 0x0001); 16 CPUMF_EVENT_ATTR(cf_fvn1, L1I_DIR_WRITES, 0x0002); 17 CPUMF_EVENT_ATTR(cf_fvn1, L1I_PENALTY_CYCLES, 0x0003); 18 CPUMF_EVENT_ATTR(cf_fvn1, PROBLEM_STATE_CPU_CYCLES, 0x0020); 19 CPUMF_EVENT_ATTR(cf_fvn1, PROBLEM_STATE_INSTRUCTIONS, 0x0021); 20 CPUMF_EVENT_ATTR(cf_fvn1, PROBLEM_STATE_L1I_DIR_WRITES, 0x0022); 21 CPUMF_EVENT_ATTR(cf_fvn1, PROBLEM_STATE_L1I_PENALTY_CYCLES, 0x0023); 22 CPUMF_EVENT_ATTR(cf_fvn1, PROBLEM_STATE_L1D_DIR_WRITES, 0x0024); 23 CPUMF_EVENT_ATTR(cf_fvn1, PROBLEM_STATE_L1D_PENALTY_CYCLES, 0x0025); 24 CPUMF_EVENT_ATTR(cf_fvn1, L1D_DIR_WRITES, 0x0004); 25 CPUMF_EVENT_ATTR(cf_fvn1, L1D_PENALTY_CYCLES, 0x0005); 26 CPUMF_EVENT_ATTR(cf_fvn3, CPU_CYCLES, 0x0000); 27 CPUMF_EVENT_ATTR(cf_fvn3, INSTRUCTIONS, 0x0001); 28 CPUMF_EVENT_ATTR(cf_fvn3, L1I_DIR_WRITES, 0x0002); 29 CPUMF_EVENT_ATTR(cf_fvn3, L1I_PENALTY_CYCLES, 0x0003); 30 CPUMF_EVENT_ATTR(cf_fvn3, PROBLEM_STATE_CPU_CYCLES, 0x0020); 31 CPUMF_EVENT_ATTR(cf_fvn3, PROBLEM_STATE_INSTRUCTIONS, 0x0021); 32 CPUMF_EVENT_ATTR(cf_fvn3, L1D_DIR_WRITES, 0x0004); 33 CPUMF_EVENT_ATTR(cf_fvn3, L1D_PENALTY_CYCLES, 0x0005); 34 CPUMF_EVENT_ATTR(cf_svn_12345, PRNG_FUNCTIONS, 0x0040); 35 CPUMF_EVENT_ATTR(cf_svn_12345, PRNG_CYCLES, 0x0041); 36 CPUMF_EVENT_ATTR(cf_svn_12345, PRNG_BLOCKED_FUNCTIONS, 0x0042); 37 CPUMF_EVENT_ATTR(cf_svn_12345, PRNG_BLOCKED_CYCLES, 0x0043); 38 CPUMF_EVENT_ATTR(cf_svn_12345, SHA_FUNCTIONS, 0x0044); 39 CPUMF_EVENT_ATTR(cf_svn_12345, SHA_CYCLES, 0x0045); 40 CPUMF_EVENT_ATTR(cf_svn_12345, SHA_BLOCKED_FUNCTIONS, 0x0046); 41 CPUMF_EVENT_ATTR(cf_svn_12345, SHA_BLOCKED_CYCLES, 0x0047); 42 CPUMF_EVENT_ATTR(cf_svn_12345, DEA_FUNCTIONS, 0x0048); 43 CPUMF_EVENT_ATTR(cf_svn_12345, DEA_CYCLES, 0x0049); 44 CPUMF_EVENT_ATTR(cf_svn_12345, DEA_BLOCKED_FUNCTIONS, 0x004a); 45 CPUMF_EVENT_ATTR(cf_svn_12345, DEA_BLOCKED_CYCLES, 0x004b); 46 CPUMF_EVENT_ATTR(cf_svn_12345, AES_FUNCTIONS, 0x004c); 47 CPUMF_EVENT_ATTR(cf_svn_12345, AES_CYCLES, 0x004d); 48 CPUMF_EVENT_ATTR(cf_svn_12345, AES_BLOCKED_FUNCTIONS, 0x004e); 49 CPUMF_EVENT_ATTR(cf_svn_12345, AES_BLOCKED_CYCLES, 0x004f); 50 CPUMF_EVENT_ATTR(cf_svn_6, ECC_FUNCTION_COUNT, 0x0050); 51 CPUMF_EVENT_ATTR(cf_svn_6, ECC_CYCLES_COUNT, 0x0051); 52 CPUMF_EVENT_ATTR(cf_svn_6, ECC_BLOCKED_FUNCTION_COUNT, 0x0052); 53 CPUMF_EVENT_ATTR(cf_svn_6, ECC_BLOCKED_CYCLES_COUNT, 0x0053); 54 CPUMF_EVENT_ATTR(cf_z10, L1I_L2_SOURCED_WRITES, 0x0080); 55 CPUMF_EVENT_ATTR(cf_z10, L1D_L2_SOURCED_WRITES, 0x0081); 56 CPUMF_EVENT_ATTR(cf_z10, L1I_L3_LOCAL_WRITES, 0x0082); 57 CPUMF_EVENT_ATTR(cf_z10, L1D_L3_LOCAL_WRITES, 0x0083); 58 CPUMF_EVENT_ATTR(cf_z10, L1I_L3_REMOTE_WRITES, 0x0084); 59 CPUMF_EVENT_ATTR(cf_z10, L1D_L3_REMOTE_WRITES, 0x0085); 60 CPUMF_EVENT_ATTR(cf_z10, L1D_LMEM_SOURCED_WRITES, 0x0086); 61 CPUMF_EVENT_ATTR(cf_z10, L1I_LMEM_SOURCED_WRITES, 0x0087); 62 CPUMF_EVENT_ATTR(cf_z10, L1D_RO_EXCL_WRITES, 0x0088); 63 CPUMF_EVENT_ATTR(cf_z10, L1I_CACHELINE_INVALIDATES, 0x0089); 64 CPUMF_EVENT_ATTR(cf_z10, ITLB1_WRITES, 0x008a); 65 CPUMF_EVENT_ATTR(cf_z10, DTLB1_WRITES, 0x008b); 66 CPUMF_EVENT_ATTR(cf_z10, TLB2_PTE_WRITES, 0x008c); 67 CPUMF_EVENT_ATTR(cf_z10, TLB2_CRSTE_WRITES, 0x008d); 68 CPUMF_EVENT_ATTR(cf_z10, TLB2_CRSTE_HPAGE_WRITES, 0x008e); 69 CPUMF_EVENT_ATTR(cf_z10, ITLB1_MISSES, 0x0091); 70 CPUMF_EVENT_ATTR(cf_z10, DTLB1_MISSES, 0x0092); 71 CPUMF_EVENT_ATTR(cf_z10, L2C_STORES_SENT, 0x0093); 72 CPUMF_EVENT_ATTR(cf_z196, L1D_L2_SOURCED_WRITES, 0x0080); 73 CPUMF_EVENT_ATTR(cf_z196, L1I_L2_SOURCED_WRITES, 0x0081); 74 CPUMF_EVENT_ATTR(cf_z196, DTLB1_MISSES, 0x0082); 75 CPUMF_EVENT_ATTR(cf_z196, ITLB1_MISSES, 0x0083); 76 CPUMF_EVENT_ATTR(cf_z196, L2C_STORES_SENT, 0x0085); 77 CPUMF_EVENT_ATTR(cf_z196, L1D_OFFBOOK_L3_SOURCED_WRITES, 0x0086); 78 CPUMF_EVENT_ATTR(cf_z196, L1D_ONBOOK_L4_SOURCED_WRITES, 0x0087); 79 CPUMF_EVENT_ATTR(cf_z196, L1I_ONBOOK_L4_SOURCED_WRITES, 0x0088); 80 CPUMF_EVENT_ATTR(cf_z196, L1D_RO_EXCL_WRITES, 0x0089); 81 CPUMF_EVENT_ATTR(cf_z196, L1D_OFFBOOK_L4_SOURCED_WRITES, 0x008a); 82 CPUMF_EVENT_ATTR(cf_z196, L1I_OFFBOOK_L4_SOURCED_WRITES, 0x008b); 83 CPUMF_EVENT_ATTR(cf_z196, DTLB1_HPAGE_WRITES, 0x008c); 84 CPUMF_EVENT_ATTR(cf_z196, L1D_LMEM_SOURCED_WRITES, 0x008d); 85 CPUMF_EVENT_ATTR(cf_z196, L1I_LMEM_SOURCED_WRITES, 0x008e); 86 CPUMF_EVENT_ATTR(cf_z196, L1I_OFFBOOK_L3_SOURCED_WRITES, 0x008f); 87 CPUMF_EVENT_ATTR(cf_z196, DTLB1_WRITES, 0x0090); 88 CPUMF_EVENT_ATTR(cf_z196, ITLB1_WRITES, 0x0091); 89 CPUMF_EVENT_ATTR(cf_z196, TLB2_PTE_WRITES, 0x0092); 90 CPUMF_EVENT_ATTR(cf_z196, TLB2_CRSTE_HPAGE_WRITES, 0x0093); 91 CPUMF_EVENT_ATTR(cf_z196, TLB2_CRSTE_WRITES, 0x0094); 92 CPUMF_EVENT_ATTR(cf_z196, L1D_ONCHIP_L3_SOURCED_WRITES, 0x0096); 93 CPUMF_EVENT_ATTR(cf_z196, L1D_OFFCHIP_L3_SOURCED_WRITES, 0x0098); 94 CPUMF_EVENT_ATTR(cf_z196, L1I_ONCHIP_L3_SOURCED_WRITES, 0x0099); 95 CPUMF_EVENT_ATTR(cf_z196, L1I_OFFCHIP_L3_SOURCED_WRITES, 0x009b); 96 CPUMF_EVENT_ATTR(cf_zec12, DTLB1_MISSES, 0x0080); 97 CPUMF_EVENT_ATTR(cf_zec12, ITLB1_MISSES, 0x0081); 98 CPUMF_EVENT_ATTR(cf_zec12, L1D_L2I_SOURCED_WRITES, 0x0082); 99 CPUMF_EVENT_ATTR(cf_zec12, L1I_L2I_SOURCED_WRITES, 0x0083); 100 CPUMF_EVENT_ATTR(cf_zec12, L1D_L2D_SOURCED_WRITES, 0x0084); 101 CPUMF_EVENT_ATTR(cf_zec12, DTLB1_WRITES, 0x0085); 102 CPUMF_EVENT_ATTR(cf_zec12, L1D_LMEM_SOURCED_WRITES, 0x0087); 103 CPUMF_EVENT_ATTR(cf_zec12, L1I_LMEM_SOURCED_WRITES, 0x0089); 104 CPUMF_EVENT_ATTR(cf_zec12, L1D_RO_EXCL_WRITES, 0x008a); 105 CPUMF_EVENT_ATTR(cf_zec12, DTLB1_HPAGE_WRITES, 0x008b); 106 CPUMF_EVENT_ATTR(cf_zec12, ITLB1_WRITES, 0x008c); 107 CPUMF_EVENT_ATTR(cf_zec12, TLB2_PTE_WRITES, 0x008d); 108 CPUMF_EVENT_ATTR(cf_zec12, TLB2_CRSTE_HPAGE_WRITES, 0x008e); 109 CPUMF_EVENT_ATTR(cf_zec12, TLB2_CRSTE_WRITES, 0x008f); 110 CPUMF_EVENT_ATTR(cf_zec12, L1D_ONCHIP_L3_SOURCED_WRITES, 0x0090); 111 CPUMF_EVENT_ATTR(cf_zec12, L1D_OFFCHIP_L3_SOURCED_WRITES, 0x0091); 112 CPUMF_EVENT_ATTR(cf_zec12, L1D_OFFBOOK_L3_SOURCED_WRITES, 0x0092); 113 CPUMF_EVENT_ATTR(cf_zec12, L1D_ONBOOK_L4_SOURCED_WRITES, 0x0093); 114 CPUMF_EVENT_ATTR(cf_zec12, L1D_OFFBOOK_L4_SOURCED_WRITES, 0x0094); 115 CPUMF_EVENT_ATTR(cf_zec12, TX_NC_TEND, 0x0095); 116 CPUMF_EVENT_ATTR(cf_zec12, L1D_ONCHIP_L3_SOURCED_WRITES_IV, 0x0096); 117 CPUMF_EVENT_ATTR(cf_zec12, L1D_OFFCHIP_L3_SOURCED_WRITES_IV, 0x0097); 118 CPUMF_EVENT_ATTR(cf_zec12, L1D_OFFBOOK_L3_SOURCED_WRITES_IV, 0x0098); 119 CPUMF_EVENT_ATTR(cf_zec12, L1I_ONCHIP_L3_SOURCED_WRITES, 0x0099); 120 CPUMF_EVENT_ATTR(cf_zec12, L1I_OFFCHIP_L3_SOURCED_WRITES, 0x009a); 121 CPUMF_EVENT_ATTR(cf_zec12, L1I_OFFBOOK_L3_SOURCED_WRITES, 0x009b); 122 CPUMF_EVENT_ATTR(cf_zec12, L1I_ONBOOK_L4_SOURCED_WRITES, 0x009c); 123 CPUMF_EVENT_ATTR(cf_zec12, L1I_OFFBOOK_L4_SOURCED_WRITES, 0x009d); 124 CPUMF_EVENT_ATTR(cf_zec12, TX_C_TEND, 0x009e); 125 CPUMF_EVENT_ATTR(cf_zec12, L1I_ONCHIP_L3_SOURCED_WRITES_IV, 0x009f); 126 CPUMF_EVENT_ATTR(cf_zec12, L1I_OFFCHIP_L3_SOURCED_WRITES_IV, 0x00a0); 127 CPUMF_EVENT_ATTR(cf_zec12, L1I_OFFBOOK_L3_SOURCED_WRITES_IV, 0x00a1); 128 CPUMF_EVENT_ATTR(cf_zec12, TX_NC_TABORT, 0x00b1); 129 CPUMF_EVENT_ATTR(cf_zec12, TX_C_TABORT_NO_SPECIAL, 0x00b2); 130 CPUMF_EVENT_ATTR(cf_zec12, TX_C_TABORT_SPECIAL, 0x00b3); 131 CPUMF_EVENT_ATTR(cf_z13, L1D_RO_EXCL_WRITES, 0x0080); 132 CPUMF_EVENT_ATTR(cf_z13, DTLB1_WRITES, 0x0081); 133 CPUMF_EVENT_ATTR(cf_z13, DTLB1_MISSES, 0x0082); 134 CPUMF_EVENT_ATTR(cf_z13, DTLB1_HPAGE_WRITES, 0x0083); 135 CPUMF_EVENT_ATTR(cf_z13, DTLB1_GPAGE_WRITES, 0x0084); 136 CPUMF_EVENT_ATTR(cf_z13, L1D_L2D_SOURCED_WRITES, 0x0085); 137 CPUMF_EVENT_ATTR(cf_z13, ITLB1_WRITES, 0x0086); 138 CPUMF_EVENT_ATTR(cf_z13, ITLB1_MISSES, 0x0087); 139 CPUMF_EVENT_ATTR(cf_z13, L1I_L2I_SOURCED_WRITES, 0x0088); 140 CPUMF_EVENT_ATTR(cf_z13, TLB2_PTE_WRITES, 0x0089); 141 CPUMF_EVENT_ATTR(cf_z13, TLB2_CRSTE_HPAGE_WRITES, 0x008a); 142 CPUMF_EVENT_ATTR(cf_z13, TLB2_CRSTE_WRITES, 0x008b); 143 CPUMF_EVENT_ATTR(cf_z13, TX_C_TEND, 0x008c); 144 CPUMF_EVENT_ATTR(cf_z13, TX_NC_TEND, 0x008d); 145 CPUMF_EVENT_ATTR(cf_z13, L1C_TLB1_MISSES, 0x008f); 146 CPUMF_EVENT_ATTR(cf_z13, L1D_ONCHIP_L3_SOURCED_WRITES, 0x0090); 147 CPUMF_EVENT_ATTR(cf_z13, L1D_ONCHIP_L3_SOURCED_WRITES_IV, 0x0091); 148 CPUMF_EVENT_ATTR(cf_z13, L1D_ONNODE_L4_SOURCED_WRITES, 0x0092); 149 CPUMF_EVENT_ATTR(cf_z13, L1D_ONNODE_L3_SOURCED_WRITES_IV, 0x0093); 150 CPUMF_EVENT_ATTR(cf_z13, L1D_ONNODE_L3_SOURCED_WRITES, 0x0094); 151 CPUMF_EVENT_ATTR(cf_z13, L1D_ONDRAWER_L4_SOURCED_WRITES, 0x0095); 152 CPUMF_EVENT_ATTR(cf_z13, L1D_ONDRAWER_L3_SOURCED_WRITES_IV, 0x0096); 153 CPUMF_EVENT_ATTR(cf_z13, L1D_ONDRAWER_L3_SOURCED_WRITES, 0x0097); 154 CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_SCOL_L4_SOURCED_WRITES, 0x0098); 155 CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV, 0x0099); 156 CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES, 0x009a); 157 CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_FCOL_L4_SOURCED_WRITES, 0x009b); 158 CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV, 0x009c); 159 CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES, 0x009d); 160 CPUMF_EVENT_ATTR(cf_z13, L1D_ONNODE_MEM_SOURCED_WRITES, 0x009e); 161 CPUMF_EVENT_ATTR(cf_z13, L1D_ONDRAWER_MEM_SOURCED_WRITES, 0x009f); 162 CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_MEM_SOURCED_WRITES, 0x00a0); 163 CPUMF_EVENT_ATTR(cf_z13, L1D_ONCHIP_MEM_SOURCED_WRITES, 0x00a1); 164 CPUMF_EVENT_ATTR(cf_z13, L1I_ONCHIP_L3_SOURCED_WRITES, 0x00a2); 165 CPUMF_EVENT_ATTR(cf_z13, L1I_ONCHIP_L3_SOURCED_WRITES_IV, 0x00a3); 166 CPUMF_EVENT_ATTR(cf_z13, L1I_ONNODE_L4_SOURCED_WRITES, 0x00a4); 167 CPUMF_EVENT_ATTR(cf_z13, L1I_ONNODE_L3_SOURCED_WRITES_IV, 0x00a5); 168 CPUMF_EVENT_ATTR(cf_z13, L1I_ONNODE_L3_SOURCED_WRITES, 0x00a6); 169 CPUMF_EVENT_ATTR(cf_z13, L1I_ONDRAWER_L4_SOURCED_WRITES, 0x00a7); 170 CPUMF_EVENT_ATTR(cf_z13, L1I_ONDRAWER_L3_SOURCED_WRITES_IV, 0x00a8); 171 CPUMF_EVENT_ATTR(cf_z13, L1I_ONDRAWER_L3_SOURCED_WRITES, 0x00a9); 172 CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_SCOL_L4_SOURCED_WRITES, 0x00aa); 173 CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV, 0x00ab); 174 CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES, 0x00ac); 175 CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_FCOL_L4_SOURCED_WRITES, 0x00ad); 176 CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV, 0x00ae); 177 CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES, 0x00af); 178 CPUMF_EVENT_ATTR(cf_z13, L1I_ONNODE_MEM_SOURCED_WRITES, 0x00b0); 179 CPUMF_EVENT_ATTR(cf_z13, L1I_ONDRAWER_MEM_SOURCED_WRITES, 0x00b1); 180 CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_MEM_SOURCED_WRITES, 0x00b2); 181 CPUMF_EVENT_ATTR(cf_z13, L1I_ONCHIP_MEM_SOURCED_WRITES, 0x00b3); 182 CPUMF_EVENT_ATTR(cf_z13, TX_NC_TABORT, 0x00da); 183 CPUMF_EVENT_ATTR(cf_z13, TX_C_TABORT_NO_SPECIAL, 0x00db); 184 CPUMF_EVENT_ATTR(cf_z13, TX_C_TABORT_SPECIAL, 0x00dc); 185 CPUMF_EVENT_ATTR(cf_z13, MT_DIAG_CYCLES_ONE_THR_ACTIVE, 0x01c0); 186 CPUMF_EVENT_ATTR(cf_z13, MT_DIAG_CYCLES_TWO_THR_ACTIVE, 0x01c1); 187 CPUMF_EVENT_ATTR(cf_z14, L1D_RO_EXCL_WRITES, 0x0080); 188 CPUMF_EVENT_ATTR(cf_z14, DTLB2_WRITES, 0x0081); 189 CPUMF_EVENT_ATTR(cf_z14, DTLB2_MISSES, 0x0082); 190 CPUMF_EVENT_ATTR(cf_z14, DTLB2_HPAGE_WRITES, 0x0083); 191 CPUMF_EVENT_ATTR(cf_z14, DTLB2_GPAGE_WRITES, 0x0084); 192 CPUMF_EVENT_ATTR(cf_z14, L1D_L2D_SOURCED_WRITES, 0x0085); 193 CPUMF_EVENT_ATTR(cf_z14, ITLB2_WRITES, 0x0086); 194 CPUMF_EVENT_ATTR(cf_z14, ITLB2_MISSES, 0x0087); 195 CPUMF_EVENT_ATTR(cf_z14, L1I_L2I_SOURCED_WRITES, 0x0088); 196 CPUMF_EVENT_ATTR(cf_z14, TLB2_PTE_WRITES, 0x0089); 197 CPUMF_EVENT_ATTR(cf_z14, TLB2_CRSTE_WRITES, 0x008a); 198 CPUMF_EVENT_ATTR(cf_z14, TLB2_ENGINES_BUSY, 0x008b); 199 CPUMF_EVENT_ATTR(cf_z14, TX_C_TEND, 0x008c); 200 CPUMF_EVENT_ATTR(cf_z14, TX_NC_TEND, 0x008d); 201 CPUMF_EVENT_ATTR(cf_z14, L1C_TLB2_MISSES, 0x008f); 202 CPUMF_EVENT_ATTR(cf_z14, L1D_ONCHIP_L3_SOURCED_WRITES, 0x0090); 203 CPUMF_EVENT_ATTR(cf_z14, L1D_ONCHIP_MEMORY_SOURCED_WRITES, 0x0091); 204 CPUMF_EVENT_ATTR(cf_z14, L1D_ONCHIP_L3_SOURCED_WRITES_IV, 0x0092); 205 CPUMF_EVENT_ATTR(cf_z14, L1D_ONCLUSTER_L3_SOURCED_WRITES, 0x0093); 206 CPUMF_EVENT_ATTR(cf_z14, L1D_ONCLUSTER_MEMORY_SOURCED_WRITES, 0x0094); 207 CPUMF_EVENT_ATTR(cf_z14, L1D_ONCLUSTER_L3_SOURCED_WRITES_IV, 0x0095); 208 CPUMF_EVENT_ATTR(cf_z14, L1D_OFFCLUSTER_L3_SOURCED_WRITES, 0x0096); 209 CPUMF_EVENT_ATTR(cf_z14, L1D_OFFCLUSTER_MEMORY_SOURCED_WRITES, 0x0097); 210 CPUMF_EVENT_ATTR(cf_z14, L1D_OFFCLUSTER_L3_SOURCED_WRITES_IV, 0x0098); 211 CPUMF_EVENT_ATTR(cf_z14, L1D_OFFDRAWER_L3_SOURCED_WRITES, 0x0099); 212 CPUMF_EVENT_ATTR(cf_z14, L1D_OFFDRAWER_MEMORY_SOURCED_WRITES, 0x009a); 213 CPUMF_EVENT_ATTR(cf_z14, L1D_OFFDRAWER_L3_SOURCED_WRITES_IV, 0x009b); 214 CPUMF_EVENT_ATTR(cf_z14, L1D_ONDRAWER_L4_SOURCED_WRITES, 0x009c); 215 CPUMF_EVENT_ATTR(cf_z14, L1D_OFFDRAWER_L4_SOURCED_WRITES, 0x009d); 216 CPUMF_EVENT_ATTR(cf_z14, L1D_ONCHIP_L3_SOURCED_WRITES_RO, 0x009e); 217 CPUMF_EVENT_ATTR(cf_z14, L1I_ONCHIP_L3_SOURCED_WRITES, 0x00a2); 218 CPUMF_EVENT_ATTR(cf_z14, L1I_ONCHIP_MEMORY_SOURCED_WRITES, 0x00a3); 219 CPUMF_EVENT_ATTR(cf_z14, L1I_ONCHIP_L3_SOURCED_WRITES_IV, 0x00a4); 220 CPUMF_EVENT_ATTR(cf_z14, L1I_ONCLUSTER_L3_SOURCED_WRITES, 0x00a5); 221 CPUMF_EVENT_ATTR(cf_z14, L1I_ONCLUSTER_MEMORY_SOURCED_WRITES, 0x00a6); 222 CPUMF_EVENT_ATTR(cf_z14, L1I_ONCLUSTER_L3_SOURCED_WRITES_IV, 0x00a7); 223 CPUMF_EVENT_ATTR(cf_z14, L1I_OFFCLUSTER_L3_SOURCED_WRITES, 0x00a8); 224 CPUMF_EVENT_ATTR(cf_z14, L1I_OFFCLUSTER_MEMORY_SOURCED_WRITES, 0x00a9); 225 CPUMF_EVENT_ATTR(cf_z14, L1I_OFFCLUSTER_L3_SOURCED_WRITES_IV, 0x00aa); 226 CPUMF_EVENT_ATTR(cf_z14, L1I_OFFDRAWER_L3_SOURCED_WRITES, 0x00ab); 227 CPUMF_EVENT_ATTR(cf_z14, L1I_OFFDRAWER_MEMORY_SOURCED_WRITES, 0x00ac); 228 CPUMF_EVENT_ATTR(cf_z14, L1I_OFFDRAWER_L3_SOURCED_WRITES_IV, 0x00ad); 229 CPUMF_EVENT_ATTR(cf_z14, L1I_ONDRAWER_L4_SOURCED_WRITES, 0x00ae); 230 CPUMF_EVENT_ATTR(cf_z14, L1I_OFFDRAWER_L4_SOURCED_WRITES, 0x00af); 231 CPUMF_EVENT_ATTR(cf_z14, BCD_DFP_EXECUTION_SLOTS, 0x00e0); 232 CPUMF_EVENT_ATTR(cf_z14, VX_BCD_EXECUTION_SLOTS, 0x00e1); 233 CPUMF_EVENT_ATTR(cf_z14, DECIMAL_INSTRUCTIONS, 0x00e2); 234 CPUMF_EVENT_ATTR(cf_z14, LAST_HOST_TRANSLATIONS, 0x00e8); 235 CPUMF_EVENT_ATTR(cf_z14, TX_NC_TABORT, 0x00f3); 236 CPUMF_EVENT_ATTR(cf_z14, TX_C_TABORT_NO_SPECIAL, 0x00f4); 237 CPUMF_EVENT_ATTR(cf_z14, TX_C_TABORT_SPECIAL, 0x00f5); 238 CPUMF_EVENT_ATTR(cf_z14, MT_DIAG_CYCLES_ONE_THR_ACTIVE, 0x01c0); 239 CPUMF_EVENT_ATTR(cf_z14, MT_DIAG_CYCLES_TWO_THR_ACTIVE, 0x01c1); 240 241 CPUMF_EVENT_ATTR(cf_z15, L1D_RO_EXCL_WRITES, 0x0080); 242 CPUMF_EVENT_ATTR(cf_z15, DTLB2_WRITES, 0x0081); 243 CPUMF_EVENT_ATTR(cf_z15, DTLB2_MISSES, 0x0082); 244 CPUMF_EVENT_ATTR(cf_z15, DTLB2_HPAGE_WRITES, 0x0083); 245 CPUMF_EVENT_ATTR(cf_z15, DTLB2_GPAGE_WRITES, 0x0084); 246 CPUMF_EVENT_ATTR(cf_z15, L1D_L2D_SOURCED_WRITES, 0x0085); 247 CPUMF_EVENT_ATTR(cf_z15, ITLB2_WRITES, 0x0086); 248 CPUMF_EVENT_ATTR(cf_z15, ITLB2_MISSES, 0x0087); 249 CPUMF_EVENT_ATTR(cf_z15, L1I_L2I_SOURCED_WRITES, 0x0088); 250 CPUMF_EVENT_ATTR(cf_z15, TLB2_PTE_WRITES, 0x0089); 251 CPUMF_EVENT_ATTR(cf_z15, TLB2_CRSTE_WRITES, 0x008a); 252 CPUMF_EVENT_ATTR(cf_z15, TLB2_ENGINES_BUSY, 0x008b); 253 CPUMF_EVENT_ATTR(cf_z15, TX_C_TEND, 0x008c); 254 CPUMF_EVENT_ATTR(cf_z15, TX_NC_TEND, 0x008d); 255 CPUMF_EVENT_ATTR(cf_z15, L1C_TLB2_MISSES, 0x008f); 256 CPUMF_EVENT_ATTR(cf_z15, L1D_ONCHIP_L3_SOURCED_WRITES, 0x0090); 257 CPUMF_EVENT_ATTR(cf_z15, L1D_ONCHIP_MEMORY_SOURCED_WRITES, 0x0091); 258 CPUMF_EVENT_ATTR(cf_z15, L1D_ONCHIP_L3_SOURCED_WRITES_IV, 0x0092); 259 CPUMF_EVENT_ATTR(cf_z15, L1D_ONCLUSTER_L3_SOURCED_WRITES, 0x0093); 260 CPUMF_EVENT_ATTR(cf_z15, L1D_ONCLUSTER_MEMORY_SOURCED_WRITES, 0x0094); 261 CPUMF_EVENT_ATTR(cf_z15, L1D_ONCLUSTER_L3_SOURCED_WRITES_IV, 0x0095); 262 CPUMF_EVENT_ATTR(cf_z15, L1D_OFFCLUSTER_L3_SOURCED_WRITES, 0x0096); 263 CPUMF_EVENT_ATTR(cf_z15, L1D_OFFCLUSTER_MEMORY_SOURCED_WRITES, 0x0097); 264 CPUMF_EVENT_ATTR(cf_z15, L1D_OFFCLUSTER_L3_SOURCED_WRITES_IV, 0x0098); 265 CPUMF_EVENT_ATTR(cf_z15, L1D_OFFDRAWER_L3_SOURCED_WRITES, 0x0099); 266 CPUMF_EVENT_ATTR(cf_z15, L1D_OFFDRAWER_MEMORY_SOURCED_WRITES, 0x009a); 267 CPUMF_EVENT_ATTR(cf_z15, L1D_OFFDRAWER_L3_SOURCED_WRITES_IV, 0x009b); 268 CPUMF_EVENT_ATTR(cf_z15, L1D_ONDRAWER_L4_SOURCED_WRITES, 0x009c); 269 CPUMF_EVENT_ATTR(cf_z15, L1D_OFFDRAWER_L4_SOURCED_WRITES, 0x009d); 270 CPUMF_EVENT_ATTR(cf_z15, L1D_ONCHIP_L3_SOURCED_WRITES_RO, 0x009e); 271 CPUMF_EVENT_ATTR(cf_z15, L1I_ONCHIP_L3_SOURCED_WRITES, 0x00a2); 272 CPUMF_EVENT_ATTR(cf_z15, L1I_ONCHIP_MEMORY_SOURCED_WRITES, 0x00a3); 273 CPUMF_EVENT_ATTR(cf_z15, L1I_ONCHIP_L3_SOURCED_WRITES_IV, 0x00a4); 274 CPUMF_EVENT_ATTR(cf_z15, L1I_ONCLUSTER_L3_SOURCED_WRITES, 0x00a5); 275 CPUMF_EVENT_ATTR(cf_z15, L1I_ONCLUSTER_MEMORY_SOURCED_WRITES, 0x00a6); 276 CPUMF_EVENT_ATTR(cf_z15, L1I_ONCLUSTER_L3_SOURCED_WRITES_IV, 0x00a7); 277 CPUMF_EVENT_ATTR(cf_z15, L1I_OFFCLUSTER_L3_SOURCED_WRITES, 0x00a8); 278 CPUMF_EVENT_ATTR(cf_z15, L1I_OFFCLUSTER_MEMORY_SOURCED_WRITES, 0x00a9); 279 CPUMF_EVENT_ATTR(cf_z15, L1I_OFFCLUSTER_L3_SOURCED_WRITES_IV, 0x00aa); 280 CPUMF_EVENT_ATTR(cf_z15, L1I_OFFDRAWER_L3_SOURCED_WRITES, 0x00ab); 281 CPUMF_EVENT_ATTR(cf_z15, L1I_OFFDRAWER_MEMORY_SOURCED_WRITES, 0x00ac); 282 CPUMF_EVENT_ATTR(cf_z15, L1I_OFFDRAWER_L3_SOURCED_WRITES_IV, 0x00ad); 283 CPUMF_EVENT_ATTR(cf_z15, L1I_ONDRAWER_L4_SOURCED_WRITES, 0x00ae); 284 CPUMF_EVENT_ATTR(cf_z15, L1I_OFFDRAWER_L4_SOURCED_WRITES, 0x00af); 285 CPUMF_EVENT_ATTR(cf_z15, BCD_DFP_EXECUTION_SLOTS, 0x00e0); 286 CPUMF_EVENT_ATTR(cf_z15, VX_BCD_EXECUTION_SLOTS, 0x00e1); 287 CPUMF_EVENT_ATTR(cf_z15, DECIMAL_INSTRUCTIONS, 0x00e2); 288 CPUMF_EVENT_ATTR(cf_z15, LAST_HOST_TRANSLATIONS, 0x00e8); 289 CPUMF_EVENT_ATTR(cf_z15, TX_NC_TABORT, 0x00f3); 290 CPUMF_EVENT_ATTR(cf_z15, TX_C_TABORT_NO_SPECIAL, 0x00f4); 291 CPUMF_EVENT_ATTR(cf_z15, TX_C_TABORT_SPECIAL, 0x00f5); 292 CPUMF_EVENT_ATTR(cf_z15, DFLT_ACCESS, 0x00f7); 293 CPUMF_EVENT_ATTR(cf_z15, DFLT_CYCLES, 0x00fc); 294 CPUMF_EVENT_ATTR(cf_z15, DFLT_CC, 0x00108); 295 CPUMF_EVENT_ATTR(cf_z15, DFLT_CCFINISH, 0x00109); 296 CPUMF_EVENT_ATTR(cf_z15, MT_DIAG_CYCLES_ONE_THR_ACTIVE, 0x01c0); 297 CPUMF_EVENT_ATTR(cf_z15, MT_DIAG_CYCLES_TWO_THR_ACTIVE, 0x01c1); 298 299 static struct attribute *cpumcf_fvn1_pmu_event_attr[] __initdata = { 300 CPUMF_EVENT_PTR(cf_fvn1, CPU_CYCLES), 301 CPUMF_EVENT_PTR(cf_fvn1, INSTRUCTIONS), 302 CPUMF_EVENT_PTR(cf_fvn1, L1I_DIR_WRITES), 303 CPUMF_EVENT_PTR(cf_fvn1, L1I_PENALTY_CYCLES), 304 CPUMF_EVENT_PTR(cf_fvn1, PROBLEM_STATE_CPU_CYCLES), 305 CPUMF_EVENT_PTR(cf_fvn1, PROBLEM_STATE_INSTRUCTIONS), 306 CPUMF_EVENT_PTR(cf_fvn1, PROBLEM_STATE_L1I_DIR_WRITES), 307 CPUMF_EVENT_PTR(cf_fvn1, PROBLEM_STATE_L1I_PENALTY_CYCLES), 308 CPUMF_EVENT_PTR(cf_fvn1, PROBLEM_STATE_L1D_DIR_WRITES), 309 CPUMF_EVENT_PTR(cf_fvn1, PROBLEM_STATE_L1D_PENALTY_CYCLES), 310 CPUMF_EVENT_PTR(cf_fvn1, L1D_DIR_WRITES), 311 CPUMF_EVENT_PTR(cf_fvn1, L1D_PENALTY_CYCLES), 312 NULL, 313 }; 314 315 static struct attribute *cpumcf_fvn3_pmu_event_attr[] __initdata = { 316 CPUMF_EVENT_PTR(cf_fvn3, CPU_CYCLES), 317 CPUMF_EVENT_PTR(cf_fvn3, INSTRUCTIONS), 318 CPUMF_EVENT_PTR(cf_fvn3, L1I_DIR_WRITES), 319 CPUMF_EVENT_PTR(cf_fvn3, L1I_PENALTY_CYCLES), 320 CPUMF_EVENT_PTR(cf_fvn3, PROBLEM_STATE_CPU_CYCLES), 321 CPUMF_EVENT_PTR(cf_fvn3, PROBLEM_STATE_INSTRUCTIONS), 322 CPUMF_EVENT_PTR(cf_fvn3, L1D_DIR_WRITES), 323 CPUMF_EVENT_PTR(cf_fvn3, L1D_PENALTY_CYCLES), 324 NULL, 325 }; 326 327 static struct attribute *cpumcf_svn_12345_pmu_event_attr[] __initdata = { 328 CPUMF_EVENT_PTR(cf_svn_12345, PRNG_FUNCTIONS), 329 CPUMF_EVENT_PTR(cf_svn_12345, PRNG_CYCLES), 330 CPUMF_EVENT_PTR(cf_svn_12345, PRNG_BLOCKED_FUNCTIONS), 331 CPUMF_EVENT_PTR(cf_svn_12345, PRNG_BLOCKED_CYCLES), 332 CPUMF_EVENT_PTR(cf_svn_12345, SHA_FUNCTIONS), 333 CPUMF_EVENT_PTR(cf_svn_12345, SHA_CYCLES), 334 CPUMF_EVENT_PTR(cf_svn_12345, SHA_BLOCKED_FUNCTIONS), 335 CPUMF_EVENT_PTR(cf_svn_12345, SHA_BLOCKED_CYCLES), 336 CPUMF_EVENT_PTR(cf_svn_12345, DEA_FUNCTIONS), 337 CPUMF_EVENT_PTR(cf_svn_12345, DEA_CYCLES), 338 CPUMF_EVENT_PTR(cf_svn_12345, DEA_BLOCKED_FUNCTIONS), 339 CPUMF_EVENT_PTR(cf_svn_12345, DEA_BLOCKED_CYCLES), 340 CPUMF_EVENT_PTR(cf_svn_12345, AES_FUNCTIONS), 341 CPUMF_EVENT_PTR(cf_svn_12345, AES_CYCLES), 342 CPUMF_EVENT_PTR(cf_svn_12345, AES_BLOCKED_FUNCTIONS), 343 CPUMF_EVENT_PTR(cf_svn_12345, AES_BLOCKED_CYCLES), 344 NULL, 345 }; 346 347 static struct attribute *cpumcf_svn_6_pmu_event_attr[] __initdata = { 348 CPUMF_EVENT_PTR(cf_svn_12345, PRNG_FUNCTIONS), 349 CPUMF_EVENT_PTR(cf_svn_12345, PRNG_CYCLES), 350 CPUMF_EVENT_PTR(cf_svn_12345, PRNG_BLOCKED_FUNCTIONS), 351 CPUMF_EVENT_PTR(cf_svn_12345, PRNG_BLOCKED_CYCLES), 352 CPUMF_EVENT_PTR(cf_svn_12345, SHA_FUNCTIONS), 353 CPUMF_EVENT_PTR(cf_svn_12345, SHA_CYCLES), 354 CPUMF_EVENT_PTR(cf_svn_12345, SHA_BLOCKED_FUNCTIONS), 355 CPUMF_EVENT_PTR(cf_svn_12345, SHA_BLOCKED_CYCLES), 356 CPUMF_EVENT_PTR(cf_svn_12345, DEA_FUNCTIONS), 357 CPUMF_EVENT_PTR(cf_svn_12345, DEA_CYCLES), 358 CPUMF_EVENT_PTR(cf_svn_12345, DEA_BLOCKED_FUNCTIONS), 359 CPUMF_EVENT_PTR(cf_svn_12345, DEA_BLOCKED_CYCLES), 360 CPUMF_EVENT_PTR(cf_svn_12345, AES_FUNCTIONS), 361 CPUMF_EVENT_PTR(cf_svn_12345, AES_CYCLES), 362 CPUMF_EVENT_PTR(cf_svn_12345, AES_BLOCKED_FUNCTIONS), 363 CPUMF_EVENT_PTR(cf_svn_12345, AES_BLOCKED_CYCLES), 364 CPUMF_EVENT_PTR(cf_svn_6, ECC_FUNCTION_COUNT), 365 CPUMF_EVENT_PTR(cf_svn_6, ECC_CYCLES_COUNT), 366 CPUMF_EVENT_PTR(cf_svn_6, ECC_BLOCKED_FUNCTION_COUNT), 367 CPUMF_EVENT_PTR(cf_svn_6, ECC_BLOCKED_CYCLES_COUNT), 368 NULL, 369 }; 370 371 static struct attribute *cpumcf_z10_pmu_event_attr[] __initdata = { 372 CPUMF_EVENT_PTR(cf_z10, L1I_L2_SOURCED_WRITES), 373 CPUMF_EVENT_PTR(cf_z10, L1D_L2_SOURCED_WRITES), 374 CPUMF_EVENT_PTR(cf_z10, L1I_L3_LOCAL_WRITES), 375 CPUMF_EVENT_PTR(cf_z10, L1D_L3_LOCAL_WRITES), 376 CPUMF_EVENT_PTR(cf_z10, L1I_L3_REMOTE_WRITES), 377 CPUMF_EVENT_PTR(cf_z10, L1D_L3_REMOTE_WRITES), 378 CPUMF_EVENT_PTR(cf_z10, L1D_LMEM_SOURCED_WRITES), 379 CPUMF_EVENT_PTR(cf_z10, L1I_LMEM_SOURCED_WRITES), 380 CPUMF_EVENT_PTR(cf_z10, L1D_RO_EXCL_WRITES), 381 CPUMF_EVENT_PTR(cf_z10, L1I_CACHELINE_INVALIDATES), 382 CPUMF_EVENT_PTR(cf_z10, ITLB1_WRITES), 383 CPUMF_EVENT_PTR(cf_z10, DTLB1_WRITES), 384 CPUMF_EVENT_PTR(cf_z10, TLB2_PTE_WRITES), 385 CPUMF_EVENT_PTR(cf_z10, TLB2_CRSTE_WRITES), 386 CPUMF_EVENT_PTR(cf_z10, TLB2_CRSTE_HPAGE_WRITES), 387 CPUMF_EVENT_PTR(cf_z10, ITLB1_MISSES), 388 CPUMF_EVENT_PTR(cf_z10, DTLB1_MISSES), 389 CPUMF_EVENT_PTR(cf_z10, L2C_STORES_SENT), 390 NULL, 391 }; 392 393 static struct attribute *cpumcf_z196_pmu_event_attr[] __initdata = { 394 CPUMF_EVENT_PTR(cf_z196, L1D_L2_SOURCED_WRITES), 395 CPUMF_EVENT_PTR(cf_z196, L1I_L2_SOURCED_WRITES), 396 CPUMF_EVENT_PTR(cf_z196, DTLB1_MISSES), 397 CPUMF_EVENT_PTR(cf_z196, ITLB1_MISSES), 398 CPUMF_EVENT_PTR(cf_z196, L2C_STORES_SENT), 399 CPUMF_EVENT_PTR(cf_z196, L1D_OFFBOOK_L3_SOURCED_WRITES), 400 CPUMF_EVENT_PTR(cf_z196, L1D_ONBOOK_L4_SOURCED_WRITES), 401 CPUMF_EVENT_PTR(cf_z196, L1I_ONBOOK_L4_SOURCED_WRITES), 402 CPUMF_EVENT_PTR(cf_z196, L1D_RO_EXCL_WRITES), 403 CPUMF_EVENT_PTR(cf_z196, L1D_OFFBOOK_L4_SOURCED_WRITES), 404 CPUMF_EVENT_PTR(cf_z196, L1I_OFFBOOK_L4_SOURCED_WRITES), 405 CPUMF_EVENT_PTR(cf_z196, DTLB1_HPAGE_WRITES), 406 CPUMF_EVENT_PTR(cf_z196, L1D_LMEM_SOURCED_WRITES), 407 CPUMF_EVENT_PTR(cf_z196, L1I_LMEM_SOURCED_WRITES), 408 CPUMF_EVENT_PTR(cf_z196, L1I_OFFBOOK_L3_SOURCED_WRITES), 409 CPUMF_EVENT_PTR(cf_z196, DTLB1_WRITES), 410 CPUMF_EVENT_PTR(cf_z196, ITLB1_WRITES), 411 CPUMF_EVENT_PTR(cf_z196, TLB2_PTE_WRITES), 412 CPUMF_EVENT_PTR(cf_z196, TLB2_CRSTE_HPAGE_WRITES), 413 CPUMF_EVENT_PTR(cf_z196, TLB2_CRSTE_WRITES), 414 CPUMF_EVENT_PTR(cf_z196, L1D_ONCHIP_L3_SOURCED_WRITES), 415 CPUMF_EVENT_PTR(cf_z196, L1D_OFFCHIP_L3_SOURCED_WRITES), 416 CPUMF_EVENT_PTR(cf_z196, L1I_ONCHIP_L3_SOURCED_WRITES), 417 CPUMF_EVENT_PTR(cf_z196, L1I_OFFCHIP_L3_SOURCED_WRITES), 418 NULL, 419 }; 420 421 static struct attribute *cpumcf_zec12_pmu_event_attr[] __initdata = { 422 CPUMF_EVENT_PTR(cf_zec12, DTLB1_MISSES), 423 CPUMF_EVENT_PTR(cf_zec12, ITLB1_MISSES), 424 CPUMF_EVENT_PTR(cf_zec12, L1D_L2I_SOURCED_WRITES), 425 CPUMF_EVENT_PTR(cf_zec12, L1I_L2I_SOURCED_WRITES), 426 CPUMF_EVENT_PTR(cf_zec12, L1D_L2D_SOURCED_WRITES), 427 CPUMF_EVENT_PTR(cf_zec12, DTLB1_WRITES), 428 CPUMF_EVENT_PTR(cf_zec12, L1D_LMEM_SOURCED_WRITES), 429 CPUMF_EVENT_PTR(cf_zec12, L1I_LMEM_SOURCED_WRITES), 430 CPUMF_EVENT_PTR(cf_zec12, L1D_RO_EXCL_WRITES), 431 CPUMF_EVENT_PTR(cf_zec12, DTLB1_HPAGE_WRITES), 432 CPUMF_EVENT_PTR(cf_zec12, ITLB1_WRITES), 433 CPUMF_EVENT_PTR(cf_zec12, TLB2_PTE_WRITES), 434 CPUMF_EVENT_PTR(cf_zec12, TLB2_CRSTE_HPAGE_WRITES), 435 CPUMF_EVENT_PTR(cf_zec12, TLB2_CRSTE_WRITES), 436 CPUMF_EVENT_PTR(cf_zec12, L1D_ONCHIP_L3_SOURCED_WRITES), 437 CPUMF_EVENT_PTR(cf_zec12, L1D_OFFCHIP_L3_SOURCED_WRITES), 438 CPUMF_EVENT_PTR(cf_zec12, L1D_OFFBOOK_L3_SOURCED_WRITES), 439 CPUMF_EVENT_PTR(cf_zec12, L1D_ONBOOK_L4_SOURCED_WRITES), 440 CPUMF_EVENT_PTR(cf_zec12, L1D_OFFBOOK_L4_SOURCED_WRITES), 441 CPUMF_EVENT_PTR(cf_zec12, TX_NC_TEND), 442 CPUMF_EVENT_PTR(cf_zec12, L1D_ONCHIP_L3_SOURCED_WRITES_IV), 443 CPUMF_EVENT_PTR(cf_zec12, L1D_OFFCHIP_L3_SOURCED_WRITES_IV), 444 CPUMF_EVENT_PTR(cf_zec12, L1D_OFFBOOK_L3_SOURCED_WRITES_IV), 445 CPUMF_EVENT_PTR(cf_zec12, L1I_ONCHIP_L3_SOURCED_WRITES), 446 CPUMF_EVENT_PTR(cf_zec12, L1I_OFFCHIP_L3_SOURCED_WRITES), 447 CPUMF_EVENT_PTR(cf_zec12, L1I_OFFBOOK_L3_SOURCED_WRITES), 448 CPUMF_EVENT_PTR(cf_zec12, L1I_ONBOOK_L4_SOURCED_WRITES), 449 CPUMF_EVENT_PTR(cf_zec12, L1I_OFFBOOK_L4_SOURCED_WRITES), 450 CPUMF_EVENT_PTR(cf_zec12, TX_C_TEND), 451 CPUMF_EVENT_PTR(cf_zec12, L1I_ONCHIP_L3_SOURCED_WRITES_IV), 452 CPUMF_EVENT_PTR(cf_zec12, L1I_OFFCHIP_L3_SOURCED_WRITES_IV), 453 CPUMF_EVENT_PTR(cf_zec12, L1I_OFFBOOK_L3_SOURCED_WRITES_IV), 454 CPUMF_EVENT_PTR(cf_zec12, TX_NC_TABORT), 455 CPUMF_EVENT_PTR(cf_zec12, TX_C_TABORT_NO_SPECIAL), 456 CPUMF_EVENT_PTR(cf_zec12, TX_C_TABORT_SPECIAL), 457 NULL, 458 }; 459 460 static struct attribute *cpumcf_z13_pmu_event_attr[] __initdata = { 461 CPUMF_EVENT_PTR(cf_z13, L1D_RO_EXCL_WRITES), 462 CPUMF_EVENT_PTR(cf_z13, DTLB1_WRITES), 463 CPUMF_EVENT_PTR(cf_z13, DTLB1_MISSES), 464 CPUMF_EVENT_PTR(cf_z13, DTLB1_HPAGE_WRITES), 465 CPUMF_EVENT_PTR(cf_z13, DTLB1_GPAGE_WRITES), 466 CPUMF_EVENT_PTR(cf_z13, L1D_L2D_SOURCED_WRITES), 467 CPUMF_EVENT_PTR(cf_z13, ITLB1_WRITES), 468 CPUMF_EVENT_PTR(cf_z13, ITLB1_MISSES), 469 CPUMF_EVENT_PTR(cf_z13, L1I_L2I_SOURCED_WRITES), 470 CPUMF_EVENT_PTR(cf_z13, TLB2_PTE_WRITES), 471 CPUMF_EVENT_PTR(cf_z13, TLB2_CRSTE_HPAGE_WRITES), 472 CPUMF_EVENT_PTR(cf_z13, TLB2_CRSTE_WRITES), 473 CPUMF_EVENT_PTR(cf_z13, TX_C_TEND), 474 CPUMF_EVENT_PTR(cf_z13, TX_NC_TEND), 475 CPUMF_EVENT_PTR(cf_z13, L1C_TLB1_MISSES), 476 CPUMF_EVENT_PTR(cf_z13, L1D_ONCHIP_L3_SOURCED_WRITES), 477 CPUMF_EVENT_PTR(cf_z13, L1D_ONCHIP_L3_SOURCED_WRITES_IV), 478 CPUMF_EVENT_PTR(cf_z13, L1D_ONNODE_L4_SOURCED_WRITES), 479 CPUMF_EVENT_PTR(cf_z13, L1D_ONNODE_L3_SOURCED_WRITES_IV), 480 CPUMF_EVENT_PTR(cf_z13, L1D_ONNODE_L3_SOURCED_WRITES), 481 CPUMF_EVENT_PTR(cf_z13, L1D_ONDRAWER_L4_SOURCED_WRITES), 482 CPUMF_EVENT_PTR(cf_z13, L1D_ONDRAWER_L3_SOURCED_WRITES_IV), 483 CPUMF_EVENT_PTR(cf_z13, L1D_ONDRAWER_L3_SOURCED_WRITES), 484 CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_SCOL_L4_SOURCED_WRITES), 485 CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV), 486 CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES), 487 CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_FCOL_L4_SOURCED_WRITES), 488 CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV), 489 CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES), 490 CPUMF_EVENT_PTR(cf_z13, L1D_ONNODE_MEM_SOURCED_WRITES), 491 CPUMF_EVENT_PTR(cf_z13, L1D_ONDRAWER_MEM_SOURCED_WRITES), 492 CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_MEM_SOURCED_WRITES), 493 CPUMF_EVENT_PTR(cf_z13, L1D_ONCHIP_MEM_SOURCED_WRITES), 494 CPUMF_EVENT_PTR(cf_z13, L1I_ONCHIP_L3_SOURCED_WRITES), 495 CPUMF_EVENT_PTR(cf_z13, L1I_ONCHIP_L3_SOURCED_WRITES_IV), 496 CPUMF_EVENT_PTR(cf_z13, L1I_ONNODE_L4_SOURCED_WRITES), 497 CPUMF_EVENT_PTR(cf_z13, L1I_ONNODE_L3_SOURCED_WRITES_IV), 498 CPUMF_EVENT_PTR(cf_z13, L1I_ONNODE_L3_SOURCED_WRITES), 499 CPUMF_EVENT_PTR(cf_z13, L1I_ONDRAWER_L4_SOURCED_WRITES), 500 CPUMF_EVENT_PTR(cf_z13, L1I_ONDRAWER_L3_SOURCED_WRITES_IV), 501 CPUMF_EVENT_PTR(cf_z13, L1I_ONDRAWER_L3_SOURCED_WRITES), 502 CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_SCOL_L4_SOURCED_WRITES), 503 CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV), 504 CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES), 505 CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_FCOL_L4_SOURCED_WRITES), 506 CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV), 507 CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES), 508 CPUMF_EVENT_PTR(cf_z13, L1I_ONNODE_MEM_SOURCED_WRITES), 509 CPUMF_EVENT_PTR(cf_z13, L1I_ONDRAWER_MEM_SOURCED_WRITES), 510 CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_MEM_SOURCED_WRITES), 511 CPUMF_EVENT_PTR(cf_z13, L1I_ONCHIP_MEM_SOURCED_WRITES), 512 CPUMF_EVENT_PTR(cf_z13, TX_NC_TABORT), 513 CPUMF_EVENT_PTR(cf_z13, TX_C_TABORT_NO_SPECIAL), 514 CPUMF_EVENT_PTR(cf_z13, TX_C_TABORT_SPECIAL), 515 CPUMF_EVENT_PTR(cf_z13, MT_DIAG_CYCLES_ONE_THR_ACTIVE), 516 CPUMF_EVENT_PTR(cf_z13, MT_DIAG_CYCLES_TWO_THR_ACTIVE), 517 NULL, 518 }; 519 520 static struct attribute *cpumcf_z14_pmu_event_attr[] __initdata = { 521 CPUMF_EVENT_PTR(cf_z14, L1D_RO_EXCL_WRITES), 522 CPUMF_EVENT_PTR(cf_z14, DTLB2_WRITES), 523 CPUMF_EVENT_PTR(cf_z14, DTLB2_MISSES), 524 CPUMF_EVENT_PTR(cf_z14, DTLB2_HPAGE_WRITES), 525 CPUMF_EVENT_PTR(cf_z14, DTLB2_GPAGE_WRITES), 526 CPUMF_EVENT_PTR(cf_z14, L1D_L2D_SOURCED_WRITES), 527 CPUMF_EVENT_PTR(cf_z14, ITLB2_WRITES), 528 CPUMF_EVENT_PTR(cf_z14, ITLB2_MISSES), 529 CPUMF_EVENT_PTR(cf_z14, L1I_L2I_SOURCED_WRITES), 530 CPUMF_EVENT_PTR(cf_z14, TLB2_PTE_WRITES), 531 CPUMF_EVENT_PTR(cf_z14, TLB2_CRSTE_WRITES), 532 CPUMF_EVENT_PTR(cf_z14, TLB2_ENGINES_BUSY), 533 CPUMF_EVENT_PTR(cf_z14, TX_C_TEND), 534 CPUMF_EVENT_PTR(cf_z14, TX_NC_TEND), 535 CPUMF_EVENT_PTR(cf_z14, L1C_TLB2_MISSES), 536 CPUMF_EVENT_PTR(cf_z14, L1D_ONCHIP_L3_SOURCED_WRITES), 537 CPUMF_EVENT_PTR(cf_z14, L1D_ONCHIP_MEMORY_SOURCED_WRITES), 538 CPUMF_EVENT_PTR(cf_z14, L1D_ONCHIP_L3_SOURCED_WRITES_IV), 539 CPUMF_EVENT_PTR(cf_z14, L1D_ONCLUSTER_L3_SOURCED_WRITES), 540 CPUMF_EVENT_PTR(cf_z14, L1D_ONCLUSTER_MEMORY_SOURCED_WRITES), 541 CPUMF_EVENT_PTR(cf_z14, L1D_ONCLUSTER_L3_SOURCED_WRITES_IV), 542 CPUMF_EVENT_PTR(cf_z14, L1D_OFFCLUSTER_L3_SOURCED_WRITES), 543 CPUMF_EVENT_PTR(cf_z14, L1D_OFFCLUSTER_MEMORY_SOURCED_WRITES), 544 CPUMF_EVENT_PTR(cf_z14, L1D_OFFCLUSTER_L3_SOURCED_WRITES_IV), 545 CPUMF_EVENT_PTR(cf_z14, L1D_OFFDRAWER_L3_SOURCED_WRITES), 546 CPUMF_EVENT_PTR(cf_z14, L1D_OFFDRAWER_MEMORY_SOURCED_WRITES), 547 CPUMF_EVENT_PTR(cf_z14, L1D_OFFDRAWER_L3_SOURCED_WRITES_IV), 548 CPUMF_EVENT_PTR(cf_z14, L1D_ONDRAWER_L4_SOURCED_WRITES), 549 CPUMF_EVENT_PTR(cf_z14, L1D_OFFDRAWER_L4_SOURCED_WRITES), 550 CPUMF_EVENT_PTR(cf_z14, L1D_ONCHIP_L3_SOURCED_WRITES_RO), 551 CPUMF_EVENT_PTR(cf_z14, L1I_ONCHIP_L3_SOURCED_WRITES), 552 CPUMF_EVENT_PTR(cf_z14, L1I_ONCHIP_MEMORY_SOURCED_WRITES), 553 CPUMF_EVENT_PTR(cf_z14, L1I_ONCHIP_L3_SOURCED_WRITES_IV), 554 CPUMF_EVENT_PTR(cf_z14, L1I_ONCLUSTER_L3_SOURCED_WRITES), 555 CPUMF_EVENT_PTR(cf_z14, L1I_ONCLUSTER_MEMORY_SOURCED_WRITES), 556 CPUMF_EVENT_PTR(cf_z14, L1I_ONCLUSTER_L3_SOURCED_WRITES_IV), 557 CPUMF_EVENT_PTR(cf_z14, L1I_OFFCLUSTER_L3_SOURCED_WRITES), 558 CPUMF_EVENT_PTR(cf_z14, L1I_OFFCLUSTER_MEMORY_SOURCED_WRITES), 559 CPUMF_EVENT_PTR(cf_z14, L1I_OFFCLUSTER_L3_SOURCED_WRITES_IV), 560 CPUMF_EVENT_PTR(cf_z14, L1I_OFFDRAWER_L3_SOURCED_WRITES), 561 CPUMF_EVENT_PTR(cf_z14, L1I_OFFDRAWER_MEMORY_SOURCED_WRITES), 562 CPUMF_EVENT_PTR(cf_z14, L1I_OFFDRAWER_L3_SOURCED_WRITES_IV), 563 CPUMF_EVENT_PTR(cf_z14, L1I_ONDRAWER_L4_SOURCED_WRITES), 564 CPUMF_EVENT_PTR(cf_z14, L1I_OFFDRAWER_L4_SOURCED_WRITES), 565 CPUMF_EVENT_PTR(cf_z14, BCD_DFP_EXECUTION_SLOTS), 566 CPUMF_EVENT_PTR(cf_z14, VX_BCD_EXECUTION_SLOTS), 567 CPUMF_EVENT_PTR(cf_z14, DECIMAL_INSTRUCTIONS), 568 CPUMF_EVENT_PTR(cf_z14, LAST_HOST_TRANSLATIONS), 569 CPUMF_EVENT_PTR(cf_z14, TX_NC_TABORT), 570 CPUMF_EVENT_PTR(cf_z14, TX_C_TABORT_NO_SPECIAL), 571 CPUMF_EVENT_PTR(cf_z14, TX_C_TABORT_SPECIAL), 572 CPUMF_EVENT_PTR(cf_z14, MT_DIAG_CYCLES_ONE_THR_ACTIVE), 573 CPUMF_EVENT_PTR(cf_z14, MT_DIAG_CYCLES_TWO_THR_ACTIVE), 574 NULL, 575 }; 576 577 static struct attribute *cpumcf_z15_pmu_event_attr[] __initdata = { 578 CPUMF_EVENT_PTR(cf_z15, L1D_RO_EXCL_WRITES), 579 CPUMF_EVENT_PTR(cf_z15, DTLB2_WRITES), 580 CPUMF_EVENT_PTR(cf_z15, DTLB2_MISSES), 581 CPUMF_EVENT_PTR(cf_z15, DTLB2_HPAGE_WRITES), 582 CPUMF_EVENT_PTR(cf_z15, DTLB2_GPAGE_WRITES), 583 CPUMF_EVENT_PTR(cf_z15, L1D_L2D_SOURCED_WRITES), 584 CPUMF_EVENT_PTR(cf_z15, ITLB2_WRITES), 585 CPUMF_EVENT_PTR(cf_z15, ITLB2_MISSES), 586 CPUMF_EVENT_PTR(cf_z15, L1I_L2I_SOURCED_WRITES), 587 CPUMF_EVENT_PTR(cf_z15, TLB2_PTE_WRITES), 588 CPUMF_EVENT_PTR(cf_z15, TLB2_CRSTE_WRITES), 589 CPUMF_EVENT_PTR(cf_z15, TLB2_ENGINES_BUSY), 590 CPUMF_EVENT_PTR(cf_z15, TX_C_TEND), 591 CPUMF_EVENT_PTR(cf_z15, TX_NC_TEND), 592 CPUMF_EVENT_PTR(cf_z15, L1C_TLB2_MISSES), 593 CPUMF_EVENT_PTR(cf_z15, L1D_ONCHIP_L3_SOURCED_WRITES), 594 CPUMF_EVENT_PTR(cf_z15, L1D_ONCHIP_MEMORY_SOURCED_WRITES), 595 CPUMF_EVENT_PTR(cf_z15, L1D_ONCHIP_L3_SOURCED_WRITES_IV), 596 CPUMF_EVENT_PTR(cf_z15, L1D_ONCLUSTER_L3_SOURCED_WRITES), 597 CPUMF_EVENT_PTR(cf_z15, L1D_ONCLUSTER_MEMORY_SOURCED_WRITES), 598 CPUMF_EVENT_PTR(cf_z15, L1D_ONCLUSTER_L3_SOURCED_WRITES_IV), 599 CPUMF_EVENT_PTR(cf_z15, L1D_OFFCLUSTER_L3_SOURCED_WRITES), 600 CPUMF_EVENT_PTR(cf_z15, L1D_OFFCLUSTER_MEMORY_SOURCED_WRITES), 601 CPUMF_EVENT_PTR(cf_z15, L1D_OFFCLUSTER_L3_SOURCED_WRITES_IV), 602 CPUMF_EVENT_PTR(cf_z15, L1D_OFFDRAWER_L3_SOURCED_WRITES), 603 CPUMF_EVENT_PTR(cf_z15, L1D_OFFDRAWER_MEMORY_SOURCED_WRITES), 604 CPUMF_EVENT_PTR(cf_z15, L1D_OFFDRAWER_L3_SOURCED_WRITES_IV), 605 CPUMF_EVENT_PTR(cf_z15, L1D_ONDRAWER_L4_SOURCED_WRITES), 606 CPUMF_EVENT_PTR(cf_z15, L1D_OFFDRAWER_L4_SOURCED_WRITES), 607 CPUMF_EVENT_PTR(cf_z15, L1D_ONCHIP_L3_SOURCED_WRITES_RO), 608 CPUMF_EVENT_PTR(cf_z15, L1I_ONCHIP_L3_SOURCED_WRITES), 609 CPUMF_EVENT_PTR(cf_z15, L1I_ONCHIP_MEMORY_SOURCED_WRITES), 610 CPUMF_EVENT_PTR(cf_z15, L1I_ONCHIP_L3_SOURCED_WRITES_IV), 611 CPUMF_EVENT_PTR(cf_z15, L1I_ONCLUSTER_L3_SOURCED_WRITES), 612 CPUMF_EVENT_PTR(cf_z15, L1I_ONCLUSTER_MEMORY_SOURCED_WRITES), 613 CPUMF_EVENT_PTR(cf_z15, L1I_ONCLUSTER_L3_SOURCED_WRITES_IV), 614 CPUMF_EVENT_PTR(cf_z15, L1I_OFFCLUSTER_L3_SOURCED_WRITES), 615 CPUMF_EVENT_PTR(cf_z15, L1I_OFFCLUSTER_MEMORY_SOURCED_WRITES), 616 CPUMF_EVENT_PTR(cf_z15, L1I_OFFCLUSTER_L3_SOURCED_WRITES_IV), 617 CPUMF_EVENT_PTR(cf_z15, L1I_OFFDRAWER_L3_SOURCED_WRITES), 618 CPUMF_EVENT_PTR(cf_z15, L1I_OFFDRAWER_MEMORY_SOURCED_WRITES), 619 CPUMF_EVENT_PTR(cf_z15, L1I_OFFDRAWER_L3_SOURCED_WRITES_IV), 620 CPUMF_EVENT_PTR(cf_z15, L1I_ONDRAWER_L4_SOURCED_WRITES), 621 CPUMF_EVENT_PTR(cf_z15, L1I_OFFDRAWER_L4_SOURCED_WRITES), 622 CPUMF_EVENT_PTR(cf_z15, BCD_DFP_EXECUTION_SLOTS), 623 CPUMF_EVENT_PTR(cf_z15, VX_BCD_EXECUTION_SLOTS), 624 CPUMF_EVENT_PTR(cf_z15, DECIMAL_INSTRUCTIONS), 625 CPUMF_EVENT_PTR(cf_z15, LAST_HOST_TRANSLATIONS), 626 CPUMF_EVENT_PTR(cf_z15, TX_NC_TABORT), 627 CPUMF_EVENT_PTR(cf_z15, TX_C_TABORT_NO_SPECIAL), 628 CPUMF_EVENT_PTR(cf_z15, TX_C_TABORT_SPECIAL), 629 CPUMF_EVENT_PTR(cf_z15, DFLT_ACCESS), 630 CPUMF_EVENT_PTR(cf_z15, DFLT_CYCLES), 631 CPUMF_EVENT_PTR(cf_z15, DFLT_CC), 632 CPUMF_EVENT_PTR(cf_z15, DFLT_CCFINISH), 633 CPUMF_EVENT_PTR(cf_z15, MT_DIAG_CYCLES_ONE_THR_ACTIVE), 634 CPUMF_EVENT_PTR(cf_z15, MT_DIAG_CYCLES_TWO_THR_ACTIVE), 635 NULL, 636 }; 637 638 /* END: CPUM_CF COUNTER DEFINITIONS ===================================== */ 639 640 static struct attribute_group cpumcf_pmu_events_group = { 641 .name = "events", 642 }; 643 644 PMU_FORMAT_ATTR(event, "config:0-63"); 645 646 static struct attribute *cpumcf_pmu_format_attr[] = { 647 &format_attr_event.attr, 648 NULL, 649 }; 650 651 static struct attribute_group cpumcf_pmu_format_group = { 652 .name = "format", 653 .attrs = cpumcf_pmu_format_attr, 654 }; 655 656 static const struct attribute_group *cpumcf_pmu_attr_groups[] = { 657 &cpumcf_pmu_events_group, 658 &cpumcf_pmu_format_group, 659 NULL, 660 }; 661 662 663 static __init struct attribute **merge_attr(struct attribute **a, 664 struct attribute **b, 665 struct attribute **c) 666 { 667 struct attribute **new; 668 int j, i; 669 670 for (j = 0; a[j]; j++) 671 ; 672 for (i = 0; b[i]; i++) 673 j++; 674 for (i = 0; c[i]; i++) 675 j++; 676 j++; 677 678 new = kmalloc_array(j, sizeof(struct attribute *), GFP_KERNEL); 679 if (!new) 680 return NULL; 681 j = 0; 682 for (i = 0; a[i]; i++) 683 new[j++] = a[i]; 684 for (i = 0; b[i]; i++) 685 new[j++] = b[i]; 686 for (i = 0; c[i]; i++) 687 new[j++] = c[i]; 688 new[j] = NULL; 689 690 return new; 691 } 692 693 __init const struct attribute_group **cpumf_cf_event_group(void) 694 { 695 struct attribute **combined, **model, **cfvn, **csvn; 696 struct attribute *none[] = { NULL }; 697 struct cpumf_ctr_info ci; 698 struct cpuid cpu_id; 699 700 /* Determine generic counters set(s) */ 701 qctri(&ci); 702 switch (ci.cfvn) { 703 case 1: 704 cfvn = cpumcf_fvn1_pmu_event_attr; 705 break; 706 case 3: 707 cfvn = cpumcf_fvn3_pmu_event_attr; 708 break; 709 default: 710 cfvn = none; 711 } 712 713 /* Determine version specific crypto set */ 714 switch (ci.csvn) { 715 case 1 ... 5: 716 csvn = cpumcf_svn_12345_pmu_event_attr; 717 break; 718 case 6: 719 csvn = cpumcf_svn_6_pmu_event_attr; 720 break; 721 default: 722 csvn = none; 723 } 724 725 /* Determine model-specific counter set(s) */ 726 get_cpu_id(&cpu_id); 727 switch (cpu_id.machine) { 728 case 0x2097: 729 case 0x2098: 730 model = cpumcf_z10_pmu_event_attr; 731 break; 732 case 0x2817: 733 case 0x2818: 734 model = cpumcf_z196_pmu_event_attr; 735 break; 736 case 0x2827: 737 case 0x2828: 738 model = cpumcf_zec12_pmu_event_attr; 739 break; 740 case 0x2964: 741 case 0x2965: 742 model = cpumcf_z13_pmu_event_attr; 743 break; 744 case 0x3906: 745 case 0x3907: 746 model = cpumcf_z14_pmu_event_attr; 747 break; 748 case 0x8561: 749 case 0x8562: 750 model = cpumcf_z15_pmu_event_attr; 751 break; 752 default: 753 model = none; 754 break; 755 } 756 757 combined = merge_attr(cfvn, csvn, model); 758 if (combined) 759 cpumcf_pmu_events_group.attrs = combined; 760 return cpumcf_pmu_attr_groups; 761 } 762