1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Performance event support for s390x - CPU-measurement Counter Facility 4 * 5 * Copyright IBM Corp. 2012, 2017 6 * Author(s): Hendrik Brueckner <brueckner@linux.vnet.ibm.com> 7 */ 8 #define KMSG_COMPONENT "cpum_cf" 9 #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt 10 11 #include <linux/kernel.h> 12 #include <linux/kernel_stat.h> 13 #include <linux/percpu.h> 14 #include <linux/notifier.h> 15 #include <linux/init.h> 16 #include <linux/export.h> 17 #include <asm/cpu_mcf.h> 18 19 static enum cpumf_ctr_set get_counter_set(u64 event) 20 { 21 int set = CPUMF_CTR_SET_MAX; 22 23 if (event < 32) 24 set = CPUMF_CTR_SET_BASIC; 25 else if (event < 64) 26 set = CPUMF_CTR_SET_USER; 27 else if (event < 128) 28 set = CPUMF_CTR_SET_CRYPTO; 29 else if (event < 256) 30 set = CPUMF_CTR_SET_EXT; 31 else if (event >= 448 && event < 496) 32 set = CPUMF_CTR_SET_MT_DIAG; 33 34 return set; 35 } 36 37 static int validate_ctr_version(const struct hw_perf_event *hwc) 38 { 39 struct cpu_cf_events *cpuhw; 40 int err = 0; 41 u16 mtdiag_ctl; 42 43 cpuhw = &get_cpu_var(cpu_cf_events); 44 45 /* check required version for counter sets */ 46 switch (hwc->config_base) { 47 case CPUMF_CTR_SET_BASIC: 48 case CPUMF_CTR_SET_USER: 49 if (cpuhw->info.cfvn < 1) 50 err = -EOPNOTSUPP; 51 break; 52 case CPUMF_CTR_SET_CRYPTO: 53 case CPUMF_CTR_SET_EXT: 54 if (cpuhw->info.csvn < 1) 55 err = -EOPNOTSUPP; 56 if ((cpuhw->info.csvn == 1 && hwc->config > 159) || 57 (cpuhw->info.csvn == 2 && hwc->config > 175) || 58 (cpuhw->info.csvn > 2 && hwc->config > 255)) 59 err = -EOPNOTSUPP; 60 break; 61 case CPUMF_CTR_SET_MT_DIAG: 62 if (cpuhw->info.csvn <= 3) 63 err = -EOPNOTSUPP; 64 /* 65 * MT-diagnostic counters are read-only. The counter set 66 * is automatically enabled and activated on all CPUs with 67 * multithreading (SMT). Deactivation of multithreading 68 * also disables the counter set. State changes are ignored 69 * by lcctl(). Because Linux controls SMT enablement through 70 * a kernel parameter only, the counter set is either disabled 71 * or enabled and active. 72 * 73 * Thus, the counters can only be used if SMT is on and the 74 * counter set is enabled and active. 75 */ 76 mtdiag_ctl = cpumf_ctr_ctl[CPUMF_CTR_SET_MT_DIAG]; 77 if (!((cpuhw->info.auth_ctl & mtdiag_ctl) && 78 (cpuhw->info.enable_ctl & mtdiag_ctl) && 79 (cpuhw->info.act_ctl & mtdiag_ctl))) 80 err = -EOPNOTSUPP; 81 break; 82 } 83 84 put_cpu_var(cpu_cf_events); 85 return err; 86 } 87 88 static int validate_ctr_auth(const struct hw_perf_event *hwc) 89 { 90 struct cpu_cf_events *cpuhw; 91 u64 ctrs_state; 92 int err = 0; 93 94 cpuhw = &get_cpu_var(cpu_cf_events); 95 96 /* Check authorization for cpu counter sets. 97 * If the particular CPU counter set is not authorized, 98 * return with -ENOENT in order to fall back to other 99 * PMUs that might suffice the event request. 100 */ 101 ctrs_state = cpumf_ctr_ctl[hwc->config_base]; 102 if (!(ctrs_state & cpuhw->info.auth_ctl)) 103 err = -ENOENT; 104 105 put_cpu_var(cpu_cf_events); 106 return err; 107 } 108 109 /* 110 * Change the CPUMF state to active. 111 * Enable and activate the CPU-counter sets according 112 * to the per-cpu control state. 113 */ 114 static void cpumf_pmu_enable(struct pmu *pmu) 115 { 116 struct cpu_cf_events *cpuhw = this_cpu_ptr(&cpu_cf_events); 117 int err; 118 119 if (cpuhw->flags & PMU_F_ENABLED) 120 return; 121 122 err = lcctl(cpuhw->state); 123 if (err) { 124 pr_err("Enabling the performance measuring unit " 125 "failed with rc=%x\n", err); 126 return; 127 } 128 129 cpuhw->flags |= PMU_F_ENABLED; 130 } 131 132 /* 133 * Change the CPUMF state to inactive. 134 * Disable and enable (inactive) the CPU-counter sets according 135 * to the per-cpu control state. 136 */ 137 static void cpumf_pmu_disable(struct pmu *pmu) 138 { 139 struct cpu_cf_events *cpuhw = this_cpu_ptr(&cpu_cf_events); 140 int err; 141 u64 inactive; 142 143 if (!(cpuhw->flags & PMU_F_ENABLED)) 144 return; 145 146 inactive = cpuhw->state & ~((1 << CPUMF_LCCTL_ENABLE_SHIFT) - 1); 147 err = lcctl(inactive); 148 if (err) { 149 pr_err("Disabling the performance measuring unit " 150 "failed with rc=%x\n", err); 151 return; 152 } 153 154 cpuhw->flags &= ~PMU_F_ENABLED; 155 } 156 157 158 /* Number of perf events counting hardware events */ 159 static atomic_t num_events = ATOMIC_INIT(0); 160 /* Used to avoid races in calling reserve/release_cpumf_hardware */ 161 static DEFINE_MUTEX(pmc_reserve_mutex); 162 163 /* Release the PMU if event is the last perf event */ 164 static void hw_perf_event_destroy(struct perf_event *event) 165 { 166 if (!atomic_add_unless(&num_events, -1, 1)) { 167 mutex_lock(&pmc_reserve_mutex); 168 if (atomic_dec_return(&num_events) == 0) 169 __kernel_cpumcf_end(); 170 mutex_unlock(&pmc_reserve_mutex); 171 } 172 } 173 174 /* CPUMF <-> perf event mappings for kernel+userspace (basic set) */ 175 static const int cpumf_generic_events_basic[] = { 176 [PERF_COUNT_HW_CPU_CYCLES] = 0, 177 [PERF_COUNT_HW_INSTRUCTIONS] = 1, 178 [PERF_COUNT_HW_CACHE_REFERENCES] = -1, 179 [PERF_COUNT_HW_CACHE_MISSES] = -1, 180 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = -1, 181 [PERF_COUNT_HW_BRANCH_MISSES] = -1, 182 [PERF_COUNT_HW_BUS_CYCLES] = -1, 183 }; 184 /* CPUMF <-> perf event mappings for userspace (problem-state set) */ 185 static const int cpumf_generic_events_user[] = { 186 [PERF_COUNT_HW_CPU_CYCLES] = 32, 187 [PERF_COUNT_HW_INSTRUCTIONS] = 33, 188 [PERF_COUNT_HW_CACHE_REFERENCES] = -1, 189 [PERF_COUNT_HW_CACHE_MISSES] = -1, 190 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = -1, 191 [PERF_COUNT_HW_BRANCH_MISSES] = -1, 192 [PERF_COUNT_HW_BUS_CYCLES] = -1, 193 }; 194 195 static int __hw_perf_event_init(struct perf_event *event) 196 { 197 struct perf_event_attr *attr = &event->attr; 198 struct hw_perf_event *hwc = &event->hw; 199 enum cpumf_ctr_set set; 200 int err = 0; 201 u64 ev; 202 203 switch (attr->type) { 204 case PERF_TYPE_RAW: 205 /* Raw events are used to access counters directly, 206 * hence do not permit excludes */ 207 if (attr->exclude_kernel || attr->exclude_user || 208 attr->exclude_hv) 209 return -EOPNOTSUPP; 210 ev = attr->config; 211 break; 212 213 case PERF_TYPE_HARDWARE: 214 if (is_sampling_event(event)) /* No sampling support */ 215 return -ENOENT; 216 ev = attr->config; 217 /* Count user space (problem-state) only */ 218 if (!attr->exclude_user && attr->exclude_kernel) { 219 if (ev >= ARRAY_SIZE(cpumf_generic_events_user)) 220 return -EOPNOTSUPP; 221 ev = cpumf_generic_events_user[ev]; 222 223 /* No support for kernel space counters only */ 224 } else if (!attr->exclude_kernel && attr->exclude_user) { 225 return -EOPNOTSUPP; 226 227 /* Count user and kernel space */ 228 } else { 229 if (ev >= ARRAY_SIZE(cpumf_generic_events_basic)) 230 return -EOPNOTSUPP; 231 ev = cpumf_generic_events_basic[ev]; 232 } 233 break; 234 235 default: 236 return -ENOENT; 237 } 238 239 if (ev == -1) 240 return -ENOENT; 241 242 if (ev > PERF_CPUM_CF_MAX_CTR) 243 return -ENOENT; 244 245 /* Obtain the counter set to which the specified counter belongs */ 246 set = get_counter_set(ev); 247 switch (set) { 248 case CPUMF_CTR_SET_BASIC: 249 case CPUMF_CTR_SET_USER: 250 case CPUMF_CTR_SET_CRYPTO: 251 case CPUMF_CTR_SET_EXT: 252 case CPUMF_CTR_SET_MT_DIAG: 253 /* 254 * Use the hardware perf event structure to store the 255 * counter number in the 'config' member and the counter 256 * set number in the 'config_base'. The counter set number 257 * is then later used to enable/disable the counter(s). 258 */ 259 hwc->config = ev; 260 hwc->config_base = set; 261 break; 262 case CPUMF_CTR_SET_MAX: 263 /* The counter could not be associated to a counter set */ 264 return -EINVAL; 265 }; 266 267 /* Initialize for using the CPU-measurement counter facility */ 268 if (!atomic_inc_not_zero(&num_events)) { 269 mutex_lock(&pmc_reserve_mutex); 270 if (atomic_read(&num_events) == 0 && __kernel_cpumcf_begin()) 271 err = -EBUSY; 272 else 273 atomic_inc(&num_events); 274 mutex_unlock(&pmc_reserve_mutex); 275 } 276 if (err) 277 return err; 278 event->destroy = hw_perf_event_destroy; 279 280 /* Finally, validate version and authorization of the counter set */ 281 err = validate_ctr_auth(hwc); 282 if (!err) 283 err = validate_ctr_version(hwc); 284 285 return err; 286 } 287 288 static int cpumf_pmu_event_init(struct perf_event *event) 289 { 290 int err; 291 292 switch (event->attr.type) { 293 case PERF_TYPE_HARDWARE: 294 case PERF_TYPE_HW_CACHE: 295 case PERF_TYPE_RAW: 296 err = __hw_perf_event_init(event); 297 break; 298 default: 299 return -ENOENT; 300 } 301 302 if (unlikely(err) && event->destroy) 303 event->destroy(event); 304 305 return err; 306 } 307 308 static int hw_perf_event_reset(struct perf_event *event) 309 { 310 u64 prev, new; 311 int err; 312 313 do { 314 prev = local64_read(&event->hw.prev_count); 315 err = ecctr(event->hw.config, &new); 316 if (err) { 317 if (err != 3) 318 break; 319 /* The counter is not (yet) available. This 320 * might happen if the counter set to which 321 * this counter belongs is in the disabled 322 * state. 323 */ 324 new = 0; 325 } 326 } while (local64_cmpxchg(&event->hw.prev_count, prev, new) != prev); 327 328 return err; 329 } 330 331 static void hw_perf_event_update(struct perf_event *event) 332 { 333 u64 prev, new, delta; 334 int err; 335 336 do { 337 prev = local64_read(&event->hw.prev_count); 338 err = ecctr(event->hw.config, &new); 339 if (err) 340 return; 341 } while (local64_cmpxchg(&event->hw.prev_count, prev, new) != prev); 342 343 delta = (prev <= new) ? new - prev 344 : (-1ULL - prev) + new + 1; /* overflow */ 345 local64_add(delta, &event->count); 346 } 347 348 static void cpumf_pmu_read(struct perf_event *event) 349 { 350 if (event->hw.state & PERF_HES_STOPPED) 351 return; 352 353 hw_perf_event_update(event); 354 } 355 356 static void cpumf_pmu_start(struct perf_event *event, int flags) 357 { 358 struct cpu_cf_events *cpuhw = this_cpu_ptr(&cpu_cf_events); 359 struct hw_perf_event *hwc = &event->hw; 360 361 if (WARN_ON_ONCE(!(hwc->state & PERF_HES_STOPPED))) 362 return; 363 364 if (WARN_ON_ONCE(hwc->config == -1)) 365 return; 366 367 if (flags & PERF_EF_RELOAD) 368 WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE)); 369 370 hwc->state = 0; 371 372 /* (Re-)enable and activate the counter set */ 373 ctr_set_enable(&cpuhw->state, hwc->config_base); 374 ctr_set_start(&cpuhw->state, hwc->config_base); 375 376 /* The counter set to which this counter belongs can be already active. 377 * Because all counters in a set are active, the event->hw.prev_count 378 * needs to be synchronized. At this point, the counter set can be in 379 * the inactive or disabled state. 380 */ 381 hw_perf_event_reset(event); 382 383 /* increment refcount for this counter set */ 384 atomic_inc(&cpuhw->ctr_set[hwc->config_base]); 385 } 386 387 static void cpumf_pmu_stop(struct perf_event *event, int flags) 388 { 389 struct cpu_cf_events *cpuhw = this_cpu_ptr(&cpu_cf_events); 390 struct hw_perf_event *hwc = &event->hw; 391 392 if (!(hwc->state & PERF_HES_STOPPED)) { 393 /* Decrement reference count for this counter set and if this 394 * is the last used counter in the set, clear activation 395 * control and set the counter set state to inactive. 396 */ 397 if (!atomic_dec_return(&cpuhw->ctr_set[hwc->config_base])) 398 ctr_set_stop(&cpuhw->state, hwc->config_base); 399 event->hw.state |= PERF_HES_STOPPED; 400 } 401 402 if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) { 403 hw_perf_event_update(event); 404 event->hw.state |= PERF_HES_UPTODATE; 405 } 406 } 407 408 static int cpumf_pmu_add(struct perf_event *event, int flags) 409 { 410 struct cpu_cf_events *cpuhw = this_cpu_ptr(&cpu_cf_events); 411 412 /* Check authorization for the counter set to which this 413 * counter belongs. 414 * For group events transaction, the authorization check is 415 * done in cpumf_pmu_commit_txn(). 416 */ 417 if (!(cpuhw->txn_flags & PERF_PMU_TXN_ADD)) 418 if (validate_ctr_auth(&event->hw)) 419 return -ENOENT; 420 421 ctr_set_enable(&cpuhw->state, event->hw.config_base); 422 event->hw.state = PERF_HES_UPTODATE | PERF_HES_STOPPED; 423 424 if (flags & PERF_EF_START) 425 cpumf_pmu_start(event, PERF_EF_RELOAD); 426 427 perf_event_update_userpage(event); 428 429 return 0; 430 } 431 432 static void cpumf_pmu_del(struct perf_event *event, int flags) 433 { 434 struct cpu_cf_events *cpuhw = this_cpu_ptr(&cpu_cf_events); 435 436 cpumf_pmu_stop(event, PERF_EF_UPDATE); 437 438 /* Check if any counter in the counter set is still used. If not used, 439 * change the counter set to the disabled state. This also clears the 440 * content of all counters in the set. 441 * 442 * When a new perf event has been added but not yet started, this can 443 * clear enable control and resets all counters in a set. Therefore, 444 * cpumf_pmu_start() always has to reenable a counter set. 445 */ 446 if (!atomic_read(&cpuhw->ctr_set[event->hw.config_base])) 447 ctr_set_disable(&cpuhw->state, event->hw.config_base); 448 449 perf_event_update_userpage(event); 450 } 451 452 /* 453 * Start group events scheduling transaction. 454 * Set flags to perform a single test at commit time. 455 * 456 * We only support PERF_PMU_TXN_ADD transactions. Save the 457 * transaction flags but otherwise ignore non-PERF_PMU_TXN_ADD 458 * transactions. 459 */ 460 static void cpumf_pmu_start_txn(struct pmu *pmu, unsigned int txn_flags) 461 { 462 struct cpu_cf_events *cpuhw = this_cpu_ptr(&cpu_cf_events); 463 464 WARN_ON_ONCE(cpuhw->txn_flags); /* txn already in flight */ 465 466 cpuhw->txn_flags = txn_flags; 467 if (txn_flags & ~PERF_PMU_TXN_ADD) 468 return; 469 470 perf_pmu_disable(pmu); 471 cpuhw->tx_state = cpuhw->state; 472 } 473 474 /* 475 * Stop and cancel a group events scheduling tranctions. 476 * Assumes cpumf_pmu_del() is called for each successful added 477 * cpumf_pmu_add() during the transaction. 478 */ 479 static void cpumf_pmu_cancel_txn(struct pmu *pmu) 480 { 481 unsigned int txn_flags; 482 struct cpu_cf_events *cpuhw = this_cpu_ptr(&cpu_cf_events); 483 484 WARN_ON_ONCE(!cpuhw->txn_flags); /* no txn in flight */ 485 486 txn_flags = cpuhw->txn_flags; 487 cpuhw->txn_flags = 0; 488 if (txn_flags & ~PERF_PMU_TXN_ADD) 489 return; 490 491 WARN_ON(cpuhw->tx_state != cpuhw->state); 492 493 perf_pmu_enable(pmu); 494 } 495 496 /* 497 * Commit the group events scheduling transaction. On success, the 498 * transaction is closed. On error, the transaction is kept open 499 * until cpumf_pmu_cancel_txn() is called. 500 */ 501 static int cpumf_pmu_commit_txn(struct pmu *pmu) 502 { 503 struct cpu_cf_events *cpuhw = this_cpu_ptr(&cpu_cf_events); 504 u64 state; 505 506 WARN_ON_ONCE(!cpuhw->txn_flags); /* no txn in flight */ 507 508 if (cpuhw->txn_flags & ~PERF_PMU_TXN_ADD) { 509 cpuhw->txn_flags = 0; 510 return 0; 511 } 512 513 /* check if the updated state can be scheduled */ 514 state = cpuhw->state & ~((1 << CPUMF_LCCTL_ENABLE_SHIFT) - 1); 515 state >>= CPUMF_LCCTL_ENABLE_SHIFT; 516 if ((state & cpuhw->info.auth_ctl) != state) 517 return -ENOENT; 518 519 cpuhw->txn_flags = 0; 520 perf_pmu_enable(pmu); 521 return 0; 522 } 523 524 /* Performance monitoring unit for s390x */ 525 static struct pmu cpumf_pmu = { 526 .task_ctx_nr = perf_sw_context, 527 .capabilities = PERF_PMU_CAP_NO_INTERRUPT, 528 .pmu_enable = cpumf_pmu_enable, 529 .pmu_disable = cpumf_pmu_disable, 530 .event_init = cpumf_pmu_event_init, 531 .add = cpumf_pmu_add, 532 .del = cpumf_pmu_del, 533 .start = cpumf_pmu_start, 534 .stop = cpumf_pmu_stop, 535 .read = cpumf_pmu_read, 536 .start_txn = cpumf_pmu_start_txn, 537 .commit_txn = cpumf_pmu_commit_txn, 538 .cancel_txn = cpumf_pmu_cancel_txn, 539 }; 540 541 static int __init cpumf_pmu_init(void) 542 { 543 int rc; 544 545 if (!kernel_cpumcf_avail()) 546 return -ENODEV; 547 548 cpumf_pmu.attr_groups = cpumf_cf_event_group(); 549 rc = perf_pmu_register(&cpumf_pmu, "cpum_cf", PERF_TYPE_RAW); 550 if (rc) 551 pr_err("Registering the cpum_cf PMU failed with rc=%i\n", rc); 552 return rc; 553 } 554 subsys_initcall(cpumf_pmu_init); 555