1 /* 2 * Copyright IBM Corp. 2004, 2011 3 * Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>, 4 * Holger Smolinski <Holger.Smolinski@de.ibm.com>, 5 * Thomas Spatzier <tspat@de.ibm.com>, 6 * 7 * This file contains interrupt related functions. 8 */ 9 10 #include <linux/kernel_stat.h> 11 #include <linux/interrupt.h> 12 #include <linux/seq_file.h> 13 #include <linux/proc_fs.h> 14 #include <linux/profile.h> 15 #include <linux/module.h> 16 #include <linux/kernel.h> 17 #include <linux/ftrace.h> 18 #include <linux/errno.h> 19 #include <linux/slab.h> 20 #include <linux/cpu.h> 21 #include <linux/irq.h> 22 #include <asm/irq_regs.h> 23 #include <asm/cputime.h> 24 #include <asm/lowcore.h> 25 #include <asm/irq.h> 26 #include <asm/hw_irq.h> 27 #include "entry.h" 28 29 DEFINE_PER_CPU_SHARED_ALIGNED(struct irq_stat, irq_stat); 30 EXPORT_PER_CPU_SYMBOL_GPL(irq_stat); 31 32 struct irq_class { 33 int irq; 34 char *name; 35 char *desc; 36 }; 37 38 /* 39 * The list of "main" irq classes on s390. This is the list of interrupts 40 * that appear both in /proc/stat ("intr" line) and /proc/interrupts. 41 * Historically only external and I/O interrupts have been part of /proc/stat. 42 * We can't add the split external and I/O sub classes since the first field 43 * in the "intr" line in /proc/stat is supposed to be the sum of all other 44 * fields. 45 * Since the external and I/O interrupt fields are already sums we would end 46 * up with having a sum which accounts each interrupt twice. 47 */ 48 static const struct irq_class irqclass_main_desc[NR_IRQS_BASE] = { 49 {.irq = EXT_INTERRUPT, .name = "EXT"}, 50 {.irq = IO_INTERRUPT, .name = "I/O"}, 51 {.irq = THIN_INTERRUPT, .name = "AIO"}, 52 }; 53 54 /* 55 * The list of split external and I/O interrupts that appear only in 56 * /proc/interrupts. 57 * In addition this list contains non external / I/O events like NMIs. 58 */ 59 static const struct irq_class irqclass_sub_desc[NR_ARCH_IRQS] = { 60 {.irq = IRQEXT_CLK, .name = "CLK", .desc = "[EXT] Clock Comparator"}, 61 {.irq = IRQEXT_EXC, .name = "EXC", .desc = "[EXT] External Call"}, 62 {.irq = IRQEXT_EMS, .name = "EMS", .desc = "[EXT] Emergency Signal"}, 63 {.irq = IRQEXT_TMR, .name = "TMR", .desc = "[EXT] CPU Timer"}, 64 {.irq = IRQEXT_TLA, .name = "TAL", .desc = "[EXT] Timing Alert"}, 65 {.irq = IRQEXT_PFL, .name = "PFL", .desc = "[EXT] Pseudo Page Fault"}, 66 {.irq = IRQEXT_DSD, .name = "DSD", .desc = "[EXT] DASD Diag"}, 67 {.irq = IRQEXT_VRT, .name = "VRT", .desc = "[EXT] Virtio"}, 68 {.irq = IRQEXT_SCP, .name = "SCP", .desc = "[EXT] Service Call"}, 69 {.irq = IRQEXT_IUC, .name = "IUC", .desc = "[EXT] IUCV"}, 70 {.irq = IRQEXT_CMS, .name = "CMS", .desc = "[EXT] CPU-Measurement: Sampling"}, 71 {.irq = IRQEXT_CMC, .name = "CMC", .desc = "[EXT] CPU-Measurement: Counter"}, 72 {.irq = IRQEXT_CMR, .name = "CMR", .desc = "[EXT] CPU-Measurement: RI"}, 73 {.irq = IRQEXT_FTP, .name = "FTP", .desc = "[EXT] HMC FTP Service"}, 74 {.irq = IRQIO_CIO, .name = "CIO", .desc = "[I/O] Common I/O Layer Interrupt"}, 75 {.irq = IRQIO_QAI, .name = "QAI", .desc = "[I/O] QDIO Adapter Interrupt"}, 76 {.irq = IRQIO_DAS, .name = "DAS", .desc = "[I/O] DASD"}, 77 {.irq = IRQIO_C15, .name = "C15", .desc = "[I/O] 3215"}, 78 {.irq = IRQIO_C70, .name = "C70", .desc = "[I/O] 3270"}, 79 {.irq = IRQIO_TAP, .name = "TAP", .desc = "[I/O] Tape"}, 80 {.irq = IRQIO_VMR, .name = "VMR", .desc = "[I/O] Unit Record Devices"}, 81 {.irq = IRQIO_LCS, .name = "LCS", .desc = "[I/O] LCS"}, 82 {.irq = IRQIO_CLW, .name = "CLW", .desc = "[I/O] CLAW"}, 83 {.irq = IRQIO_CTC, .name = "CTC", .desc = "[I/O] CTC"}, 84 {.irq = IRQIO_APB, .name = "APB", .desc = "[I/O] AP Bus"}, 85 {.irq = IRQIO_ADM, .name = "ADM", .desc = "[I/O] EADM Subchannel"}, 86 {.irq = IRQIO_CSC, .name = "CSC", .desc = "[I/O] CHSC Subchannel"}, 87 {.irq = IRQIO_PCI, .name = "PCI", .desc = "[I/O] PCI Interrupt" }, 88 {.irq = IRQIO_MSI, .name = "MSI", .desc = "[I/O] MSI Interrupt" }, 89 {.irq = IRQIO_VIR, .name = "VIR", .desc = "[I/O] Virtual I/O Devices"}, 90 {.irq = IRQIO_VAI, .name = "VAI", .desc = "[I/O] Virtual I/O Devices AI"}, 91 {.irq = NMI_NMI, .name = "NMI", .desc = "[NMI] Machine Check"}, 92 {.irq = CPU_RST, .name = "RST", .desc = "[CPU] CPU Restart"}, 93 }; 94 95 void __init init_IRQ(void) 96 { 97 init_cio_interrupts(); 98 init_airq_interrupts(); 99 init_ext_interrupts(); 100 } 101 102 void do_IRQ(struct pt_regs *regs, int irq) 103 { 104 struct pt_regs *old_regs; 105 106 old_regs = set_irq_regs(regs); 107 irq_enter(); 108 if (S390_lowcore.int_clock >= S390_lowcore.clock_comparator) 109 /* Serve timer interrupts first. */ 110 clock_comparator_work(); 111 generic_handle_irq(irq); 112 irq_exit(); 113 set_irq_regs(old_regs); 114 } 115 116 /* 117 * show_interrupts is needed by /proc/interrupts. 118 */ 119 int show_interrupts(struct seq_file *p, void *v) 120 { 121 int index = *(loff_t *) v; 122 int cpu, irq; 123 124 get_online_cpus(); 125 if (index == 0) { 126 seq_puts(p, " "); 127 for_each_online_cpu(cpu) 128 seq_printf(p, "CPU%d ", cpu); 129 seq_putc(p, '\n'); 130 } 131 if (index < NR_IRQS) { 132 if (index >= NR_IRQS_BASE) 133 goto out; 134 seq_printf(p, "%s: ", irqclass_main_desc[index].name); 135 irq = irqclass_main_desc[index].irq; 136 for_each_online_cpu(cpu) 137 seq_printf(p, "%10u ", kstat_irqs_cpu(irq, cpu)); 138 seq_putc(p, '\n'); 139 goto out; 140 } 141 for (index = 0; index < NR_ARCH_IRQS; index++) { 142 seq_printf(p, "%s: ", irqclass_sub_desc[index].name); 143 irq = irqclass_sub_desc[index].irq; 144 for_each_online_cpu(cpu) 145 seq_printf(p, "%10u ", 146 per_cpu(irq_stat, cpu).irqs[irq]); 147 if (irqclass_sub_desc[index].desc) 148 seq_printf(p, " %s", irqclass_sub_desc[index].desc); 149 seq_putc(p, '\n'); 150 } 151 out: 152 put_online_cpus(); 153 return 0; 154 } 155 156 unsigned int arch_dynirq_lower_bound(unsigned int from) 157 { 158 return from < NR_IRQS_BASE ? NR_IRQS_BASE : from; 159 } 160 161 /* 162 * Switch to the asynchronous interrupt stack for softirq execution. 163 */ 164 void do_softirq_own_stack(void) 165 { 166 unsigned long old, new; 167 168 /* Get current stack pointer. */ 169 asm volatile("la %0,0(15)" : "=a" (old)); 170 /* Check against async. stack address range. */ 171 new = S390_lowcore.async_stack; 172 if (((new - old) >> (PAGE_SHIFT + THREAD_ORDER)) != 0) { 173 /* Need to switch to the async. stack. */ 174 new -= STACK_FRAME_OVERHEAD; 175 ((struct stack_frame *) new)->back_chain = old; 176 asm volatile(" la 15,0(%0)\n" 177 " basr 14,%2\n" 178 " la 15,0(%1)\n" 179 : : "a" (new), "a" (old), 180 "a" (__do_softirq) 181 : "0", "1", "2", "3", "4", "5", "14", 182 "cc", "memory" ); 183 } else { 184 /* We are already on the async stack. */ 185 __do_softirq(); 186 } 187 } 188 189 /* 190 * ext_int_hash[index] is the list head for all external interrupts that hash 191 * to this index. 192 */ 193 static struct hlist_head ext_int_hash[32] ____cacheline_aligned; 194 195 struct ext_int_info { 196 ext_int_handler_t handler; 197 struct hlist_node entry; 198 struct rcu_head rcu; 199 u16 code; 200 }; 201 202 /* ext_int_hash_lock protects the handler lists for external interrupts */ 203 static DEFINE_SPINLOCK(ext_int_hash_lock); 204 205 static inline int ext_hash(u16 code) 206 { 207 BUILD_BUG_ON(!is_power_of_2(ARRAY_SIZE(ext_int_hash))); 208 209 return (code + (code >> 9)) & (ARRAY_SIZE(ext_int_hash) - 1); 210 } 211 212 int register_external_irq(u16 code, ext_int_handler_t handler) 213 { 214 struct ext_int_info *p; 215 unsigned long flags; 216 int index; 217 218 p = kmalloc(sizeof(*p), GFP_ATOMIC); 219 if (!p) 220 return -ENOMEM; 221 p->code = code; 222 p->handler = handler; 223 index = ext_hash(code); 224 225 spin_lock_irqsave(&ext_int_hash_lock, flags); 226 hlist_add_head_rcu(&p->entry, &ext_int_hash[index]); 227 spin_unlock_irqrestore(&ext_int_hash_lock, flags); 228 return 0; 229 } 230 EXPORT_SYMBOL(register_external_irq); 231 232 int unregister_external_irq(u16 code, ext_int_handler_t handler) 233 { 234 struct ext_int_info *p; 235 unsigned long flags; 236 int index = ext_hash(code); 237 238 spin_lock_irqsave(&ext_int_hash_lock, flags); 239 hlist_for_each_entry_rcu(p, &ext_int_hash[index], entry) { 240 if (p->code == code && p->handler == handler) { 241 hlist_del_rcu(&p->entry); 242 kfree_rcu(p, rcu); 243 } 244 } 245 spin_unlock_irqrestore(&ext_int_hash_lock, flags); 246 return 0; 247 } 248 EXPORT_SYMBOL(unregister_external_irq); 249 250 static irqreturn_t do_ext_interrupt(int irq, void *dummy) 251 { 252 struct pt_regs *regs = get_irq_regs(); 253 struct ext_code ext_code; 254 struct ext_int_info *p; 255 int index; 256 257 ext_code = *(struct ext_code *) ®s->int_code; 258 if (ext_code.code != EXT_IRQ_CLK_COMP) 259 set_cpu_flag(CIF_NOHZ_DELAY); 260 261 index = ext_hash(ext_code.code); 262 rcu_read_lock(); 263 hlist_for_each_entry_rcu(p, &ext_int_hash[index], entry) { 264 if (unlikely(p->code != ext_code.code)) 265 continue; 266 p->handler(ext_code, regs->int_parm, regs->int_parm_long); 267 } 268 rcu_read_unlock(); 269 return IRQ_HANDLED; 270 } 271 272 static struct irqaction external_interrupt = { 273 .name = "EXT", 274 .handler = do_ext_interrupt, 275 }; 276 277 void __init init_ext_interrupts(void) 278 { 279 int idx; 280 281 for (idx = 0; idx < ARRAY_SIZE(ext_int_hash); idx++) 282 INIT_HLIST_HEAD(&ext_int_hash[idx]); 283 284 irq_set_chip_and_handler(EXT_INTERRUPT, 285 &dummy_irq_chip, handle_percpu_irq); 286 setup_irq(EXT_INTERRUPT, &external_interrupt); 287 } 288 289 static DEFINE_SPINLOCK(irq_subclass_lock); 290 static unsigned char irq_subclass_refcount[64]; 291 292 void irq_subclass_register(enum irq_subclass subclass) 293 { 294 spin_lock(&irq_subclass_lock); 295 if (!irq_subclass_refcount[subclass]) 296 ctl_set_bit(0, subclass); 297 irq_subclass_refcount[subclass]++; 298 spin_unlock(&irq_subclass_lock); 299 } 300 EXPORT_SYMBOL(irq_subclass_register); 301 302 void irq_subclass_unregister(enum irq_subclass subclass) 303 { 304 spin_lock(&irq_subclass_lock); 305 irq_subclass_refcount[subclass]--; 306 if (!irq_subclass_refcount[subclass]) 307 ctl_clear_bit(0, subclass); 308 spin_unlock(&irq_subclass_lock); 309 } 310 EXPORT_SYMBOL(irq_subclass_unregister); 311