1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright IBM Corp. 2004, 2011 4 * Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>, 5 * Holger Smolinski <Holger.Smolinski@de.ibm.com>, 6 * Thomas Spatzier <tspat@de.ibm.com>, 7 * 8 * This file contains interrupt related functions. 9 */ 10 11 #include <linux/kernel_stat.h> 12 #include <linux/interrupt.h> 13 #include <linux/seq_file.h> 14 #include <linux/proc_fs.h> 15 #include <linux/profile.h> 16 #include <linux/export.h> 17 #include <linux/kernel.h> 18 #include <linux/ftrace.h> 19 #include <linux/errno.h> 20 #include <linux/slab.h> 21 #include <linux/init.h> 22 #include <linux/cpu.h> 23 #include <linux/irq.h> 24 #include <linux/entry-common.h> 25 #include <asm/irq_regs.h> 26 #include <asm/cputime.h> 27 #include <asm/lowcore.h> 28 #include <asm/irq.h> 29 #include <asm/hw_irq.h> 30 #include <asm/stacktrace.h> 31 #include <asm/softirq_stack.h> 32 #include "entry.h" 33 34 DEFINE_PER_CPU_SHARED_ALIGNED(struct irq_stat, irq_stat); 35 EXPORT_PER_CPU_SYMBOL_GPL(irq_stat); 36 37 struct irq_class { 38 int irq; 39 char *name; 40 char *desc; 41 }; 42 43 /* 44 * The list of "main" irq classes on s390. This is the list of interrupts 45 * that appear both in /proc/stat ("intr" line) and /proc/interrupts. 46 * Historically only external and I/O interrupts have been part of /proc/stat. 47 * We can't add the split external and I/O sub classes since the first field 48 * in the "intr" line in /proc/stat is supposed to be the sum of all other 49 * fields. 50 * Since the external and I/O interrupt fields are already sums we would end 51 * up with having a sum which accounts each interrupt twice. 52 */ 53 static const struct irq_class irqclass_main_desc[NR_IRQS_BASE] = { 54 {.irq = EXT_INTERRUPT, .name = "EXT"}, 55 {.irq = IO_INTERRUPT, .name = "I/O"}, 56 {.irq = THIN_INTERRUPT, .name = "AIO"}, 57 }; 58 59 /* 60 * The list of split external and I/O interrupts that appear only in 61 * /proc/interrupts. 62 * In addition this list contains non external / I/O events like NMIs. 63 */ 64 static const struct irq_class irqclass_sub_desc[] = { 65 {.irq = IRQEXT_CLK, .name = "CLK", .desc = "[EXT] Clock Comparator"}, 66 {.irq = IRQEXT_EXC, .name = "EXC", .desc = "[EXT] External Call"}, 67 {.irq = IRQEXT_EMS, .name = "EMS", .desc = "[EXT] Emergency Signal"}, 68 {.irq = IRQEXT_TMR, .name = "TMR", .desc = "[EXT] CPU Timer"}, 69 {.irq = IRQEXT_TLA, .name = "TAL", .desc = "[EXT] Timing Alert"}, 70 {.irq = IRQEXT_PFL, .name = "PFL", .desc = "[EXT] Pseudo Page Fault"}, 71 {.irq = IRQEXT_DSD, .name = "DSD", .desc = "[EXT] DASD Diag"}, 72 {.irq = IRQEXT_VRT, .name = "VRT", .desc = "[EXT] Virtio"}, 73 {.irq = IRQEXT_SCP, .name = "SCP", .desc = "[EXT] Service Call"}, 74 {.irq = IRQEXT_IUC, .name = "IUC", .desc = "[EXT] IUCV"}, 75 {.irq = IRQEXT_CMS, .name = "CMS", .desc = "[EXT] CPU-Measurement: Sampling"}, 76 {.irq = IRQEXT_CMC, .name = "CMC", .desc = "[EXT] CPU-Measurement: Counter"}, 77 {.irq = IRQEXT_FTP, .name = "FTP", .desc = "[EXT] HMC FTP Service"}, 78 {.irq = IRQIO_CIO, .name = "CIO", .desc = "[I/O] Common I/O Layer Interrupt"}, 79 {.irq = IRQIO_DAS, .name = "DAS", .desc = "[I/O] DASD"}, 80 {.irq = IRQIO_C15, .name = "C15", .desc = "[I/O] 3215"}, 81 {.irq = IRQIO_C70, .name = "C70", .desc = "[I/O] 3270"}, 82 {.irq = IRQIO_TAP, .name = "TAP", .desc = "[I/O] Tape"}, 83 {.irq = IRQIO_VMR, .name = "VMR", .desc = "[I/O] Unit Record Devices"}, 84 {.irq = IRQIO_LCS, .name = "LCS", .desc = "[I/O] LCS"}, 85 {.irq = IRQIO_CTC, .name = "CTC", .desc = "[I/O] CTC"}, 86 {.irq = IRQIO_ADM, .name = "ADM", .desc = "[I/O] EADM Subchannel"}, 87 {.irq = IRQIO_CSC, .name = "CSC", .desc = "[I/O] CHSC Subchannel"}, 88 {.irq = IRQIO_VIR, .name = "VIR", .desc = "[I/O] Virtual I/O Devices"}, 89 {.irq = IRQIO_QAI, .name = "QAI", .desc = "[AIO] QDIO Adapter Interrupt"}, 90 {.irq = IRQIO_APB, .name = "APB", .desc = "[AIO] AP Bus"}, 91 {.irq = IRQIO_PCF, .name = "PCF", .desc = "[AIO] PCI Floating Interrupt"}, 92 {.irq = IRQIO_PCD, .name = "PCD", .desc = "[AIO] PCI Directed Interrupt"}, 93 {.irq = IRQIO_MSI, .name = "MSI", .desc = "[AIO] MSI Interrupt"}, 94 {.irq = IRQIO_VAI, .name = "VAI", .desc = "[AIO] Virtual I/O Devices AI"}, 95 {.irq = IRQIO_GAL, .name = "GAL", .desc = "[AIO] GIB Alert"}, 96 {.irq = NMI_NMI, .name = "NMI", .desc = "[NMI] Machine Check"}, 97 {.irq = CPU_RST, .name = "RST", .desc = "[CPU] CPU Restart"}, 98 }; 99 100 static void do_IRQ(struct pt_regs *regs, int irq) 101 { 102 if (tod_after_eq(S390_lowcore.int_clock, 103 S390_lowcore.clock_comparator)) 104 /* Serve timer interrupts first. */ 105 clock_comparator_work(); 106 generic_handle_irq(irq); 107 } 108 109 static int on_async_stack(void) 110 { 111 unsigned long frame = current_frame_address(); 112 113 return ((S390_lowcore.async_stack ^ frame) & ~(THREAD_SIZE - 1)) == 0; 114 } 115 116 static void do_irq_async(struct pt_regs *regs, int irq) 117 { 118 if (on_async_stack()) { 119 do_IRQ(regs, irq); 120 } else { 121 call_on_stack(2, S390_lowcore.async_stack, void, do_IRQ, 122 struct pt_regs *, regs, int, irq); 123 } 124 } 125 126 static int irq_pending(struct pt_regs *regs) 127 { 128 int cc; 129 130 asm volatile("tpi 0\n" 131 "ipm %0" : "=d" (cc) : : "cc"); 132 return cc >> 28; 133 } 134 135 void noinstr do_io_irq(struct pt_regs *regs) 136 { 137 irqentry_state_t state = irqentry_enter(regs); 138 struct pt_regs *old_regs = set_irq_regs(regs); 139 int from_idle; 140 141 irq_enter(); 142 143 if (user_mode(regs)) 144 update_timer_sys(); 145 146 from_idle = !user_mode(regs) && regs->psw.addr == (unsigned long)psw_idle_exit; 147 if (from_idle) 148 account_idle_time_irq(); 149 150 do { 151 regs->tpi_info = S390_lowcore.tpi_info; 152 if (S390_lowcore.tpi_info.adapter_IO) 153 do_irq_async(regs, THIN_INTERRUPT); 154 else 155 do_irq_async(regs, IO_INTERRUPT); 156 } while (MACHINE_IS_LPAR && irq_pending(regs)); 157 158 irq_exit(); 159 set_irq_regs(old_regs); 160 irqentry_exit(regs, state); 161 162 if (from_idle) 163 regs->psw.mask &= ~(PSW_MASK_EXT | PSW_MASK_IO | PSW_MASK_WAIT); 164 } 165 166 void noinstr do_ext_irq(struct pt_regs *regs) 167 { 168 irqentry_state_t state = irqentry_enter(regs); 169 struct pt_regs *old_regs = set_irq_regs(regs); 170 int from_idle; 171 172 irq_enter(); 173 174 if (user_mode(regs)) 175 update_timer_sys(); 176 177 regs->int_code = S390_lowcore.ext_int_code_addr; 178 regs->int_parm = S390_lowcore.ext_params; 179 regs->int_parm_long = S390_lowcore.ext_params2; 180 181 from_idle = !user_mode(regs) && regs->psw.addr == (unsigned long)psw_idle_exit; 182 if (from_idle) 183 account_idle_time_irq(); 184 185 do_irq_async(regs, EXT_INTERRUPT); 186 187 irq_exit(); 188 set_irq_regs(old_regs); 189 irqentry_exit(regs, state); 190 191 if (from_idle) 192 regs->psw.mask &= ~(PSW_MASK_EXT | PSW_MASK_IO | PSW_MASK_WAIT); 193 } 194 195 static void show_msi_interrupt(struct seq_file *p, int irq) 196 { 197 struct irq_desc *desc; 198 unsigned long flags; 199 int cpu; 200 201 irq_lock_sparse(); 202 desc = irq_to_desc(irq); 203 if (!desc) 204 goto out; 205 206 raw_spin_lock_irqsave(&desc->lock, flags); 207 seq_printf(p, "%3d: ", irq); 208 for_each_online_cpu(cpu) 209 seq_printf(p, "%10u ", irq_desc_kstat_cpu(desc, cpu)); 210 211 if (desc->irq_data.chip) 212 seq_printf(p, " %8s", desc->irq_data.chip->name); 213 214 if (desc->action) 215 seq_printf(p, " %s", desc->action->name); 216 217 seq_putc(p, '\n'); 218 raw_spin_unlock_irqrestore(&desc->lock, flags); 219 out: 220 irq_unlock_sparse(); 221 } 222 223 /* 224 * show_interrupts is needed by /proc/interrupts. 225 */ 226 int show_interrupts(struct seq_file *p, void *v) 227 { 228 int index = *(loff_t *) v; 229 int cpu, irq; 230 231 get_online_cpus(); 232 if (index == 0) { 233 seq_puts(p, " "); 234 for_each_online_cpu(cpu) 235 seq_printf(p, "CPU%-8d", cpu); 236 seq_putc(p, '\n'); 237 } 238 if (index < NR_IRQS_BASE) { 239 seq_printf(p, "%s: ", irqclass_main_desc[index].name); 240 irq = irqclass_main_desc[index].irq; 241 for_each_online_cpu(cpu) 242 seq_printf(p, "%10u ", kstat_irqs_cpu(irq, cpu)); 243 seq_putc(p, '\n'); 244 goto out; 245 } 246 if (index < nr_irqs) { 247 show_msi_interrupt(p, index); 248 goto out; 249 } 250 for (index = 0; index < NR_ARCH_IRQS; index++) { 251 seq_printf(p, "%s: ", irqclass_sub_desc[index].name); 252 irq = irqclass_sub_desc[index].irq; 253 for_each_online_cpu(cpu) 254 seq_printf(p, "%10u ", 255 per_cpu(irq_stat, cpu).irqs[irq]); 256 if (irqclass_sub_desc[index].desc) 257 seq_printf(p, " %s", irqclass_sub_desc[index].desc); 258 seq_putc(p, '\n'); 259 } 260 out: 261 put_online_cpus(); 262 return 0; 263 } 264 265 unsigned int arch_dynirq_lower_bound(unsigned int from) 266 { 267 return from < NR_IRQS_BASE ? NR_IRQS_BASE : from; 268 } 269 270 /* 271 * ext_int_hash[index] is the list head for all external interrupts that hash 272 * to this index. 273 */ 274 static struct hlist_head ext_int_hash[32] ____cacheline_aligned; 275 276 struct ext_int_info { 277 ext_int_handler_t handler; 278 struct hlist_node entry; 279 struct rcu_head rcu; 280 u16 code; 281 }; 282 283 /* ext_int_hash_lock protects the handler lists for external interrupts */ 284 static DEFINE_SPINLOCK(ext_int_hash_lock); 285 286 static inline int ext_hash(u16 code) 287 { 288 BUILD_BUG_ON(!is_power_of_2(ARRAY_SIZE(ext_int_hash))); 289 290 return (code + (code >> 9)) & (ARRAY_SIZE(ext_int_hash) - 1); 291 } 292 293 int register_external_irq(u16 code, ext_int_handler_t handler) 294 { 295 struct ext_int_info *p; 296 unsigned long flags; 297 int index; 298 299 p = kmalloc(sizeof(*p), GFP_ATOMIC); 300 if (!p) 301 return -ENOMEM; 302 p->code = code; 303 p->handler = handler; 304 index = ext_hash(code); 305 306 spin_lock_irqsave(&ext_int_hash_lock, flags); 307 hlist_add_head_rcu(&p->entry, &ext_int_hash[index]); 308 spin_unlock_irqrestore(&ext_int_hash_lock, flags); 309 return 0; 310 } 311 EXPORT_SYMBOL(register_external_irq); 312 313 int unregister_external_irq(u16 code, ext_int_handler_t handler) 314 { 315 struct ext_int_info *p; 316 unsigned long flags; 317 int index = ext_hash(code); 318 319 spin_lock_irqsave(&ext_int_hash_lock, flags); 320 hlist_for_each_entry_rcu(p, &ext_int_hash[index], entry) { 321 if (p->code == code && p->handler == handler) { 322 hlist_del_rcu(&p->entry); 323 kfree_rcu(p, rcu); 324 } 325 } 326 spin_unlock_irqrestore(&ext_int_hash_lock, flags); 327 return 0; 328 } 329 EXPORT_SYMBOL(unregister_external_irq); 330 331 static irqreturn_t do_ext_interrupt(int irq, void *dummy) 332 { 333 struct pt_regs *regs = get_irq_regs(); 334 struct ext_code ext_code; 335 struct ext_int_info *p; 336 int index; 337 338 ext_code = *(struct ext_code *) ®s->int_code; 339 if (ext_code.code != EXT_IRQ_CLK_COMP) 340 set_cpu_flag(CIF_NOHZ_DELAY); 341 342 index = ext_hash(ext_code.code); 343 rcu_read_lock(); 344 hlist_for_each_entry_rcu(p, &ext_int_hash[index], entry) { 345 if (unlikely(p->code != ext_code.code)) 346 continue; 347 p->handler(ext_code, regs->int_parm, regs->int_parm_long); 348 } 349 rcu_read_unlock(); 350 return IRQ_HANDLED; 351 } 352 353 static void __init init_ext_interrupts(void) 354 { 355 int idx; 356 357 for (idx = 0; idx < ARRAY_SIZE(ext_int_hash); idx++) 358 INIT_HLIST_HEAD(&ext_int_hash[idx]); 359 360 irq_set_chip_and_handler(EXT_INTERRUPT, 361 &dummy_irq_chip, handle_percpu_irq); 362 if (request_irq(EXT_INTERRUPT, do_ext_interrupt, 0, "EXT", NULL)) 363 panic("Failed to register EXT interrupt\n"); 364 } 365 366 void __init init_IRQ(void) 367 { 368 BUILD_BUG_ON(ARRAY_SIZE(irqclass_sub_desc) != NR_ARCH_IRQS); 369 init_cio_interrupts(); 370 init_airq_interrupts(); 371 init_ext_interrupts(); 372 } 373 374 static DEFINE_SPINLOCK(irq_subclass_lock); 375 static unsigned char irq_subclass_refcount[64]; 376 377 void irq_subclass_register(enum irq_subclass subclass) 378 { 379 spin_lock(&irq_subclass_lock); 380 if (!irq_subclass_refcount[subclass]) 381 ctl_set_bit(0, subclass); 382 irq_subclass_refcount[subclass]++; 383 spin_unlock(&irq_subclass_lock); 384 } 385 EXPORT_SYMBOL(irq_subclass_register); 386 387 void irq_subclass_unregister(enum irq_subclass subclass) 388 { 389 spin_lock(&irq_subclass_lock); 390 irq_subclass_refcount[subclass]--; 391 if (!irq_subclass_refcount[subclass]) 392 ctl_clear_bit(0, subclass); 393 spin_unlock(&irq_subclass_lock); 394 } 395 EXPORT_SYMBOL(irq_subclass_unregister); 396