1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright IBM Corp. 1999, 2010 4 * 5 * Author(s): Hartmut Penner <hp@de.ibm.com> 6 * Martin Schwidefsky <schwidefsky@de.ibm.com> 7 * Rob van der Heij <rvdhei@iae.nl> 8 * Heiko Carstens <heiko.carstens@de.ibm.com> 9 * 10 */ 11 12#include <linux/init.h> 13#include <linux/linkage.h> 14#include <asm/asm-offsets.h> 15#include <asm/thread_info.h> 16#include <asm/page.h> 17#include <asm/ptrace.h> 18 19__HEAD 20ENTRY(startup_continue) 21 tm __LC_STFLE_FAC_LIST+5,0x80 # LPP available ? 22 jz 0f 23 xc __LC_LPP+1(7,0),__LC_LPP+1 # clear lpp and current_pid 24 mvi __LC_LPP,0x80 # and set LPP_MAGIC 25 .insn s,0xb2800000,__LC_LPP # load program parameter 260: larl %r1,tod_clock_base 27 mvc 0(16,%r1),__LC_BOOT_CLOCK 28 larl %r13,.LPG1 # get base 29 lctlg %c0,%c15,.Lctl-.LPG1(%r13) # load control registers 30 lg %r12,.Lparmaddr-.LPG1(%r13) # pointer to parameter area 31 # move IPL device to lowcore 32 larl %r0,boot_vdso_data 33 stg %r0,__LC_VDSO_PER_CPU 34# 35# Setup stack 36# 37 larl %r14,init_task 38 stg %r14,__LC_CURRENT 39 larl %r15,init_thread_union+THREAD_SIZE-STACK_FRAME_OVERHEAD 40# 41# Early setup functions that may not rely on an initialized bss section, 42# like moving the initrd. Returns with an initialized bss section. 43# 44 brasl %r14,startup_init_nobss 45# 46# Early machine initialization and detection functions. 47# 48 brasl %r14,startup_init 49 50# check control registers 51 stctg %c0,%c15,0(%r15) 52 oi 6(%r15),0x60 # enable sigp emergency & external call 53 oi 4(%r15),0x10 # switch on low address proctection 54 lctlg %c0,%c15,0(%r15) 55 56 lam 0,15,.Laregs-.LPG1(%r13) # load acrs needed by uaccess 57 brasl %r14,start_kernel # go to C code 58# 59# We returned from start_kernel ?!? PANIK 60# 61 basr %r13,0 62 lpswe .Ldw-.(%r13) # load disabled wait psw 63 64 .align 16 65.LPG1: 66.Lctl: .quad 0x04040000 # cr0: AFP registers & secondary space 67 .quad 0 # cr1: primary space segment table 68 .quad .Lduct # cr2: dispatchable unit control table 69 .quad 0 # cr3: instruction authorization 70 .quad 0xffff # cr4: instruction authorization 71 .quad .Lduct # cr5: primary-aste origin 72 .quad 0 # cr6: I/O interrupts 73 .quad 0 # cr7: secondary space segment table 74 .quad 0 # cr8: access registers translation 75 .quad 0 # cr9: tracing off 76 .quad 0 # cr10: tracing off 77 .quad 0 # cr11: tracing off 78 .quad 0 # cr12: tracing off 79 .quad 0 # cr13: home space segment table 80 .quad 0xc0000000 # cr14: machine check handling off 81 .quad .Llinkage_stack # cr15: linkage stack operations 82.Lpcmsk:.quad 0x0000000180000000 83.L4malign:.quad 0xffffffffffc00000 84.Lscan2g:.quad 0x80000000 + 0x20000 - 8 # 2GB + 128K - 8 85.Lnop: .long 0x07000700 86.Lparmaddr: 87 .quad PARMAREA 88 .align 64 89.Lduct: .long 0,.Laste,.Laste,0,.Lduald,0,0,0 90 .long 0,0,0,0,0,0,0,0 91.Laste: .quad 0,0xffffffffffffffff,0,0,0,0,0,0 92 .align 128 93.Lduald:.rept 8 94 .long 0x80000000,0,0,0 # invalid access-list entries 95 .endr 96.Llinkage_stack: 97 .long 0,0,0x89000000,0,0,0,0x8a000000,0 98.Ldw: .quad 0x0002000180000000,0x0000000000000000 99.Laregs:.long 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 100