xref: /openbmc/linux/arch/s390/kernel/entry.S (revision ddc141e5) 
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 *    S390 low-level entry points.
4 *
5 *    Copyright IBM Corp. 1999, 2012
6 *    Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com),
7 *		 Hartmut Penner (hp@de.ibm.com),
8 *		 Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com),
9 *		 Heiko Carstens <heiko.carstens@de.ibm.com>
10 */
11
12#include <linux/init.h>
13#include <linux/linkage.h>
14#include <asm/processor.h>
15#include <asm/cache.h>
16#include <asm/ctl_reg.h>
17#include <asm/errno.h>
18#include <asm/ptrace.h>
19#include <asm/thread_info.h>
20#include <asm/asm-offsets.h>
21#include <asm/unistd.h>
22#include <asm/page.h>
23#include <asm/sigp.h>
24#include <asm/irq.h>
25#include <asm/vx-insn.h>
26#include <asm/setup.h>
27#include <asm/nmi.h>
28#include <asm/export.h>
29
30__PT_R0      =	__PT_GPRS
31__PT_R1      =	__PT_GPRS + 8
32__PT_R2      =	__PT_GPRS + 16
33__PT_R3      =	__PT_GPRS + 24
34__PT_R4      =	__PT_GPRS + 32
35__PT_R5      =	__PT_GPRS + 40
36__PT_R6      =	__PT_GPRS + 48
37__PT_R7      =	__PT_GPRS + 56
38__PT_R8      =	__PT_GPRS + 64
39__PT_R9      =	__PT_GPRS + 72
40__PT_R10     =	__PT_GPRS + 80
41__PT_R11     =	__PT_GPRS + 88
42__PT_R12     =	__PT_GPRS + 96
43__PT_R13     =	__PT_GPRS + 104
44__PT_R14     =	__PT_GPRS + 112
45__PT_R15     =	__PT_GPRS + 120
46
47STACK_SHIFT = PAGE_SHIFT + THREAD_SIZE_ORDER
48STACK_SIZE  = 1 << STACK_SHIFT
49STACK_INIT = STACK_SIZE - STACK_FRAME_OVERHEAD - __PT_SIZE
50
51_TIF_WORK	= (_TIF_SIGPENDING | _TIF_NOTIFY_RESUME | _TIF_NEED_RESCHED | \
52		   _TIF_UPROBE | _TIF_GUARDED_STORAGE | _TIF_PATCH_PENDING)
53_TIF_TRACE	= (_TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT | _TIF_SECCOMP | \
54		   _TIF_SYSCALL_TRACEPOINT)
55_CIF_WORK	= (_CIF_MCCK_PENDING | _CIF_ASCE_PRIMARY | \
56		   _CIF_ASCE_SECONDARY | _CIF_FPU)
57_PIF_WORK	= (_PIF_PER_TRAP | _PIF_SYSCALL_RESTART)
58
59#define BASED(name) name-cleanup_critical(%r13)
60
61	.macro	TRACE_IRQS_ON
62#ifdef CONFIG_TRACE_IRQFLAGS
63	basr	%r2,%r0
64	brasl	%r14,trace_hardirqs_on_caller
65#endif
66	.endm
67
68	.macro	TRACE_IRQS_OFF
69#ifdef CONFIG_TRACE_IRQFLAGS
70	basr	%r2,%r0
71	brasl	%r14,trace_hardirqs_off_caller
72#endif
73	.endm
74
75	.macro	LOCKDEP_SYS_EXIT
76#ifdef CONFIG_LOCKDEP
77	tm	__PT_PSW+1(%r11),0x01	# returning to user ?
78	jz	.+10
79	brasl	%r14,lockdep_sys_exit
80#endif
81	.endm
82
83	.macro	CHECK_STACK stacksize,savearea
84#ifdef CONFIG_CHECK_STACK
85	tml	%r15,\stacksize - CONFIG_STACK_GUARD
86	lghi	%r14,\savearea
87	jz	stack_overflow
88#endif
89	.endm
90
91	.macro	SWITCH_ASYNC savearea,timer
92	tmhh	%r8,0x0001		# interrupting from user ?
93	jnz	1f
94	lgr	%r14,%r9
95	slg	%r14,BASED(.Lcritical_start)
96	clg	%r14,BASED(.Lcritical_length)
97	jhe	0f
98	lghi	%r11,\savearea		# inside critical section, do cleanup
99	brasl	%r14,cleanup_critical
100	tmhh	%r8,0x0001		# retest problem state after cleanup
101	jnz	1f
1020:	lg	%r14,__LC_ASYNC_STACK	# are we already on the async stack?
103	slgr	%r14,%r15
104	srag	%r14,%r14,STACK_SHIFT
105	jnz	2f
106	CHECK_STACK 1<<STACK_SHIFT,\savearea
107	aghi	%r15,-(STACK_FRAME_OVERHEAD + __PT_SIZE)
108	j	3f
1091:	UPDATE_VTIME %r14,%r15,\timer
110	BPENTER __TI_flags(%r12),_TIF_ISOLATE_BP
1112:	lg	%r15,__LC_ASYNC_STACK	# load async stack
1123:	la	%r11,STACK_FRAME_OVERHEAD(%r15)
113	.endm
114
115	.macro UPDATE_VTIME w1,w2,enter_timer
116	lg	\w1,__LC_EXIT_TIMER
117	lg	\w2,__LC_LAST_UPDATE_TIMER
118	slg	\w1,\enter_timer
119	slg	\w2,__LC_EXIT_TIMER
120	alg	\w1,__LC_USER_TIMER
121	alg	\w2,__LC_SYSTEM_TIMER
122	stg	\w1,__LC_USER_TIMER
123	stg	\w2,__LC_SYSTEM_TIMER
124	mvc	__LC_LAST_UPDATE_TIMER(8),\enter_timer
125	.endm
126
127	.macro REENABLE_IRQS
128	stg	%r8,__LC_RETURN_PSW
129	ni	__LC_RETURN_PSW,0xbf
130	ssm	__LC_RETURN_PSW
131	.endm
132
133	.macro STCK savearea
134#ifdef CONFIG_HAVE_MARCH_Z9_109_FEATURES
135	.insn	s,0xb27c0000,\savearea		# store clock fast
136#else
137	.insn	s,0xb2050000,\savearea		# store clock
138#endif
139	.endm
140
141	/*
142	 * The TSTMSK macro generates a test-under-mask instruction by
143	 * calculating the memory offset for the specified mask value.
144	 * Mask value can be any constant.  The macro shifts the mask
145	 * value to calculate the memory offset for the test-under-mask
146	 * instruction.
147	 */
148	.macro TSTMSK addr, mask, size=8, bytepos=0
149		.if (\bytepos < \size) && (\mask >> 8)
150			.if (\mask & 0xff)
151				.error "Mask exceeds byte boundary"
152			.endif
153			TSTMSK \addr, "(\mask >> 8)", \size, "(\bytepos + 1)"
154			.exitm
155		.endif
156		.ifeq \mask
157			.error "Mask must not be zero"
158		.endif
159		off = \size - \bytepos - 1
160		tm	off+\addr, \mask
161	.endm
162
163	.macro BPOFF
164	.pushsection .altinstr_replacement, "ax"
165660:	.long	0xb2e8c000
166	.popsection
167661:	.long	0x47000000
168	.pushsection .altinstructions, "a"
169	.long 661b - .
170	.long 660b - .
171	.word 82
172	.byte 4
173	.byte 4
174	.popsection
175	.endm
176
177	.macro BPON
178	.pushsection .altinstr_replacement, "ax"
179662:	.long	0xb2e8d000
180	.popsection
181663:	.long	0x47000000
182	.pushsection .altinstructions, "a"
183	.long 663b - .
184	.long 662b - .
185	.word 82
186	.byte 4
187	.byte 4
188	.popsection
189	.endm
190
191	.macro BPENTER tif_ptr,tif_mask
192	.pushsection .altinstr_replacement, "ax"
193662:	.word	0xc004, 0x0000, 0x0000	# 6 byte nop
194	.word	0xc004, 0x0000, 0x0000	# 6 byte nop
195	.popsection
196664:	TSTMSK	\tif_ptr,\tif_mask
197	jz	. + 8
198	.long	0xb2e8d000
199	.pushsection .altinstructions, "a"
200	.long 664b - .
201	.long 662b - .
202	.word 82
203	.byte 12
204	.byte 12
205	.popsection
206	.endm
207
208	.macro BPEXIT tif_ptr,tif_mask
209	TSTMSK	\tif_ptr,\tif_mask
210	.pushsection .altinstr_replacement, "ax"
211662:	jnz	. + 8
212	.long	0xb2e8d000
213	.popsection
214664:	jz	. + 8
215	.long	0xb2e8c000
216	.pushsection .altinstructions, "a"
217	.long 664b - .
218	.long 662b - .
219	.word 82
220	.byte 8
221	.byte 8
222	.popsection
223	.endm
224
225#ifdef CONFIG_EXPOLINE
226
227	.macro GEN_BR_THUNK name,reg,tmp
228	.section .text.\name,"axG",@progbits,\name,comdat
229	.globl \name
230	.hidden \name
231	.type \name,@function
232\name:
233	.cfi_startproc
234#ifdef CONFIG_HAVE_MARCH_Z10_FEATURES
235	exrl	0,0f
236#else
237	larl	\tmp,0f
238	ex	0,0(\tmp)
239#endif
240	j	.
2410:	br	\reg
242	.cfi_endproc
243	.endm
244
245	GEN_BR_THUNK __s390x_indirect_jump_r1use_r9,%r9,%r1
246	GEN_BR_THUNK __s390x_indirect_jump_r1use_r14,%r14,%r1
247	GEN_BR_THUNK __s390x_indirect_jump_r11use_r14,%r14,%r11
248
249	.macro BASR_R14_R9
2500:	brasl	%r14,__s390x_indirect_jump_r1use_r9
251	.pushsection .s390_indirect_branches,"a",@progbits
252	.long	0b-.
253	.popsection
254	.endm
255
256	.macro BR_R1USE_R14
2570:	jg	__s390x_indirect_jump_r1use_r14
258	.pushsection .s390_indirect_branches,"a",@progbits
259	.long	0b-.
260	.popsection
261	.endm
262
263	.macro BR_R11USE_R14
2640:	jg	__s390x_indirect_jump_r11use_r14
265	.pushsection .s390_indirect_branches,"a",@progbits
266	.long	0b-.
267	.popsection
268	.endm
269
270#else	/* CONFIG_EXPOLINE */
271
272	.macro BASR_R14_R9
273	basr	%r14,%r9
274	.endm
275
276	.macro BR_R1USE_R14
277	br	%r14
278	.endm
279
280	.macro BR_R11USE_R14
281	br	%r14
282	.endm
283
284#endif /* CONFIG_EXPOLINE */
285
286
287	.section .kprobes.text, "ax"
288.Ldummy:
289	/*
290	 * This nop exists only in order to avoid that __switch_to starts at
291	 * the beginning of the kprobes text section. In that case we would
292	 * have several symbols at the same address. E.g. objdump would take
293	 * an arbitrary symbol name when disassembling this code.
294	 * With the added nop in between the __switch_to symbol is unique
295	 * again.
296	 */
297	nop	0
298
299ENTRY(__bpon)
300	.globl __bpon
301	BPON
302	BR_R1USE_R14
303
304/*
305 * Scheduler resume function, called by switch_to
306 *  gpr2 = (task_struct *) prev
307 *  gpr3 = (task_struct *) next
308 * Returns:
309 *  gpr2 = prev
310 */
311ENTRY(__switch_to)
312	stmg	%r6,%r15,__SF_GPRS(%r15)	# store gprs of prev task
313	lghi	%r4,__TASK_stack
314	lghi	%r1,__TASK_thread
315	lg	%r5,0(%r4,%r3)			# start of kernel stack of next
316	stg	%r15,__THREAD_ksp(%r1,%r2)	# store kernel stack of prev
317	lgr	%r15,%r5
318	aghi	%r15,STACK_INIT			# end of kernel stack of next
319	stg	%r3,__LC_CURRENT		# store task struct of next
320	stg	%r15,__LC_KERNEL_STACK		# store end of kernel stack
321	lg	%r15,__THREAD_ksp(%r1,%r3)	# load kernel stack of next
322	aghi	%r3,__TASK_pid
323	mvc	__LC_CURRENT_PID(4,%r0),0(%r3)	# store pid of next
324	lmg	%r6,%r15,__SF_GPRS(%r15)	# load gprs of next task
325	TSTMSK	__LC_MACHINE_FLAGS,MACHINE_FLAG_LPP
326	jz	0f
327	.insn	s,0xb2800000,__LC_LPP		# set program parameter
3280:	BR_R1USE_R14
329
330.L__critical_start:
331
332#if IS_ENABLED(CONFIG_KVM)
333/*
334 * sie64a calling convention:
335 * %r2 pointer to sie control block
336 * %r3 guest register save area
337 */
338ENTRY(sie64a)
339	stmg	%r6,%r14,__SF_GPRS(%r15)	# save kernel registers
340	lg	%r12,__LC_CURRENT
341	stg	%r2,__SF_EMPTY(%r15)		# save control block pointer
342	stg	%r3,__SF_EMPTY+8(%r15)		# save guest register save area
343	xc	__SF_EMPTY+16(8,%r15),__SF_EMPTY+16(%r15) # reason code = 0
344	mvc	__SF_EMPTY+24(8,%r15),__TI_flags(%r12) # copy thread flags
345	TSTMSK	__LC_CPU_FLAGS,_CIF_FPU		# load guest fp/vx registers ?
346	jno	.Lsie_load_guest_gprs
347	brasl	%r14,load_fpu_regs		# load guest fp/vx regs
348.Lsie_load_guest_gprs:
349	lmg	%r0,%r13,0(%r3)			# load guest gprs 0-13
350	lg	%r14,__LC_GMAP			# get gmap pointer
351	ltgr	%r14,%r14
352	jz	.Lsie_gmap
353	lctlg	%c1,%c1,__GMAP_ASCE(%r14)	# load primary asce
354.Lsie_gmap:
355	lg	%r14,__SF_EMPTY(%r15)		# get control block pointer
356	oi	__SIE_PROG0C+3(%r14),1		# we are going into SIE now
357	tm	__SIE_PROG20+3(%r14),3		# last exit...
358	jnz	.Lsie_skip
359	TSTMSK	__LC_CPU_FLAGS,_CIF_FPU
360	jo	.Lsie_skip			# exit if fp/vx regs changed
361	BPEXIT	__SF_EMPTY+24(%r15),(_TIF_ISOLATE_BP|_TIF_ISOLATE_BP_GUEST)
362.Lsie_entry:
363	sie	0(%r14)
364.Lsie_exit:
365	BPOFF
366	BPENTER	__SF_EMPTY+24(%r15),(_TIF_ISOLATE_BP|_TIF_ISOLATE_BP_GUEST)
367.Lsie_skip:
368	ni	__SIE_PROG0C+3(%r14),0xfe	# no longer in SIE
369	lctlg	%c1,%c1,__LC_USER_ASCE		# load primary asce
370.Lsie_done:
371# some program checks are suppressing. C code (e.g. do_protection_exception)
372# will rewind the PSW by the ILC, which is often 4 bytes in case of SIE. There
373# are some corner cases (e.g. runtime instrumentation) where ILC is unpredictable.
374# Other instructions between sie64a and .Lsie_done should not cause program
375# interrupts. So lets use 3 nops as a landing pad for all possible rewinds.
376# See also .Lcleanup_sie
377.Lrewind_pad6:
378	nopr	7
379.Lrewind_pad4:
380	nopr	7
381.Lrewind_pad2:
382	nopr	7
383	.globl sie_exit
384sie_exit:
385	lg	%r14,__SF_EMPTY+8(%r15)		# load guest register save area
386	stmg	%r0,%r13,0(%r14)		# save guest gprs 0-13
387	xgr	%r0,%r0				# clear guest registers to
388	xgr	%r1,%r1				# prevent speculative use
389	xgr	%r2,%r2
390	xgr	%r3,%r3
391	xgr	%r4,%r4
392	xgr	%r5,%r5
393	lmg	%r6,%r14,__SF_GPRS(%r15)	# restore kernel registers
394	lg	%r2,__SF_EMPTY+16(%r15)		# return exit reason code
395	BR_R1USE_R14
396.Lsie_fault:
397	lghi	%r14,-EFAULT
398	stg	%r14,__SF_EMPTY+16(%r15)	# set exit reason code
399	j	sie_exit
400
401	EX_TABLE(.Lrewind_pad6,.Lsie_fault)
402	EX_TABLE(.Lrewind_pad4,.Lsie_fault)
403	EX_TABLE(.Lrewind_pad2,.Lsie_fault)
404	EX_TABLE(sie_exit,.Lsie_fault)
405EXPORT_SYMBOL(sie64a)
406EXPORT_SYMBOL(sie_exit)
407#endif
408
409/*
410 * SVC interrupt handler routine. System calls are synchronous events and
411 * are executed with interrupts enabled.
412 */
413
414ENTRY(system_call)
415	stpt	__LC_SYNC_ENTER_TIMER
416.Lsysc_stmg:
417	stmg	%r8,%r15,__LC_SAVE_AREA_SYNC
418	BPOFF
419	lg	%r12,__LC_CURRENT
420	lghi	%r13,__TASK_thread
421	lghi	%r14,_PIF_SYSCALL
422.Lsysc_per:
423	lg	%r15,__LC_KERNEL_STACK
424	la	%r11,STACK_FRAME_OVERHEAD(%r15)	# pointer to pt_regs
425.Lsysc_vtime:
426	UPDATE_VTIME %r8,%r9,__LC_SYNC_ENTER_TIMER
427	BPENTER __TI_flags(%r12),_TIF_ISOLATE_BP
428	stmg	%r0,%r7,__PT_R0(%r11)
429	# clear user controlled register to prevent speculative use
430	xgr	%r0,%r0
431	mvc	__PT_R8(64,%r11),__LC_SAVE_AREA_SYNC
432	mvc	__PT_PSW(16,%r11),__LC_SVC_OLD_PSW
433	mvc	__PT_INT_CODE(4,%r11),__LC_SVC_ILC
434	stg	%r14,__PT_FLAGS(%r11)
435.Lsysc_do_svc:
436	# load address of system call table
437	lg	%r10,__THREAD_sysc_table(%r13,%r12)
438	llgh	%r8,__PT_INT_CODE+2(%r11)
439	slag	%r8,%r8,2			# shift and test for svc 0
440	jnz	.Lsysc_nr_ok
441	# svc 0: system call number in %r1
442	llgfr	%r1,%r1				# clear high word in r1
443	cghi	%r1,NR_syscalls
444	jnl	.Lsysc_nr_ok
445	sth	%r1,__PT_INT_CODE+2(%r11)
446	slag	%r8,%r1,2
447.Lsysc_nr_ok:
448	xc	__SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
449	stg	%r2,__PT_ORIG_GPR2(%r11)
450	stg	%r7,STACK_FRAME_OVERHEAD(%r15)
451	lgf	%r9,0(%r8,%r10)			# get system call add.
452	TSTMSK	__TI_flags(%r12),_TIF_TRACE
453	jnz	.Lsysc_tracesys
454	BASR_R14_R9				# call sys_xxxx
455	stg	%r2,__PT_R2(%r11)		# store return value
456
457.Lsysc_return:
458	LOCKDEP_SYS_EXIT
459.Lsysc_tif:
460	TSTMSK	__PT_FLAGS(%r11),_PIF_WORK
461	jnz	.Lsysc_work
462	TSTMSK	__TI_flags(%r12),_TIF_WORK
463	jnz	.Lsysc_work			# check for work
464	TSTMSK	__LC_CPU_FLAGS,_CIF_WORK
465	jnz	.Lsysc_work
466	BPEXIT	__TI_flags(%r12),_TIF_ISOLATE_BP
467.Lsysc_restore:
468	lg	%r14,__LC_VDSO_PER_CPU
469	lmg	%r0,%r10,__PT_R0(%r11)
470	mvc	__LC_RETURN_PSW(16),__PT_PSW(%r11)
471.Lsysc_exit_timer:
472	stpt	__LC_EXIT_TIMER
473	mvc	__VDSO_ECTG_BASE(16,%r14),__LC_EXIT_TIMER
474	lmg	%r11,%r15,__PT_R11(%r11)
475	lpswe	__LC_RETURN_PSW
476.Lsysc_done:
477
478#
479# One of the work bits is on. Find out which one.
480#
481.Lsysc_work:
482	TSTMSK	__LC_CPU_FLAGS,_CIF_MCCK_PENDING
483	jo	.Lsysc_mcck_pending
484	TSTMSK	__TI_flags(%r12),_TIF_NEED_RESCHED
485	jo	.Lsysc_reschedule
486	TSTMSK	__PT_FLAGS(%r11),_PIF_SYSCALL_RESTART
487	jo	.Lsysc_syscall_restart
488#ifdef CONFIG_UPROBES
489	TSTMSK	__TI_flags(%r12),_TIF_UPROBE
490	jo	.Lsysc_uprobe_notify
491#endif
492	TSTMSK	__TI_flags(%r12),_TIF_GUARDED_STORAGE
493	jo	.Lsysc_guarded_storage
494	TSTMSK	__PT_FLAGS(%r11),_PIF_PER_TRAP
495	jo	.Lsysc_singlestep
496#ifdef CONFIG_LIVEPATCH
497	TSTMSK	__TI_flags(%r12),_TIF_PATCH_PENDING
498	jo	.Lsysc_patch_pending	# handle live patching just before
499					# signals and possible syscall restart
500#endif
501	TSTMSK	__PT_FLAGS(%r11),_PIF_SYSCALL_RESTART
502	jo	.Lsysc_syscall_restart
503	TSTMSK	__TI_flags(%r12),_TIF_SIGPENDING
504	jo	.Lsysc_sigpending
505	TSTMSK	__TI_flags(%r12),_TIF_NOTIFY_RESUME
506	jo	.Lsysc_notify_resume
507	TSTMSK	__LC_CPU_FLAGS,_CIF_FPU
508	jo	.Lsysc_vxrs
509	TSTMSK	__LC_CPU_FLAGS,(_CIF_ASCE_PRIMARY|_CIF_ASCE_SECONDARY)
510	jnz	.Lsysc_asce
511	j	.Lsysc_return		# beware of critical section cleanup
512
513#
514# _TIF_NEED_RESCHED is set, call schedule
515#
516.Lsysc_reschedule:
517	larl	%r14,.Lsysc_return
518	jg	schedule
519
520#
521# _CIF_MCCK_PENDING is set, call handler
522#
523.Lsysc_mcck_pending:
524	larl	%r14,.Lsysc_return
525	jg	s390_handle_mcck	# TIF bit will be cleared by handler
526
527#
528# _CIF_ASCE_PRIMARY and/or _CIF_ASCE_SECONDARY set, load user space asce
529#
530.Lsysc_asce:
531	ni	__LC_CPU_FLAGS+7,255-_CIF_ASCE_SECONDARY
532	lctlg	%c7,%c7,__LC_VDSO_ASCE		# load secondary asce
533	TSTMSK	__LC_CPU_FLAGS,_CIF_ASCE_PRIMARY
534	jz	.Lsysc_return
535#ifndef CONFIG_HAVE_MARCH_Z10_FEATURES
536	tm	__LC_STFLE_FAC_LIST+3,0x10	# has MVCOS ?
537	jnz	.Lsysc_set_fs_fixup
538	ni	__LC_CPU_FLAGS+7,255-_CIF_ASCE_PRIMARY
539	lctlg	%c1,%c1,__LC_USER_ASCE		# load primary asce
540	j	.Lsysc_return
541.Lsysc_set_fs_fixup:
542#endif
543	larl	%r14,.Lsysc_return
544	jg	set_fs_fixup
545
546#
547# CIF_FPU is set, restore floating-point controls and floating-point registers.
548#
549.Lsysc_vxrs:
550	larl	%r14,.Lsysc_return
551	jg	load_fpu_regs
552
553#
554# _TIF_SIGPENDING is set, call do_signal
555#
556.Lsysc_sigpending:
557	lgr	%r2,%r11		# pass pointer to pt_regs
558	brasl	%r14,do_signal
559	TSTMSK	__PT_FLAGS(%r11),_PIF_SYSCALL
560	jno	.Lsysc_return
561.Lsysc_do_syscall:
562	lghi	%r13,__TASK_thread
563	lmg	%r2,%r7,__PT_R2(%r11)	# load svc arguments
564	lghi	%r1,0			# svc 0 returns -ENOSYS
565	j	.Lsysc_do_svc
566
567#
568# _TIF_NOTIFY_RESUME is set, call do_notify_resume
569#
570.Lsysc_notify_resume:
571	lgr	%r2,%r11		# pass pointer to pt_regs
572	larl	%r14,.Lsysc_return
573	jg	do_notify_resume
574
575#
576# _TIF_UPROBE is set, call uprobe_notify_resume
577#
578#ifdef CONFIG_UPROBES
579.Lsysc_uprobe_notify:
580	lgr	%r2,%r11		# pass pointer to pt_regs
581	larl	%r14,.Lsysc_return
582	jg	uprobe_notify_resume
583#endif
584
585#
586# _TIF_GUARDED_STORAGE is set, call guarded_storage_load
587#
588.Lsysc_guarded_storage:
589	lgr	%r2,%r11		# pass pointer to pt_regs
590	larl	%r14,.Lsysc_return
591	jg	gs_load_bc_cb
592#
593# _TIF_PATCH_PENDING is set, call klp_update_patch_state
594#
595#ifdef CONFIG_LIVEPATCH
596.Lsysc_patch_pending:
597	lg	%r2,__LC_CURRENT	# pass pointer to task struct
598	larl	%r14,.Lsysc_return
599	jg	klp_update_patch_state
600#endif
601
602#
603# _PIF_PER_TRAP is set, call do_per_trap
604#
605.Lsysc_singlestep:
606	ni	__PT_FLAGS+7(%r11),255-_PIF_PER_TRAP
607	lgr	%r2,%r11		# pass pointer to pt_regs
608	larl	%r14,.Lsysc_return
609	jg	do_per_trap
610
611#
612# _PIF_SYSCALL_RESTART is set, repeat the current system call
613#
614.Lsysc_syscall_restart:
615	ni	__PT_FLAGS+7(%r11),255-_PIF_SYSCALL_RESTART
616	lmg	%r1,%r7,__PT_R1(%r11)	# load svc arguments
617	lg	%r2,__PT_ORIG_GPR2(%r11)
618	j	.Lsysc_do_svc
619
620#
621# call tracehook_report_syscall_entry/tracehook_report_syscall_exit before
622# and after the system call
623#
624.Lsysc_tracesys:
625	lgr	%r2,%r11		# pass pointer to pt_regs
626	la	%r3,0
627	llgh	%r0,__PT_INT_CODE+2(%r11)
628	stg	%r0,__PT_R2(%r11)
629	brasl	%r14,do_syscall_trace_enter
630	lghi	%r0,NR_syscalls
631	clgr	%r0,%r2
632	jnh	.Lsysc_tracenogo
633	sllg	%r8,%r2,2
634	lgf	%r9,0(%r8,%r10)
635.Lsysc_tracego:
636	lmg	%r3,%r7,__PT_R3(%r11)
637	stg	%r7,STACK_FRAME_OVERHEAD(%r15)
638	lg	%r2,__PT_ORIG_GPR2(%r11)
639	BASR_R14_R9			# call sys_xxx
640	stg	%r2,__PT_R2(%r11)	# store return value
641.Lsysc_tracenogo:
642	TSTMSK	__TI_flags(%r12),_TIF_TRACE
643	jz	.Lsysc_return
644	lgr	%r2,%r11		# pass pointer to pt_regs
645	larl	%r14,.Lsysc_return
646	jg	do_syscall_trace_exit
647
648#
649# a new process exits the kernel with ret_from_fork
650#
651ENTRY(ret_from_fork)
652	la	%r11,STACK_FRAME_OVERHEAD(%r15)
653	lg	%r12,__LC_CURRENT
654	brasl	%r14,schedule_tail
655	TRACE_IRQS_ON
656	ssm	__LC_SVC_NEW_PSW	# reenable interrupts
657	tm	__PT_PSW+1(%r11),0x01	# forking a kernel thread ?
658	jne	.Lsysc_tracenogo
659	# it's a kernel thread
660	lmg	%r9,%r10,__PT_R9(%r11)	# load gprs
661ENTRY(kernel_thread_starter)
662	la	%r2,0(%r10)
663	BASR_R14_R9
664	j	.Lsysc_tracenogo
665
666/*
667 * Program check handler routine
668 */
669
670ENTRY(pgm_check_handler)
671	stpt	__LC_SYNC_ENTER_TIMER
672	BPOFF
673	stmg	%r8,%r15,__LC_SAVE_AREA_SYNC
674	lg	%r10,__LC_LAST_BREAK
675	lg	%r12,__LC_CURRENT
676	lghi	%r11,0
677	larl	%r13,cleanup_critical
678	lmg	%r8,%r9,__LC_PGM_OLD_PSW
679	tmhh	%r8,0x0001		# test problem state bit
680	jnz	2f			# -> fault in user space
681#if IS_ENABLED(CONFIG_KVM)
682	# cleanup critical section for program checks in sie64a
683	lgr	%r14,%r9
684	slg	%r14,BASED(.Lsie_critical_start)
685	clg	%r14,BASED(.Lsie_critical_length)
686	jhe	0f
687	lg	%r14,__SF_EMPTY(%r15)		# get control block pointer
688	ni	__SIE_PROG0C+3(%r14),0xfe	# no longer in SIE
689	lctlg	%c1,%c1,__LC_USER_ASCE		# load primary asce
690	larl	%r9,sie_exit			# skip forward to sie_exit
691	lghi	%r11,_PIF_GUEST_FAULT
692#endif
6930:	tmhh	%r8,0x4000		# PER bit set in old PSW ?
694	jnz	1f			# -> enabled, can't be a double fault
695	tm	__LC_PGM_ILC+3,0x80	# check for per exception
696	jnz	.Lpgm_svcper		# -> single stepped svc
6971:	CHECK_STACK STACK_SIZE,__LC_SAVE_AREA_SYNC
698	aghi	%r15,-(STACK_FRAME_OVERHEAD + __PT_SIZE)
699	j	4f
7002:	UPDATE_VTIME %r14,%r15,__LC_SYNC_ENTER_TIMER
701	BPENTER __TI_flags(%r12),_TIF_ISOLATE_BP
702	lg	%r15,__LC_KERNEL_STACK
703	lgr	%r14,%r12
704	aghi	%r14,__TASK_thread	# pointer to thread_struct
705	lghi	%r13,__LC_PGM_TDB
706	tm	__LC_PGM_ILC+2,0x02	# check for transaction abort
707	jz	3f
708	mvc	__THREAD_trap_tdb(256,%r14),0(%r13)
7093:	stg	%r10,__THREAD_last_break(%r14)
7104:	lgr	%r13,%r11
711	la	%r11,STACK_FRAME_OVERHEAD(%r15)
712	stmg	%r0,%r7,__PT_R0(%r11)
713	# clear user controlled registers to prevent speculative use
714	xgr	%r0,%r0
715	xgr	%r1,%r1
716	xgr	%r2,%r2
717	xgr	%r3,%r3
718	xgr	%r4,%r4
719	xgr	%r5,%r5
720	xgr	%r6,%r6
721	xgr	%r7,%r7
722	mvc	__PT_R8(64,%r11),__LC_SAVE_AREA_SYNC
723	stmg	%r8,%r9,__PT_PSW(%r11)
724	mvc	__PT_INT_CODE(4,%r11),__LC_PGM_ILC
725	mvc	__PT_INT_PARM_LONG(8,%r11),__LC_TRANS_EXC_CODE
726	stg	%r13,__PT_FLAGS(%r11)
727	stg	%r10,__PT_ARGS(%r11)
728	tm	__LC_PGM_ILC+3,0x80	# check for per exception
729	jz	5f
730	tmhh	%r8,0x0001		# kernel per event ?
731	jz	.Lpgm_kprobe
732	oi	__PT_FLAGS+7(%r11),_PIF_PER_TRAP
733	mvc	__THREAD_per_address(8,%r14),__LC_PER_ADDRESS
734	mvc	__THREAD_per_cause(2,%r14),__LC_PER_CODE
735	mvc	__THREAD_per_paid(1,%r14),__LC_PER_ACCESS_ID
7365:	REENABLE_IRQS
737	xc	__SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
738	larl	%r1,pgm_check_table
739	llgh	%r10,__PT_INT_CODE+2(%r11)
740	nill	%r10,0x007f
741	sll	%r10,2
742	je	.Lpgm_return
743	lgf	%r9,0(%r10,%r1)		# load address of handler routine
744	lgr	%r2,%r11		# pass pointer to pt_regs
745	BASR_R14_R9			# branch to interrupt-handler
746.Lpgm_return:
747	LOCKDEP_SYS_EXIT
748	tm	__PT_PSW+1(%r11),0x01	# returning to user ?
749	jno	.Lsysc_restore
750	TSTMSK	__PT_FLAGS(%r11),_PIF_SYSCALL
751	jo	.Lsysc_do_syscall
752	j	.Lsysc_tif
753
754#
755# PER event in supervisor state, must be kprobes
756#
757.Lpgm_kprobe:
758	REENABLE_IRQS
759	xc	__SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
760	lgr	%r2,%r11		# pass pointer to pt_regs
761	brasl	%r14,do_per_trap
762	j	.Lpgm_return
763
764#
765# single stepped system call
766#
767.Lpgm_svcper:
768	mvc	__LC_RETURN_PSW(8),__LC_SVC_NEW_PSW
769	lghi	%r13,__TASK_thread
770	larl	%r14,.Lsysc_per
771	stg	%r14,__LC_RETURN_PSW+8
772	lghi	%r14,_PIF_SYSCALL | _PIF_PER_TRAP
773	lpswe	__LC_RETURN_PSW		# branch to .Lsysc_per and enable irqs
774
775/*
776 * IO interrupt handler routine
777 */
778ENTRY(io_int_handler)
779	STCK	__LC_INT_CLOCK
780	stpt	__LC_ASYNC_ENTER_TIMER
781	BPOFF
782	stmg	%r8,%r15,__LC_SAVE_AREA_ASYNC
783	lg	%r12,__LC_CURRENT
784	larl	%r13,cleanup_critical
785	lmg	%r8,%r9,__LC_IO_OLD_PSW
786	SWITCH_ASYNC __LC_SAVE_AREA_ASYNC,__LC_ASYNC_ENTER_TIMER
787	stmg	%r0,%r7,__PT_R0(%r11)
788	# clear user controlled registers to prevent speculative use
789	xgr	%r0,%r0
790	xgr	%r1,%r1
791	xgr	%r2,%r2
792	xgr	%r3,%r3
793	xgr	%r4,%r4
794	xgr	%r5,%r5
795	xgr	%r6,%r6
796	xgr	%r7,%r7
797	xgr	%r10,%r10
798	mvc	__PT_R8(64,%r11),__LC_SAVE_AREA_ASYNC
799	stmg	%r8,%r9,__PT_PSW(%r11)
800	mvc	__PT_INT_CODE(12,%r11),__LC_SUBCHANNEL_ID
801	xc	__PT_FLAGS(8,%r11),__PT_FLAGS(%r11)
802	TSTMSK	__LC_CPU_FLAGS,_CIF_IGNORE_IRQ
803	jo	.Lio_restore
804	TRACE_IRQS_OFF
805	xc	__SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
806.Lio_loop:
807	lgr	%r2,%r11		# pass pointer to pt_regs
808	lghi	%r3,IO_INTERRUPT
809	tm	__PT_INT_CODE+8(%r11),0x80	# adapter interrupt ?
810	jz	.Lio_call
811	lghi	%r3,THIN_INTERRUPT
812.Lio_call:
813	brasl	%r14,do_IRQ
814	TSTMSK	__LC_MACHINE_FLAGS,MACHINE_FLAG_LPAR
815	jz	.Lio_return
816	tpi	0
817	jz	.Lio_return
818	mvc	__PT_INT_CODE(12,%r11),__LC_SUBCHANNEL_ID
819	j	.Lio_loop
820.Lio_return:
821	LOCKDEP_SYS_EXIT
822	TRACE_IRQS_ON
823.Lio_tif:
824	TSTMSK	__TI_flags(%r12),_TIF_WORK
825	jnz	.Lio_work		# there is work to do (signals etc.)
826	TSTMSK	__LC_CPU_FLAGS,_CIF_WORK
827	jnz	.Lio_work
828.Lio_restore:
829	lg	%r14,__LC_VDSO_PER_CPU
830	lmg	%r0,%r10,__PT_R0(%r11)
831	mvc	__LC_RETURN_PSW(16),__PT_PSW(%r11)
832	tm	__PT_PSW+1(%r11),0x01	# returning to user ?
833	jno	.Lio_exit_kernel
834	BPEXIT	__TI_flags(%r12),_TIF_ISOLATE_BP
835.Lio_exit_timer:
836	stpt	__LC_EXIT_TIMER
837	mvc	__VDSO_ECTG_BASE(16,%r14),__LC_EXIT_TIMER
838.Lio_exit_kernel:
839	lmg	%r11,%r15,__PT_R11(%r11)
840	lpswe	__LC_RETURN_PSW
841.Lio_done:
842
843#
844# There is work todo, find out in which context we have been interrupted:
845# 1) if we return to user space we can do all _TIF_WORK work
846# 2) if we return to kernel code and kvm is enabled check if we need to
847#    modify the psw to leave SIE
848# 3) if we return to kernel code and preemptive scheduling is enabled check
849#    the preemption counter and if it is zero call preempt_schedule_irq
850# Before any work can be done, a switch to the kernel stack is required.
851#
852.Lio_work:
853	tm	__PT_PSW+1(%r11),0x01	# returning to user ?
854	jo	.Lio_work_user		# yes -> do resched & signal
855#ifdef CONFIG_PREEMPT
856	# check for preemptive scheduling
857	icm	%r0,15,__LC_PREEMPT_COUNT
858	jnz	.Lio_restore		# preemption is disabled
859	TSTMSK	__TI_flags(%r12),_TIF_NEED_RESCHED
860	jno	.Lio_restore
861	# switch to kernel stack
862	lg	%r1,__PT_R15(%r11)
863	aghi	%r1,-(STACK_FRAME_OVERHEAD + __PT_SIZE)
864	mvc	STACK_FRAME_OVERHEAD(__PT_SIZE,%r1),0(%r11)
865	xc	__SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1)
866	la	%r11,STACK_FRAME_OVERHEAD(%r1)
867	lgr	%r15,%r1
868	# TRACE_IRQS_ON already done at .Lio_return, call
869	# TRACE_IRQS_OFF to keep things symmetrical
870	TRACE_IRQS_OFF
871	brasl	%r14,preempt_schedule_irq
872	j	.Lio_return
873#else
874	j	.Lio_restore
875#endif
876
877#
878# Need to do work before returning to userspace, switch to kernel stack
879#
880.Lio_work_user:
881	lg	%r1,__LC_KERNEL_STACK
882	mvc	STACK_FRAME_OVERHEAD(__PT_SIZE,%r1),0(%r11)
883	xc	__SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1)
884	la	%r11,STACK_FRAME_OVERHEAD(%r1)
885	lgr	%r15,%r1
886
887#
888# One of the work bits is on. Find out which one.
889#
890.Lio_work_tif:
891	TSTMSK	__LC_CPU_FLAGS,_CIF_MCCK_PENDING
892	jo	.Lio_mcck_pending
893	TSTMSK	__TI_flags(%r12),_TIF_NEED_RESCHED
894	jo	.Lio_reschedule
895#ifdef CONFIG_LIVEPATCH
896	TSTMSK	__TI_flags(%r12),_TIF_PATCH_PENDING
897	jo	.Lio_patch_pending
898#endif
899	TSTMSK	__TI_flags(%r12),_TIF_SIGPENDING
900	jo	.Lio_sigpending
901	TSTMSK	__TI_flags(%r12),_TIF_NOTIFY_RESUME
902	jo	.Lio_notify_resume
903	TSTMSK	__TI_flags(%r12),_TIF_GUARDED_STORAGE
904	jo	.Lio_guarded_storage
905	TSTMSK	__LC_CPU_FLAGS,_CIF_FPU
906	jo	.Lio_vxrs
907	TSTMSK	__LC_CPU_FLAGS,(_CIF_ASCE_PRIMARY|_CIF_ASCE_SECONDARY)
908	jnz	.Lio_asce
909	j	.Lio_return		# beware of critical section cleanup
910
911#
912# _CIF_MCCK_PENDING is set, call handler
913#
914.Lio_mcck_pending:
915	# TRACE_IRQS_ON already done at .Lio_return
916	brasl	%r14,s390_handle_mcck	# TIF bit will be cleared by handler
917	TRACE_IRQS_OFF
918	j	.Lio_return
919
920#
921# _CIF_ASCE_PRIMARY and/or CIF_ASCE_SECONDARY set, load user space asce
922#
923.Lio_asce:
924	ni	__LC_CPU_FLAGS+7,255-_CIF_ASCE_SECONDARY
925	lctlg	%c7,%c7,__LC_VDSO_ASCE		# load secondary asce
926	TSTMSK	__LC_CPU_FLAGS,_CIF_ASCE_PRIMARY
927	jz	.Lio_return
928#ifndef CONFIG_HAVE_MARCH_Z10_FEATURES
929	tm	__LC_STFLE_FAC_LIST+3,0x10	# has MVCOS ?
930	jnz	.Lio_set_fs_fixup
931	ni	__LC_CPU_FLAGS+7,255-_CIF_ASCE_PRIMARY
932	lctlg	%c1,%c1,__LC_USER_ASCE		# load primary asce
933	j	.Lio_return
934.Lio_set_fs_fixup:
935#endif
936	larl	%r14,.Lio_return
937	jg	set_fs_fixup
938
939#
940# CIF_FPU is set, restore floating-point controls and floating-point registers.
941#
942.Lio_vxrs:
943	larl	%r14,.Lio_return
944	jg	load_fpu_regs
945
946#
947# _TIF_GUARDED_STORAGE is set, call guarded_storage_load
948#
949.Lio_guarded_storage:
950	# TRACE_IRQS_ON already done at .Lio_return
951	ssm	__LC_SVC_NEW_PSW	# reenable interrupts
952	lgr	%r2,%r11		# pass pointer to pt_regs
953	brasl	%r14,gs_load_bc_cb
954	ssm	__LC_PGM_NEW_PSW	# disable I/O and ext. interrupts
955	TRACE_IRQS_OFF
956	j	.Lio_return
957
958#
959# _TIF_NEED_RESCHED is set, call schedule
960#
961.Lio_reschedule:
962	# TRACE_IRQS_ON already done at .Lio_return
963	ssm	__LC_SVC_NEW_PSW	# reenable interrupts
964	brasl	%r14,schedule		# call scheduler
965	ssm	__LC_PGM_NEW_PSW	# disable I/O and ext. interrupts
966	TRACE_IRQS_OFF
967	j	.Lio_return
968
969#
970# _TIF_PATCH_PENDING is set, call klp_update_patch_state
971#
972#ifdef CONFIG_LIVEPATCH
973.Lio_patch_pending:
974	lg	%r2,__LC_CURRENT	# pass pointer to task struct
975	larl	%r14,.Lio_return
976	jg	klp_update_patch_state
977#endif
978
979#
980# _TIF_SIGPENDING or is set, call do_signal
981#
982.Lio_sigpending:
983	# TRACE_IRQS_ON already done at .Lio_return
984	ssm	__LC_SVC_NEW_PSW	# reenable interrupts
985	lgr	%r2,%r11		# pass pointer to pt_regs
986	brasl	%r14,do_signal
987	ssm	__LC_PGM_NEW_PSW	# disable I/O and ext. interrupts
988	TRACE_IRQS_OFF
989	j	.Lio_return
990
991#
992# _TIF_NOTIFY_RESUME or is set, call do_notify_resume
993#
994.Lio_notify_resume:
995	# TRACE_IRQS_ON already done at .Lio_return
996	ssm	__LC_SVC_NEW_PSW	# reenable interrupts
997	lgr	%r2,%r11		# pass pointer to pt_regs
998	brasl	%r14,do_notify_resume
999	ssm	__LC_PGM_NEW_PSW	# disable I/O and ext. interrupts
1000	TRACE_IRQS_OFF
1001	j	.Lio_return
1002
1003/*
1004 * External interrupt handler routine
1005 */
1006ENTRY(ext_int_handler)
1007	STCK	__LC_INT_CLOCK
1008	stpt	__LC_ASYNC_ENTER_TIMER
1009	BPOFF
1010	stmg	%r8,%r15,__LC_SAVE_AREA_ASYNC
1011	lg	%r12,__LC_CURRENT
1012	larl	%r13,cleanup_critical
1013	lmg	%r8,%r9,__LC_EXT_OLD_PSW
1014	SWITCH_ASYNC __LC_SAVE_AREA_ASYNC,__LC_ASYNC_ENTER_TIMER
1015	stmg	%r0,%r7,__PT_R0(%r11)
1016	# clear user controlled registers to prevent speculative use
1017	xgr	%r0,%r0
1018	xgr	%r1,%r1
1019	xgr	%r2,%r2
1020	xgr	%r3,%r3
1021	xgr	%r4,%r4
1022	xgr	%r5,%r5
1023	xgr	%r6,%r6
1024	xgr	%r7,%r7
1025	xgr	%r10,%r10
1026	mvc	__PT_R8(64,%r11),__LC_SAVE_AREA_ASYNC
1027	stmg	%r8,%r9,__PT_PSW(%r11)
1028	lghi	%r1,__LC_EXT_PARAMS2
1029	mvc	__PT_INT_CODE(4,%r11),__LC_EXT_CPU_ADDR
1030	mvc	__PT_INT_PARM(4,%r11),__LC_EXT_PARAMS
1031	mvc	__PT_INT_PARM_LONG(8,%r11),0(%r1)
1032	xc	__PT_FLAGS(8,%r11),__PT_FLAGS(%r11)
1033	TSTMSK	__LC_CPU_FLAGS,_CIF_IGNORE_IRQ
1034	jo	.Lio_restore
1035	TRACE_IRQS_OFF
1036	xc	__SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
1037	lgr	%r2,%r11		# pass pointer to pt_regs
1038	lghi	%r3,EXT_INTERRUPT
1039	brasl	%r14,do_IRQ
1040	j	.Lio_return
1041
1042/*
1043 * Load idle PSW. The second "half" of this function is in .Lcleanup_idle.
1044 */
1045ENTRY(psw_idle)
1046	stg	%r3,__SF_EMPTY(%r15)
1047	larl	%r1,.Lpsw_idle_lpsw+4
1048	stg	%r1,__SF_EMPTY+8(%r15)
1049#ifdef CONFIG_SMP
1050	larl	%r1,smp_cpu_mtid
1051	llgf	%r1,0(%r1)
1052	ltgr	%r1,%r1
1053	jz	.Lpsw_idle_stcctm
1054	.insn	rsy,0xeb0000000017,%r1,5,__SF_EMPTY+16(%r15)
1055.Lpsw_idle_stcctm:
1056#endif
1057	oi	__LC_CPU_FLAGS+7,_CIF_ENABLED_WAIT
1058	BPON
1059	STCK	__CLOCK_IDLE_ENTER(%r2)
1060	stpt	__TIMER_IDLE_ENTER(%r2)
1061.Lpsw_idle_lpsw:
1062	lpswe	__SF_EMPTY(%r15)
1063	BR_R1USE_R14
1064.Lpsw_idle_end:
1065
1066/*
1067 * Store floating-point controls and floating-point or vector register
1068 * depending whether the vector facility is available.	A critical section
1069 * cleanup assures that the registers are stored even if interrupted for
1070 * some other work.  The CIF_FPU flag is set to trigger a lazy restore
1071 * of the register contents at return from io or a system call.
1072 */
1073ENTRY(save_fpu_regs)
1074	lg	%r2,__LC_CURRENT
1075	aghi	%r2,__TASK_thread
1076	TSTMSK	__LC_CPU_FLAGS,_CIF_FPU
1077	jo	.Lsave_fpu_regs_exit
1078	stfpc	__THREAD_FPU_fpc(%r2)
1079	lg	%r3,__THREAD_FPU_regs(%r2)
1080	TSTMSK	__LC_MACHINE_FLAGS,MACHINE_FLAG_VX
1081	jz	.Lsave_fpu_regs_fp	  # no -> store FP regs
1082	VSTM	%v0,%v15,0,%r3		  # vstm 0,15,0(3)
1083	VSTM	%v16,%v31,256,%r3	  # vstm 16,31,256(3)
1084	j	.Lsave_fpu_regs_done	  # -> set CIF_FPU flag
1085.Lsave_fpu_regs_fp:
1086	std	0,0(%r3)
1087	std	1,8(%r3)
1088	std	2,16(%r3)
1089	std	3,24(%r3)
1090	std	4,32(%r3)
1091	std	5,40(%r3)
1092	std	6,48(%r3)
1093	std	7,56(%r3)
1094	std	8,64(%r3)
1095	std	9,72(%r3)
1096	std	10,80(%r3)
1097	std	11,88(%r3)
1098	std	12,96(%r3)
1099	std	13,104(%r3)
1100	std	14,112(%r3)
1101	std	15,120(%r3)
1102.Lsave_fpu_regs_done:
1103	oi	__LC_CPU_FLAGS+7,_CIF_FPU
1104.Lsave_fpu_regs_exit:
1105	BR_R1USE_R14
1106.Lsave_fpu_regs_end:
1107EXPORT_SYMBOL(save_fpu_regs)
1108
1109/*
1110 * Load floating-point controls and floating-point or vector registers.
1111 * A critical section cleanup assures that the register contents are
1112 * loaded even if interrupted for some other work.
1113 *
1114 * There are special calling conventions to fit into sysc and io return work:
1115 *	%r15:	<kernel stack>
1116 * The function requires:
1117 *	%r4
1118 */
1119load_fpu_regs:
1120	lg	%r4,__LC_CURRENT
1121	aghi	%r4,__TASK_thread
1122	TSTMSK	__LC_CPU_FLAGS,_CIF_FPU
1123	jno	.Lload_fpu_regs_exit
1124	lfpc	__THREAD_FPU_fpc(%r4)
1125	TSTMSK	__LC_MACHINE_FLAGS,MACHINE_FLAG_VX
1126	lg	%r4,__THREAD_FPU_regs(%r4)	# %r4 <- reg save area
1127	jz	.Lload_fpu_regs_fp		# -> no VX, load FP regs
1128	VLM	%v0,%v15,0,%r4
1129	VLM	%v16,%v31,256,%r4
1130	j	.Lload_fpu_regs_done
1131.Lload_fpu_regs_fp:
1132	ld	0,0(%r4)
1133	ld	1,8(%r4)
1134	ld	2,16(%r4)
1135	ld	3,24(%r4)
1136	ld	4,32(%r4)
1137	ld	5,40(%r4)
1138	ld	6,48(%r4)
1139	ld	7,56(%r4)
1140	ld	8,64(%r4)
1141	ld	9,72(%r4)
1142	ld	10,80(%r4)
1143	ld	11,88(%r4)
1144	ld	12,96(%r4)
1145	ld	13,104(%r4)
1146	ld	14,112(%r4)
1147	ld	15,120(%r4)
1148.Lload_fpu_regs_done:
1149	ni	__LC_CPU_FLAGS+7,255-_CIF_FPU
1150.Lload_fpu_regs_exit:
1151	BR_R1USE_R14
1152.Lload_fpu_regs_end:
1153
1154.L__critical_end:
1155
1156/*
1157 * Machine check handler routines
1158 */
1159ENTRY(mcck_int_handler)
1160	STCK	__LC_MCCK_CLOCK
1161	BPOFF
1162	la	%r1,4095		# validate r1
1163	spt	__LC_CPU_TIMER_SAVE_AREA-4095(%r1)	# validate cpu timer
1164	sckc	__LC_CLOCK_COMPARATOR			# validate comparator
1165	lam	%a0,%a15,__LC_AREGS_SAVE_AREA-4095(%r1) # validate acrs
1166	lmg	%r0,%r15,__LC_GPREGS_SAVE_AREA-4095(%r1)# validate gprs
1167	lg	%r12,__LC_CURRENT
1168	larl	%r13,cleanup_critical
1169	lmg	%r8,%r9,__LC_MCK_OLD_PSW
1170	TSTMSK	__LC_MCCK_CODE,MCCK_CODE_SYSTEM_DAMAGE
1171	jo	.Lmcck_panic		# yes -> rest of mcck code invalid
1172	TSTMSK	__LC_MCCK_CODE,MCCK_CODE_CR_VALID
1173	jno	.Lmcck_panic		# control registers invalid -> panic
1174	la	%r14,4095
1175	lctlg	%c0,%c15,__LC_CREGS_SAVE_AREA-4095(%r14) # validate ctl regs
1176	ptlb
1177	lg	%r11,__LC_MCESAD-4095(%r14) # extended machine check save area
1178	nill	%r11,0xfc00		# MCESA_ORIGIN_MASK
1179	TSTMSK	__LC_CREGS_SAVE_AREA+16-4095(%r14),CR2_GUARDED_STORAGE
1180	jno	0f
1181	TSTMSK	__LC_MCCK_CODE,MCCK_CODE_GS_VALID
1182	jno	0f
1183	.insn	 rxy,0xe3000000004d,0,__MCESA_GS_SAVE_AREA(%r11) # LGSC
11840:	l	%r14,__LC_FP_CREG_SAVE_AREA-4095(%r14)
1185	TSTMSK	__LC_MCCK_CODE,MCCK_CODE_FC_VALID
1186	jo	0f
1187	sr	%r14,%r14
11880:	sfpc	%r14
1189	TSTMSK	__LC_MACHINE_FLAGS,MACHINE_FLAG_VX
1190	jo	0f
1191	lghi	%r14,__LC_FPREGS_SAVE_AREA
1192	ld	%f0,0(%r14)
1193	ld	%f1,8(%r14)
1194	ld	%f2,16(%r14)
1195	ld	%f3,24(%r14)
1196	ld	%f4,32(%r14)
1197	ld	%f5,40(%r14)
1198	ld	%f6,48(%r14)
1199	ld	%f7,56(%r14)
1200	ld	%f8,64(%r14)
1201	ld	%f9,72(%r14)
1202	ld	%f10,80(%r14)
1203	ld	%f11,88(%r14)
1204	ld	%f12,96(%r14)
1205	ld	%f13,104(%r14)
1206	ld	%f14,112(%r14)
1207	ld	%f15,120(%r14)
1208	j	1f
12090:	VLM	%v0,%v15,0,%r11
1210	VLM	%v16,%v31,256,%r11
12111:	lghi	%r14,__LC_CPU_TIMER_SAVE_AREA
1212	mvc	__LC_MCCK_ENTER_TIMER(8),0(%r14)
1213	TSTMSK	__LC_MCCK_CODE,MCCK_CODE_CPU_TIMER_VALID
1214	jo	3f
1215	la	%r14,__LC_SYNC_ENTER_TIMER
1216	clc	0(8,%r14),__LC_ASYNC_ENTER_TIMER
1217	jl	0f
1218	la	%r14,__LC_ASYNC_ENTER_TIMER
12190:	clc	0(8,%r14),__LC_EXIT_TIMER
1220	jl	1f
1221	la	%r14,__LC_EXIT_TIMER
12221:	clc	0(8,%r14),__LC_LAST_UPDATE_TIMER
1223	jl	2f
1224	la	%r14,__LC_LAST_UPDATE_TIMER
12252:	spt	0(%r14)
1226	mvc	__LC_MCCK_ENTER_TIMER(8),0(%r14)
12273:	TSTMSK	__LC_MCCK_CODE,MCCK_CODE_PSW_MWP_VALID
1228	jno	.Lmcck_panic
1229	tmhh	%r8,0x0001		# interrupting from user ?
1230	jnz	4f
1231	TSTMSK	__LC_MCCK_CODE,MCCK_CODE_PSW_IA_VALID
1232	jno	.Lmcck_panic
12334:	SWITCH_ASYNC __LC_GPREGS_SAVE_AREA+64,__LC_MCCK_ENTER_TIMER
1234.Lmcck_skip:
1235	lghi	%r14,__LC_GPREGS_SAVE_AREA+64
1236	stmg	%r0,%r7,__PT_R0(%r11)
1237	# clear user controlled registers to prevent speculative use
1238	xgr	%r0,%r0
1239	xgr	%r1,%r1
1240	xgr	%r2,%r2
1241	xgr	%r3,%r3
1242	xgr	%r4,%r4
1243	xgr	%r5,%r5
1244	xgr	%r6,%r6
1245	xgr	%r7,%r7
1246	xgr	%r10,%r10
1247	mvc	__PT_R8(64,%r11),0(%r14)
1248	stmg	%r8,%r9,__PT_PSW(%r11)
1249	xc	__PT_FLAGS(8,%r11),__PT_FLAGS(%r11)
1250	xc	__SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
1251	lgr	%r2,%r11		# pass pointer to pt_regs
1252	brasl	%r14,s390_do_machine_check
1253	tm	__PT_PSW+1(%r11),0x01	# returning to user ?
1254	jno	.Lmcck_return
1255	lg	%r1,__LC_KERNEL_STACK	# switch to kernel stack
1256	mvc	STACK_FRAME_OVERHEAD(__PT_SIZE,%r1),0(%r11)
1257	xc	__SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1)
1258	la	%r11,STACK_FRAME_OVERHEAD(%r1)
1259	lgr	%r15,%r1
1260	ssm	__LC_PGM_NEW_PSW	# turn dat on, keep irqs off
1261	TSTMSK	__LC_CPU_FLAGS,_CIF_MCCK_PENDING
1262	jno	.Lmcck_return
1263	TRACE_IRQS_OFF
1264	brasl	%r14,s390_handle_mcck
1265	TRACE_IRQS_ON
1266.Lmcck_return:
1267	lg	%r14,__LC_VDSO_PER_CPU
1268	lmg	%r0,%r10,__PT_R0(%r11)
1269	mvc	__LC_RETURN_MCCK_PSW(16),__PT_PSW(%r11) # move return PSW
1270	tm	__LC_RETURN_MCCK_PSW+1,0x01 # returning to user ?
1271	jno	0f
1272	BPEXIT	__TI_flags(%r12),_TIF_ISOLATE_BP
1273	stpt	__LC_EXIT_TIMER
1274	mvc	__VDSO_ECTG_BASE(16,%r14),__LC_EXIT_TIMER
12750:	lmg	%r11,%r15,__PT_R11(%r11)
1276	lpswe	__LC_RETURN_MCCK_PSW
1277
1278.Lmcck_panic:
1279	lg	%r15,__LC_PANIC_STACK
1280	la	%r11,STACK_FRAME_OVERHEAD(%r15)
1281	j	.Lmcck_skip
1282
1283#
1284# PSW restart interrupt handler
1285#
1286ENTRY(restart_int_handler)
1287	TSTMSK	__LC_MACHINE_FLAGS,MACHINE_FLAG_LPP
1288	jz	0f
1289	.insn	s,0xb2800000,__LC_LPP
12900:	stg	%r15,__LC_SAVE_AREA_RESTART
1291	lg	%r15,__LC_RESTART_STACK
1292	aghi	%r15,-__PT_SIZE			# create pt_regs on stack
1293	xc	0(__PT_SIZE,%r15),0(%r15)
1294	stmg	%r0,%r14,__PT_R0(%r15)
1295	mvc	__PT_R15(8,%r15),__LC_SAVE_AREA_RESTART
1296	mvc	__PT_PSW(16,%r15),__LC_RST_OLD_PSW # store restart old psw
1297	aghi	%r15,-STACK_FRAME_OVERHEAD	# create stack frame on stack
1298	xc	0(STACK_FRAME_OVERHEAD,%r15),0(%r15)
1299	lg	%r1,__LC_RESTART_FN		# load fn, parm & source cpu
1300	lg	%r2,__LC_RESTART_DATA
1301	lg	%r3,__LC_RESTART_SOURCE
1302	ltgr	%r3,%r3				# test source cpu address
1303	jm	1f				# negative -> skip source stop
13040:	sigp	%r4,%r3,SIGP_SENSE		# sigp sense to source cpu
1305	brc	10,0b				# wait for status stored
13061:	basr	%r14,%r1			# call function
1307	stap	__SF_EMPTY(%r15)		# store cpu address
1308	llgh	%r3,__SF_EMPTY(%r15)
13092:	sigp	%r4,%r3,SIGP_STOP		# sigp stop to current cpu
1310	brc	2,2b
13113:	j	3b
1312
1313	.section .kprobes.text, "ax"
1314
1315#ifdef CONFIG_CHECK_STACK
1316/*
1317 * The synchronous or the asynchronous stack overflowed. We are dead.
1318 * No need to properly save the registers, we are going to panic anyway.
1319 * Setup a pt_regs so that show_trace can provide a good call trace.
1320 */
1321stack_overflow:
1322	lg	%r15,__LC_PANIC_STACK	# change to panic stack
1323	la	%r11,STACK_FRAME_OVERHEAD(%r15)
1324	stmg	%r0,%r7,__PT_R0(%r11)
1325	stmg	%r8,%r9,__PT_PSW(%r11)
1326	mvc	__PT_R8(64,%r11),0(%r14)
1327	stg	%r10,__PT_ORIG_GPR2(%r11) # store last break to orig_gpr2
1328	xc	__SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
1329	lgr	%r2,%r11		# pass pointer to pt_regs
1330	jg	kernel_stack_overflow
1331#endif
1332
1333cleanup_critical:
1334#if IS_ENABLED(CONFIG_KVM)
1335	clg	%r9,BASED(.Lcleanup_table_sie)	# .Lsie_gmap
1336	jl	0f
1337	clg	%r9,BASED(.Lcleanup_table_sie+8)# .Lsie_done
1338	jl	.Lcleanup_sie
1339#endif
1340	clg	%r9,BASED(.Lcleanup_table)	# system_call
1341	jl	0f
1342	clg	%r9,BASED(.Lcleanup_table+8)	# .Lsysc_do_svc
1343	jl	.Lcleanup_system_call
1344	clg	%r9,BASED(.Lcleanup_table+16)	# .Lsysc_tif
1345	jl	0f
1346	clg	%r9,BASED(.Lcleanup_table+24)	# .Lsysc_restore
1347	jl	.Lcleanup_sysc_tif
1348	clg	%r9,BASED(.Lcleanup_table+32)	# .Lsysc_done
1349	jl	.Lcleanup_sysc_restore
1350	clg	%r9,BASED(.Lcleanup_table+40)	# .Lio_tif
1351	jl	0f
1352	clg	%r9,BASED(.Lcleanup_table+48)	# .Lio_restore
1353	jl	.Lcleanup_io_tif
1354	clg	%r9,BASED(.Lcleanup_table+56)	# .Lio_done
1355	jl	.Lcleanup_io_restore
1356	clg	%r9,BASED(.Lcleanup_table+64)	# psw_idle
1357	jl	0f
1358	clg	%r9,BASED(.Lcleanup_table+72)	# .Lpsw_idle_end
1359	jl	.Lcleanup_idle
1360	clg	%r9,BASED(.Lcleanup_table+80)	# save_fpu_regs
1361	jl	0f
1362	clg	%r9,BASED(.Lcleanup_table+88)	# .Lsave_fpu_regs_end
1363	jl	.Lcleanup_save_fpu_regs
1364	clg	%r9,BASED(.Lcleanup_table+96)	# load_fpu_regs
1365	jl	0f
1366	clg	%r9,BASED(.Lcleanup_table+104)	# .Lload_fpu_regs_end
1367	jl	.Lcleanup_load_fpu_regs
13680:	BR_R11USE_R14
1369
1370	.align	8
1371.Lcleanup_table:
1372	.quad	system_call
1373	.quad	.Lsysc_do_svc
1374	.quad	.Lsysc_tif
1375	.quad	.Lsysc_restore
1376	.quad	.Lsysc_done
1377	.quad	.Lio_tif
1378	.quad	.Lio_restore
1379	.quad	.Lio_done
1380	.quad	psw_idle
1381	.quad	.Lpsw_idle_end
1382	.quad	save_fpu_regs
1383	.quad	.Lsave_fpu_regs_end
1384	.quad	load_fpu_regs
1385	.quad	.Lload_fpu_regs_end
1386
1387#if IS_ENABLED(CONFIG_KVM)
1388.Lcleanup_table_sie:
1389	.quad	.Lsie_gmap
1390	.quad	.Lsie_done
1391
1392.Lcleanup_sie:
1393	cghi    %r11,__LC_SAVE_AREA_ASYNC 	#Is this in normal interrupt?
1394	je      1f
1395	slg     %r9,BASED(.Lsie_crit_mcck_start)
1396	clg     %r9,BASED(.Lsie_crit_mcck_length)
1397	jh      1f
1398	oi      __LC_CPU_FLAGS+7, _CIF_MCCK_GUEST
13991:	BPENTER __SF_EMPTY+24(%r15),(_TIF_ISOLATE_BP|_TIF_ISOLATE_BP_GUEST)
1400	lg	%r9,__SF_EMPTY(%r15)		# get control block pointer
1401	ni	__SIE_PROG0C+3(%r9),0xfe	# no longer in SIE
1402	lctlg	%c1,%c1,__LC_USER_ASCE		# load primary asce
1403	larl	%r9,sie_exit			# skip forward to sie_exit
1404	BR_R11USE_R14
1405#endif
1406
1407.Lcleanup_system_call:
1408	# check if stpt has been executed
1409	clg	%r9,BASED(.Lcleanup_system_call_insn)
1410	jh	0f
1411	mvc	__LC_SYNC_ENTER_TIMER(8),__LC_ASYNC_ENTER_TIMER
1412	cghi	%r11,__LC_SAVE_AREA_ASYNC
1413	je	0f
1414	mvc	__LC_SYNC_ENTER_TIMER(8),__LC_MCCK_ENTER_TIMER
14150:	# check if stmg has been executed
1416	clg	%r9,BASED(.Lcleanup_system_call_insn+8)
1417	jh	0f
1418	mvc	__LC_SAVE_AREA_SYNC(64),0(%r11)
14190:	# check if base register setup + TIF bit load has been done
1420	clg	%r9,BASED(.Lcleanup_system_call_insn+16)
1421	jhe	0f
1422	# set up saved register r12 task struct pointer
1423	stg	%r12,32(%r11)
1424	# set up saved register r13 __TASK_thread offset
1425	mvc	40(8,%r11),BASED(.Lcleanup_system_call_const)
14260:	# check if the user time update has been done
1427	clg	%r9,BASED(.Lcleanup_system_call_insn+24)
1428	jh	0f
1429	lg	%r15,__LC_EXIT_TIMER
1430	slg	%r15,__LC_SYNC_ENTER_TIMER
1431	alg	%r15,__LC_USER_TIMER
1432	stg	%r15,__LC_USER_TIMER
14330:	# check if the system time update has been done
1434	clg	%r9,BASED(.Lcleanup_system_call_insn+32)
1435	jh	0f
1436	lg	%r15,__LC_LAST_UPDATE_TIMER
1437	slg	%r15,__LC_EXIT_TIMER
1438	alg	%r15,__LC_SYSTEM_TIMER
1439	stg	%r15,__LC_SYSTEM_TIMER
14400:	# update accounting time stamp
1441	mvc	__LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER
1442	# set up saved register r11
1443	lg	%r15,__LC_KERNEL_STACK
1444	la	%r9,STACK_FRAME_OVERHEAD(%r15)
1445	stg	%r9,24(%r11)		# r11 pt_regs pointer
1446	# fill pt_regs
1447	mvc	__PT_R8(64,%r9),__LC_SAVE_AREA_SYNC
1448	stmg	%r0,%r7,__PT_R0(%r9)
1449	mvc	__PT_PSW(16,%r9),__LC_SVC_OLD_PSW
1450	mvc	__PT_INT_CODE(4,%r9),__LC_SVC_ILC
1451	xc	__PT_FLAGS(8,%r9),__PT_FLAGS(%r9)
1452	mvi	__PT_FLAGS+7(%r9),_PIF_SYSCALL
1453	# setup saved register r15
1454	stg	%r15,56(%r11)		# r15 stack pointer
1455	# set new psw address and exit
1456	larl	%r9,.Lsysc_do_svc
1457	BR_R11USE_R14
1458.Lcleanup_system_call_insn:
1459	.quad	system_call
1460	.quad	.Lsysc_stmg
1461	.quad	.Lsysc_per
1462	.quad	.Lsysc_vtime+36
1463	.quad	.Lsysc_vtime+42
1464.Lcleanup_system_call_const:
1465	.quad	__TASK_thread
1466
1467.Lcleanup_sysc_tif:
1468	larl	%r9,.Lsysc_tif
1469	BR_R11USE_R14
1470
1471.Lcleanup_sysc_restore:
1472	# check if stpt has been executed
1473	clg	%r9,BASED(.Lcleanup_sysc_restore_insn)
1474	jh	0f
1475	mvc	__LC_EXIT_TIMER(8),__LC_ASYNC_ENTER_TIMER
1476	cghi	%r11,__LC_SAVE_AREA_ASYNC
1477	je	0f
1478	mvc	__LC_EXIT_TIMER(8),__LC_MCCK_ENTER_TIMER
14790:	clg	%r9,BASED(.Lcleanup_sysc_restore_insn+8)
1480	je	1f
1481	lg	%r9,24(%r11)		# get saved pointer to pt_regs
1482	mvc	__LC_RETURN_PSW(16),__PT_PSW(%r9)
1483	mvc	0(64,%r11),__PT_R8(%r9)
1484	lmg	%r0,%r7,__PT_R0(%r9)
14851:	lmg	%r8,%r9,__LC_RETURN_PSW
1486	BR_R11USE_R14
1487.Lcleanup_sysc_restore_insn:
1488	.quad	.Lsysc_exit_timer
1489	.quad	.Lsysc_done - 4
1490
1491.Lcleanup_io_tif:
1492	larl	%r9,.Lio_tif
1493	BR_R11USE_R14
1494
1495.Lcleanup_io_restore:
1496	# check if stpt has been executed
1497	clg	%r9,BASED(.Lcleanup_io_restore_insn)
1498	jh	0f
1499	mvc	__LC_EXIT_TIMER(8),__LC_MCCK_ENTER_TIMER
15000:	clg	%r9,BASED(.Lcleanup_io_restore_insn+8)
1501	je	1f
1502	lg	%r9,24(%r11)		# get saved r11 pointer to pt_regs
1503	mvc	__LC_RETURN_PSW(16),__PT_PSW(%r9)
1504	mvc	0(64,%r11),__PT_R8(%r9)
1505	lmg	%r0,%r7,__PT_R0(%r9)
15061:	lmg	%r8,%r9,__LC_RETURN_PSW
1507	BR_R11USE_R14
1508.Lcleanup_io_restore_insn:
1509	.quad	.Lio_exit_timer
1510	.quad	.Lio_done - 4
1511
1512.Lcleanup_idle:
1513	ni	__LC_CPU_FLAGS+7,255-_CIF_ENABLED_WAIT
1514	# copy interrupt clock & cpu timer
1515	mvc	__CLOCK_IDLE_EXIT(8,%r2),__LC_INT_CLOCK
1516	mvc	__TIMER_IDLE_EXIT(8,%r2),__LC_ASYNC_ENTER_TIMER
1517	cghi	%r11,__LC_SAVE_AREA_ASYNC
1518	je	0f
1519	mvc	__CLOCK_IDLE_EXIT(8,%r2),__LC_MCCK_CLOCK
1520	mvc	__TIMER_IDLE_EXIT(8,%r2),__LC_MCCK_ENTER_TIMER
15210:	# check if stck & stpt have been executed
1522	clg	%r9,BASED(.Lcleanup_idle_insn)
1523	jhe	1f
1524	mvc	__CLOCK_IDLE_ENTER(8,%r2),__CLOCK_IDLE_EXIT(%r2)
1525	mvc	__TIMER_IDLE_ENTER(8,%r2),__TIMER_IDLE_EXIT(%r2)
15261:	# calculate idle cycles
1527#ifdef CONFIG_SMP
1528	clg	%r9,BASED(.Lcleanup_idle_insn)
1529	jl	3f
1530	larl	%r1,smp_cpu_mtid
1531	llgf	%r1,0(%r1)
1532	ltgr	%r1,%r1
1533	jz	3f
1534	.insn	rsy,0xeb0000000017,%r1,5,__SF_EMPTY+80(%r15)
1535	larl	%r3,mt_cycles
1536	ag	%r3,__LC_PERCPU_OFFSET
1537	la	%r4,__SF_EMPTY+16(%r15)
15382:	lg	%r0,0(%r3)
1539	slg	%r0,0(%r4)
1540	alg	%r0,64(%r4)
1541	stg	%r0,0(%r3)
1542	la	%r3,8(%r3)
1543	la	%r4,8(%r4)
1544	brct	%r1,2b
1545#endif
15463:	# account system time going idle
1547	lg	%r9,__LC_STEAL_TIMER
1548	alg	%r9,__CLOCK_IDLE_ENTER(%r2)
1549	slg	%r9,__LC_LAST_UPDATE_CLOCK
1550	stg	%r9,__LC_STEAL_TIMER
1551	mvc	__LC_LAST_UPDATE_CLOCK(8),__CLOCK_IDLE_EXIT(%r2)
1552	lg	%r9,__LC_SYSTEM_TIMER
1553	alg	%r9,__LC_LAST_UPDATE_TIMER
1554	slg	%r9,__TIMER_IDLE_ENTER(%r2)
1555	stg	%r9,__LC_SYSTEM_TIMER
1556	mvc	__LC_LAST_UPDATE_TIMER(8),__TIMER_IDLE_EXIT(%r2)
1557	# prepare return psw
1558	nihh	%r8,0xfcfd		# clear irq & wait state bits
1559	lg	%r9,48(%r11)		# return from psw_idle
1560	BR_R11USE_R14
1561.Lcleanup_idle_insn:
1562	.quad	.Lpsw_idle_lpsw
1563
1564.Lcleanup_save_fpu_regs:
1565	larl	%r9,save_fpu_regs
1566	BR_R11USE_R14
1567
1568.Lcleanup_load_fpu_regs:
1569	larl	%r9,load_fpu_regs
1570	BR_R11USE_R14
1571
1572/*
1573 * Integer constants
1574 */
1575	.align	8
1576.Lcritical_start:
1577	.quad	.L__critical_start
1578.Lcritical_length:
1579	.quad	.L__critical_end - .L__critical_start
1580#if IS_ENABLED(CONFIG_KVM)
1581.Lsie_critical_start:
1582	.quad	.Lsie_gmap
1583.Lsie_critical_length:
1584	.quad	.Lsie_done - .Lsie_gmap
1585.Lsie_crit_mcck_start:
1586	.quad   .Lsie_entry
1587.Lsie_crit_mcck_length:
1588	.quad   .Lsie_skip - .Lsie_entry
1589#endif
1590	.section .rodata, "a"
1591#define SYSCALL(esame,emu)	.long esame
1592	.globl	sys_call_table
1593sys_call_table:
1594#include "asm/syscall_table.h"
1595#undef SYSCALL
1596
1597#ifdef CONFIG_COMPAT
1598
1599#define SYSCALL(esame,emu)	.long emu
1600	.globl	sys_call_table_emu
1601sys_call_table_emu:
1602#include "asm/syscall_table.h"
1603#undef SYSCALL
1604#endif
1605