1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * S390 low-level entry points. 4 * 5 * Copyright IBM Corp. 1999, 2012 6 * Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com), 7 * Hartmut Penner (hp@de.ibm.com), 8 * Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com), 9 * Heiko Carstens <heiko.carstens@de.ibm.com> 10 */ 11 12#include <linux/init.h> 13#include <linux/linkage.h> 14#include <asm/processor.h> 15#include <asm/cache.h> 16#include <asm/ctl_reg.h> 17#include <asm/errno.h> 18#include <asm/ptrace.h> 19#include <asm/thread_info.h> 20#include <asm/asm-offsets.h> 21#include <asm/unistd.h> 22#include <asm/page.h> 23#include <asm/sigp.h> 24#include <asm/irq.h> 25#include <asm/vx-insn.h> 26#include <asm/setup.h> 27#include <asm/nmi.h> 28#include <asm/export.h> 29 30__PT_R0 = __PT_GPRS 31__PT_R1 = __PT_GPRS + 8 32__PT_R2 = __PT_GPRS + 16 33__PT_R3 = __PT_GPRS + 24 34__PT_R4 = __PT_GPRS + 32 35__PT_R5 = __PT_GPRS + 40 36__PT_R6 = __PT_GPRS + 48 37__PT_R7 = __PT_GPRS + 56 38__PT_R8 = __PT_GPRS + 64 39__PT_R9 = __PT_GPRS + 72 40__PT_R10 = __PT_GPRS + 80 41__PT_R11 = __PT_GPRS + 88 42__PT_R12 = __PT_GPRS + 96 43__PT_R13 = __PT_GPRS + 104 44__PT_R14 = __PT_GPRS + 112 45__PT_R15 = __PT_GPRS + 120 46 47STACK_SHIFT = PAGE_SHIFT + THREAD_SIZE_ORDER 48STACK_SIZE = 1 << STACK_SHIFT 49STACK_INIT = STACK_SIZE - STACK_FRAME_OVERHEAD - __PT_SIZE 50 51_TIF_WORK = (_TIF_SIGPENDING | _TIF_NOTIFY_RESUME | _TIF_NEED_RESCHED | \ 52 _TIF_UPROBE | _TIF_GUARDED_STORAGE | _TIF_PATCH_PENDING) 53_TIF_TRACE = (_TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT | _TIF_SECCOMP | \ 54 _TIF_SYSCALL_TRACEPOINT) 55_CIF_WORK = (_CIF_MCCK_PENDING | _CIF_ASCE_PRIMARY | \ 56 _CIF_ASCE_SECONDARY | _CIF_FPU) 57_PIF_WORK = (_PIF_PER_TRAP | _PIF_SYSCALL_RESTART) 58 59#define BASED(name) name-cleanup_critical(%r13) 60 61 .macro TRACE_IRQS_ON 62#ifdef CONFIG_TRACE_IRQFLAGS 63 basr %r2,%r0 64 brasl %r14,trace_hardirqs_on_caller 65#endif 66 .endm 67 68 .macro TRACE_IRQS_OFF 69#ifdef CONFIG_TRACE_IRQFLAGS 70 basr %r2,%r0 71 brasl %r14,trace_hardirqs_off_caller 72#endif 73 .endm 74 75 .macro LOCKDEP_SYS_EXIT 76#ifdef CONFIG_LOCKDEP 77 tm __PT_PSW+1(%r11),0x01 # returning to user ? 78 jz .+10 79 brasl %r14,lockdep_sys_exit 80#endif 81 .endm 82 83 .macro CHECK_STACK stacksize,savearea 84#ifdef CONFIG_CHECK_STACK 85 tml %r15,\stacksize - CONFIG_STACK_GUARD 86 lghi %r14,\savearea 87 jz stack_overflow 88#endif 89 .endm 90 91 .macro SWITCH_ASYNC savearea,timer 92 tmhh %r8,0x0001 # interrupting from user ? 93 jnz 1f 94 lgr %r14,%r9 95 slg %r14,BASED(.Lcritical_start) 96 clg %r14,BASED(.Lcritical_length) 97 jhe 0f 98 lghi %r11,\savearea # inside critical section, do cleanup 99 brasl %r14,cleanup_critical 100 tmhh %r8,0x0001 # retest problem state after cleanup 101 jnz 1f 1020: lg %r14,__LC_ASYNC_STACK # are we already on the async stack? 103 slgr %r14,%r15 104 srag %r14,%r14,STACK_SHIFT 105 jnz 2f 106 CHECK_STACK 1<<STACK_SHIFT,\savearea 107 aghi %r15,-(STACK_FRAME_OVERHEAD + __PT_SIZE) 108 j 3f 1091: UPDATE_VTIME %r14,%r15,\timer 1102: lg %r15,__LC_ASYNC_STACK # load async stack 1113: la %r11,STACK_FRAME_OVERHEAD(%r15) 112 .endm 113 114 .macro UPDATE_VTIME w1,w2,enter_timer 115 lg \w1,__LC_EXIT_TIMER 116 lg \w2,__LC_LAST_UPDATE_TIMER 117 slg \w1,\enter_timer 118 slg \w2,__LC_EXIT_TIMER 119 alg \w1,__LC_USER_TIMER 120 alg \w2,__LC_SYSTEM_TIMER 121 stg \w1,__LC_USER_TIMER 122 stg \w2,__LC_SYSTEM_TIMER 123 mvc __LC_LAST_UPDATE_TIMER(8),\enter_timer 124 .endm 125 126 .macro REENABLE_IRQS 127 stg %r8,__LC_RETURN_PSW 128 ni __LC_RETURN_PSW,0xbf 129 ssm __LC_RETURN_PSW 130 .endm 131 132 .macro STCK savearea 133#ifdef CONFIG_HAVE_MARCH_Z9_109_FEATURES 134 .insn s,0xb27c0000,\savearea # store clock fast 135#else 136 .insn s,0xb2050000,\savearea # store clock 137#endif 138 .endm 139 140 /* 141 * The TSTMSK macro generates a test-under-mask instruction by 142 * calculating the memory offset for the specified mask value. 143 * Mask value can be any constant. The macro shifts the mask 144 * value to calculate the memory offset for the test-under-mask 145 * instruction. 146 */ 147 .macro TSTMSK addr, mask, size=8, bytepos=0 148 .if (\bytepos < \size) && (\mask >> 8) 149 .if (\mask & 0xff) 150 .error "Mask exceeds byte boundary" 151 .endif 152 TSTMSK \addr, "(\mask >> 8)", \size, "(\bytepos + 1)" 153 .exitm 154 .endif 155 .ifeq \mask 156 .error "Mask must not be zero" 157 .endif 158 off = \size - \bytepos - 1 159 tm off+\addr, \mask 160 .endm 161 162 .section .kprobes.text, "ax" 163.Ldummy: 164 /* 165 * This nop exists only in order to avoid that __switch_to starts at 166 * the beginning of the kprobes text section. In that case we would 167 * have several symbols at the same address. E.g. objdump would take 168 * an arbitrary symbol name when disassembling this code. 169 * With the added nop in between the __switch_to symbol is unique 170 * again. 171 */ 172 nop 0 173 174/* 175 * Scheduler resume function, called by switch_to 176 * gpr2 = (task_struct *) prev 177 * gpr3 = (task_struct *) next 178 * Returns: 179 * gpr2 = prev 180 */ 181ENTRY(__switch_to) 182 stmg %r6,%r15,__SF_GPRS(%r15) # store gprs of prev task 183 lgr %r1,%r2 184 aghi %r1,__TASK_thread # thread_struct of prev task 185 lg %r5,__TASK_stack(%r3) # start of kernel stack of next 186 stg %r15,__THREAD_ksp(%r1) # store kernel stack of prev 187 lgr %r1,%r3 188 aghi %r1,__TASK_thread # thread_struct of next task 189 lgr %r15,%r5 190 aghi %r15,STACK_INIT # end of kernel stack of next 191 stg %r3,__LC_CURRENT # store task struct of next 192 stg %r15,__LC_KERNEL_STACK # store end of kernel stack 193 lg %r15,__THREAD_ksp(%r1) # load kernel stack of next 194 mvc __LC_CURRENT_PID(4,%r0),__TASK_pid(%r3) # store pid of next 195 lmg %r6,%r15,__SF_GPRS(%r15) # load gprs of next task 196 TSTMSK __LC_MACHINE_FLAGS,MACHINE_FLAG_LPP 197 bzr %r14 198 .insn s,0xb2800000,__LC_LPP # set program parameter 199 br %r14 200 201.L__critical_start: 202 203#if IS_ENABLED(CONFIG_KVM) 204/* 205 * sie64a calling convention: 206 * %r2 pointer to sie control block 207 * %r3 guest register save area 208 */ 209ENTRY(sie64a) 210 stmg %r6,%r14,__SF_GPRS(%r15) # save kernel registers 211 stg %r2,__SF_EMPTY(%r15) # save control block pointer 212 stg %r3,__SF_EMPTY+8(%r15) # save guest register save area 213 xc __SF_EMPTY+16(8,%r15),__SF_EMPTY+16(%r15) # reason code = 0 214 TSTMSK __LC_CPU_FLAGS,_CIF_FPU # load guest fp/vx registers ? 215 jno .Lsie_load_guest_gprs 216 brasl %r14,load_fpu_regs # load guest fp/vx regs 217.Lsie_load_guest_gprs: 218 lmg %r0,%r13,0(%r3) # load guest gprs 0-13 219 lg %r14,__LC_GMAP # get gmap pointer 220 ltgr %r14,%r14 221 jz .Lsie_gmap 222 lctlg %c1,%c1,__GMAP_ASCE(%r14) # load primary asce 223.Lsie_gmap: 224 lg %r14,__SF_EMPTY(%r15) # get control block pointer 225 oi __SIE_PROG0C+3(%r14),1 # we are going into SIE now 226 tm __SIE_PROG20+3(%r14),3 # last exit... 227 jnz .Lsie_skip 228 TSTMSK __LC_CPU_FLAGS,_CIF_FPU 229 jo .Lsie_skip # exit if fp/vx regs changed 230.Lsie_entry: 231 sie 0(%r14) 232.Lsie_skip: 233 ni __SIE_PROG0C+3(%r14),0xfe # no longer in SIE 234 lctlg %c1,%c1,__LC_USER_ASCE # load primary asce 235.Lsie_done: 236# some program checks are suppressing. C code (e.g. do_protection_exception) 237# will rewind the PSW by the ILC, which is often 4 bytes in case of SIE. There 238# are some corner cases (e.g. runtime instrumentation) where ILC is unpredictable. 239# Other instructions between sie64a and .Lsie_done should not cause program 240# interrupts. So lets use 3 nops as a landing pad for all possible rewinds. 241# See also .Lcleanup_sie 242.Lrewind_pad6: 243 nopr 7 244.Lrewind_pad4: 245 nopr 7 246.Lrewind_pad2: 247 nopr 7 248 .globl sie_exit 249sie_exit: 250 lg %r14,__SF_EMPTY+8(%r15) # load guest register save area 251 stmg %r0,%r13,0(%r14) # save guest gprs 0-13 252 lmg %r6,%r14,__SF_GPRS(%r15) # restore kernel registers 253 lg %r2,__SF_EMPTY+16(%r15) # return exit reason code 254 br %r14 255.Lsie_fault: 256 lghi %r14,-EFAULT 257 stg %r14,__SF_EMPTY+16(%r15) # set exit reason code 258 j sie_exit 259 260 EX_TABLE(.Lrewind_pad6,.Lsie_fault) 261 EX_TABLE(.Lrewind_pad4,.Lsie_fault) 262 EX_TABLE(.Lrewind_pad2,.Lsie_fault) 263 EX_TABLE(sie_exit,.Lsie_fault) 264EXPORT_SYMBOL(sie64a) 265EXPORT_SYMBOL(sie_exit) 266#endif 267 268/* 269 * SVC interrupt handler routine. System calls are synchronous events and 270 * are executed with interrupts enabled. 271 */ 272 273ENTRY(system_call) 274 stpt __LC_SYNC_ENTER_TIMER 275.Lsysc_stmg: 276 stmg %r8,%r15,__LC_SAVE_AREA_SYNC 277 lg %r12,__LC_CURRENT 278 lghi %r13,__TASK_thread 279 lghi %r14,_PIF_SYSCALL 280.Lsysc_per: 281 lg %r15,__LC_KERNEL_STACK 282 la %r11,STACK_FRAME_OVERHEAD(%r15) # pointer to pt_regs 283.Lsysc_vtime: 284 UPDATE_VTIME %r8,%r9,__LC_SYNC_ENTER_TIMER 285 stmg %r0,%r7,__PT_R0(%r11) 286 mvc __PT_R8(64,%r11),__LC_SAVE_AREA_SYNC 287 mvc __PT_PSW(16,%r11),__LC_SVC_OLD_PSW 288 mvc __PT_INT_CODE(4,%r11),__LC_SVC_ILC 289 stg %r14,__PT_FLAGS(%r11) 290.Lsysc_do_svc: 291 # load address of system call table 292 lg %r10,__THREAD_sysc_table(%r13,%r12) 293 llgh %r8,__PT_INT_CODE+2(%r11) 294 slag %r8,%r8,2 # shift and test for svc 0 295 jnz .Lsysc_nr_ok 296 # svc 0: system call number in %r1 297 llgfr %r1,%r1 # clear high word in r1 298 cghi %r1,NR_syscalls 299 jnl .Lsysc_nr_ok 300 sth %r1,__PT_INT_CODE+2(%r11) 301 slag %r8,%r1,2 302.Lsysc_nr_ok: 303 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15) 304 stg %r2,__PT_ORIG_GPR2(%r11) 305 stg %r7,STACK_FRAME_OVERHEAD(%r15) 306 lgf %r9,0(%r8,%r10) # get system call add. 307 TSTMSK __TI_flags(%r12),_TIF_TRACE 308 jnz .Lsysc_tracesys 309 basr %r14,%r9 # call sys_xxxx 310 stg %r2,__PT_R2(%r11) # store return value 311 312.Lsysc_return: 313 LOCKDEP_SYS_EXIT 314.Lsysc_tif: 315 TSTMSK __PT_FLAGS(%r11),_PIF_WORK 316 jnz .Lsysc_work 317 TSTMSK __TI_flags(%r12),_TIF_WORK 318 jnz .Lsysc_work # check for work 319 TSTMSK __LC_CPU_FLAGS,_CIF_WORK 320 jnz .Lsysc_work 321.Lsysc_restore: 322 lg %r14,__LC_VDSO_PER_CPU 323 lmg %r0,%r10,__PT_R0(%r11) 324 mvc __LC_RETURN_PSW(16),__PT_PSW(%r11) 325.Lsysc_exit_timer: 326 stpt __LC_EXIT_TIMER 327 mvc __VDSO_ECTG_BASE(16,%r14),__LC_EXIT_TIMER 328 lmg %r11,%r15,__PT_R11(%r11) 329 lpswe __LC_RETURN_PSW 330.Lsysc_done: 331 332# 333# One of the work bits is on. Find out which one. 334# 335.Lsysc_work: 336 TSTMSK __LC_CPU_FLAGS,_CIF_MCCK_PENDING 337 jo .Lsysc_mcck_pending 338 TSTMSK __TI_flags(%r12),_TIF_NEED_RESCHED 339 jo .Lsysc_reschedule 340 TSTMSK __PT_FLAGS(%r11),_PIF_SYSCALL_RESTART 341 jo .Lsysc_syscall_restart 342#ifdef CONFIG_UPROBES 343 TSTMSK __TI_flags(%r12),_TIF_UPROBE 344 jo .Lsysc_uprobe_notify 345#endif 346 TSTMSK __TI_flags(%r12),_TIF_GUARDED_STORAGE 347 jo .Lsysc_guarded_storage 348 TSTMSK __PT_FLAGS(%r11),_PIF_PER_TRAP 349 jo .Lsysc_singlestep 350#ifdef CONFIG_LIVEPATCH 351 TSTMSK __TI_flags(%r12),_TIF_PATCH_PENDING 352 jo .Lsysc_patch_pending # handle live patching just before 353 # signals and possible syscall restart 354#endif 355 TSTMSK __PT_FLAGS(%r11),_PIF_SYSCALL_RESTART 356 jo .Lsysc_syscall_restart 357 TSTMSK __TI_flags(%r12),_TIF_SIGPENDING 358 jo .Lsysc_sigpending 359 TSTMSK __TI_flags(%r12),_TIF_NOTIFY_RESUME 360 jo .Lsysc_notify_resume 361 TSTMSK __LC_CPU_FLAGS,_CIF_FPU 362 jo .Lsysc_vxrs 363 TSTMSK __LC_CPU_FLAGS,(_CIF_ASCE_PRIMARY|_CIF_ASCE_SECONDARY) 364 jnz .Lsysc_asce 365 j .Lsysc_return # beware of critical section cleanup 366 367# 368# _TIF_NEED_RESCHED is set, call schedule 369# 370.Lsysc_reschedule: 371 larl %r14,.Lsysc_return 372 jg schedule 373 374# 375# _CIF_MCCK_PENDING is set, call handler 376# 377.Lsysc_mcck_pending: 378 larl %r14,.Lsysc_return 379 jg s390_handle_mcck # TIF bit will be cleared by handler 380 381# 382# _CIF_ASCE_PRIMARY and/or _CIF_ASCE_SECONDARY set, load user space asce 383# 384.Lsysc_asce: 385 ni __LC_CPU_FLAGS+7,255-_CIF_ASCE_SECONDARY 386 lctlg %c7,%c7,__LC_VDSO_ASCE # load secondary asce 387 TSTMSK __LC_CPU_FLAGS,_CIF_ASCE_PRIMARY 388 jz .Lsysc_return 389#ifndef CONFIG_HAVE_MARCH_Z10_FEATURES 390 tm __LC_STFLE_FAC_LIST+3,0x10 # has MVCOS ? 391 jnz .Lsysc_set_fs_fixup 392 ni __LC_CPU_FLAGS+7,255-_CIF_ASCE_PRIMARY 393 lctlg %c1,%c1,__LC_USER_ASCE # load primary asce 394 j .Lsysc_return 395.Lsysc_set_fs_fixup: 396#endif 397 larl %r14,.Lsysc_return 398 jg set_fs_fixup 399 400# 401# CIF_FPU is set, restore floating-point controls and floating-point registers. 402# 403.Lsysc_vxrs: 404 larl %r14,.Lsysc_return 405 jg load_fpu_regs 406 407# 408# _TIF_SIGPENDING is set, call do_signal 409# 410.Lsysc_sigpending: 411 lgr %r2,%r11 # pass pointer to pt_regs 412 brasl %r14,do_signal 413 TSTMSK __PT_FLAGS(%r11),_PIF_SYSCALL 414 jno .Lsysc_return 415.Lsysc_do_syscall: 416 lghi %r13,__TASK_thread 417 lmg %r2,%r7,__PT_R2(%r11) # load svc arguments 418 lghi %r1,0 # svc 0 returns -ENOSYS 419 j .Lsysc_do_svc 420 421# 422# _TIF_NOTIFY_RESUME is set, call do_notify_resume 423# 424.Lsysc_notify_resume: 425 lgr %r2,%r11 # pass pointer to pt_regs 426 larl %r14,.Lsysc_return 427 jg do_notify_resume 428 429# 430# _TIF_UPROBE is set, call uprobe_notify_resume 431# 432#ifdef CONFIG_UPROBES 433.Lsysc_uprobe_notify: 434 lgr %r2,%r11 # pass pointer to pt_regs 435 larl %r14,.Lsysc_return 436 jg uprobe_notify_resume 437#endif 438 439# 440# _TIF_GUARDED_STORAGE is set, call guarded_storage_load 441# 442.Lsysc_guarded_storage: 443 lgr %r2,%r11 # pass pointer to pt_regs 444 larl %r14,.Lsysc_return 445 jg gs_load_bc_cb 446# 447# _TIF_PATCH_PENDING is set, call klp_update_patch_state 448# 449#ifdef CONFIG_LIVEPATCH 450.Lsysc_patch_pending: 451 lg %r2,__LC_CURRENT # pass pointer to task struct 452 larl %r14,.Lsysc_return 453 jg klp_update_patch_state 454#endif 455 456# 457# _PIF_PER_TRAP is set, call do_per_trap 458# 459.Lsysc_singlestep: 460 ni __PT_FLAGS+7(%r11),255-_PIF_PER_TRAP 461 lgr %r2,%r11 # pass pointer to pt_regs 462 larl %r14,.Lsysc_return 463 jg do_per_trap 464 465# 466# _PIF_SYSCALL_RESTART is set, repeat the current system call 467# 468.Lsysc_syscall_restart: 469 ni __PT_FLAGS+7(%r11),255-_PIF_SYSCALL_RESTART 470 lmg %r1,%r7,__PT_R1(%r11) # load svc arguments 471 lg %r2,__PT_ORIG_GPR2(%r11) 472 j .Lsysc_do_svc 473 474# 475# call tracehook_report_syscall_entry/tracehook_report_syscall_exit before 476# and after the system call 477# 478.Lsysc_tracesys: 479 lgr %r2,%r11 # pass pointer to pt_regs 480 la %r3,0 481 llgh %r0,__PT_INT_CODE+2(%r11) 482 stg %r0,__PT_R2(%r11) 483 brasl %r14,do_syscall_trace_enter 484 lghi %r0,NR_syscalls 485 clgr %r0,%r2 486 jnh .Lsysc_tracenogo 487 sllg %r8,%r2,2 488 lgf %r9,0(%r8,%r10) 489.Lsysc_tracego: 490 lmg %r3,%r7,__PT_R3(%r11) 491 stg %r7,STACK_FRAME_OVERHEAD(%r15) 492 lg %r2,__PT_ORIG_GPR2(%r11) 493 basr %r14,%r9 # call sys_xxx 494 stg %r2,__PT_R2(%r11) # store return value 495.Lsysc_tracenogo: 496 TSTMSK __TI_flags(%r12),_TIF_TRACE 497 jz .Lsysc_return 498 lgr %r2,%r11 # pass pointer to pt_regs 499 larl %r14,.Lsysc_return 500 jg do_syscall_trace_exit 501 502# 503# a new process exits the kernel with ret_from_fork 504# 505ENTRY(ret_from_fork) 506 la %r11,STACK_FRAME_OVERHEAD(%r15) 507 lg %r12,__LC_CURRENT 508 brasl %r14,schedule_tail 509 TRACE_IRQS_ON 510 ssm __LC_SVC_NEW_PSW # reenable interrupts 511 tm __PT_PSW+1(%r11),0x01 # forking a kernel thread ? 512 jne .Lsysc_tracenogo 513 # it's a kernel thread 514 lmg %r9,%r10,__PT_R9(%r11) # load gprs 515ENTRY(kernel_thread_starter) 516 la %r2,0(%r10) 517 basr %r14,%r9 518 j .Lsysc_tracenogo 519 520/* 521 * Program check handler routine 522 */ 523 524ENTRY(pgm_check_handler) 525 stpt __LC_SYNC_ENTER_TIMER 526 stmg %r8,%r15,__LC_SAVE_AREA_SYNC 527 lg %r10,__LC_LAST_BREAK 528 lg %r12,__LC_CURRENT 529 lghi %r11,0 530 larl %r13,cleanup_critical 531 lmg %r8,%r9,__LC_PGM_OLD_PSW 532 tmhh %r8,0x0001 # test problem state bit 533 jnz 2f # -> fault in user space 534#if IS_ENABLED(CONFIG_KVM) 535 # cleanup critical section for program checks in sie64a 536 lgr %r14,%r9 537 slg %r14,BASED(.Lsie_critical_start) 538 clg %r14,BASED(.Lsie_critical_length) 539 jhe 0f 540 lg %r14,__SF_EMPTY(%r15) # get control block pointer 541 ni __SIE_PROG0C+3(%r14),0xfe # no longer in SIE 542 lctlg %c1,%c1,__LC_USER_ASCE # load primary asce 543 larl %r9,sie_exit # skip forward to sie_exit 544 lghi %r11,_PIF_GUEST_FAULT 545#endif 5460: tmhh %r8,0x4000 # PER bit set in old PSW ? 547 jnz 1f # -> enabled, can't be a double fault 548 tm __LC_PGM_ILC+3,0x80 # check for per exception 549 jnz .Lpgm_svcper # -> single stepped svc 5501: CHECK_STACK STACK_SIZE,__LC_SAVE_AREA_SYNC 551 aghi %r15,-(STACK_FRAME_OVERHEAD + __PT_SIZE) 552 j 4f 5532: UPDATE_VTIME %r14,%r15,__LC_SYNC_ENTER_TIMER 554 lg %r15,__LC_KERNEL_STACK 555 lgr %r14,%r12 556 aghi %r14,__TASK_thread # pointer to thread_struct 557 lghi %r13,__LC_PGM_TDB 558 tm __LC_PGM_ILC+2,0x02 # check for transaction abort 559 jz 3f 560 mvc __THREAD_trap_tdb(256,%r14),0(%r13) 5613: stg %r10,__THREAD_last_break(%r14) 5624: lgr %r13,%r11 563 la %r11,STACK_FRAME_OVERHEAD(%r15) 564 stmg %r0,%r7,__PT_R0(%r11) 565 mvc __PT_R8(64,%r11),__LC_SAVE_AREA_SYNC 566 stmg %r8,%r9,__PT_PSW(%r11) 567 mvc __PT_INT_CODE(4,%r11),__LC_PGM_ILC 568 mvc __PT_INT_PARM_LONG(8,%r11),__LC_TRANS_EXC_CODE 569 stg %r13,__PT_FLAGS(%r11) 570 stg %r10,__PT_ARGS(%r11) 571 tm __LC_PGM_ILC+3,0x80 # check for per exception 572 jz 5f 573 tmhh %r8,0x0001 # kernel per event ? 574 jz .Lpgm_kprobe 575 oi __PT_FLAGS+7(%r11),_PIF_PER_TRAP 576 mvc __THREAD_per_address(8,%r14),__LC_PER_ADDRESS 577 mvc __THREAD_per_cause(2,%r14),__LC_PER_CODE 578 mvc __THREAD_per_paid(1,%r14),__LC_PER_ACCESS_ID 5795: REENABLE_IRQS 580 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15) 581 larl %r1,pgm_check_table 582 llgh %r10,__PT_INT_CODE+2(%r11) 583 nill %r10,0x007f 584 sll %r10,2 585 je .Lpgm_return 586 lgf %r1,0(%r10,%r1) # load address of handler routine 587 lgr %r2,%r11 # pass pointer to pt_regs 588 basr %r14,%r1 # branch to interrupt-handler 589.Lpgm_return: 590 LOCKDEP_SYS_EXIT 591 tm __PT_PSW+1(%r11),0x01 # returning to user ? 592 jno .Lsysc_restore 593 TSTMSK __PT_FLAGS(%r11),_PIF_SYSCALL 594 jo .Lsysc_do_syscall 595 j .Lsysc_tif 596 597# 598# PER event in supervisor state, must be kprobes 599# 600.Lpgm_kprobe: 601 REENABLE_IRQS 602 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15) 603 lgr %r2,%r11 # pass pointer to pt_regs 604 brasl %r14,do_per_trap 605 j .Lpgm_return 606 607# 608# single stepped system call 609# 610.Lpgm_svcper: 611 mvc __LC_RETURN_PSW(8),__LC_SVC_NEW_PSW 612 lghi %r13,__TASK_thread 613 larl %r14,.Lsysc_per 614 stg %r14,__LC_RETURN_PSW+8 615 lghi %r14,_PIF_SYSCALL | _PIF_PER_TRAP 616 lpswe __LC_RETURN_PSW # branch to .Lsysc_per and enable irqs 617 618/* 619 * IO interrupt handler routine 620 */ 621ENTRY(io_int_handler) 622 STCK __LC_INT_CLOCK 623 stpt __LC_ASYNC_ENTER_TIMER 624 stmg %r8,%r15,__LC_SAVE_AREA_ASYNC 625 lg %r12,__LC_CURRENT 626 larl %r13,cleanup_critical 627 lmg %r8,%r9,__LC_IO_OLD_PSW 628 SWITCH_ASYNC __LC_SAVE_AREA_ASYNC,__LC_ASYNC_ENTER_TIMER 629 stmg %r0,%r7,__PT_R0(%r11) 630 mvc __PT_R8(64,%r11),__LC_SAVE_AREA_ASYNC 631 stmg %r8,%r9,__PT_PSW(%r11) 632 mvc __PT_INT_CODE(12,%r11),__LC_SUBCHANNEL_ID 633 xc __PT_FLAGS(8,%r11),__PT_FLAGS(%r11) 634 TSTMSK __LC_CPU_FLAGS,_CIF_IGNORE_IRQ 635 jo .Lio_restore 636 TRACE_IRQS_OFF 637 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15) 638.Lio_loop: 639 lgr %r2,%r11 # pass pointer to pt_regs 640 lghi %r3,IO_INTERRUPT 641 tm __PT_INT_CODE+8(%r11),0x80 # adapter interrupt ? 642 jz .Lio_call 643 lghi %r3,THIN_INTERRUPT 644.Lio_call: 645 brasl %r14,do_IRQ 646 TSTMSK __LC_MACHINE_FLAGS,MACHINE_FLAG_LPAR 647 jz .Lio_return 648 tpi 0 649 jz .Lio_return 650 mvc __PT_INT_CODE(12,%r11),__LC_SUBCHANNEL_ID 651 j .Lio_loop 652.Lio_return: 653 LOCKDEP_SYS_EXIT 654 TRACE_IRQS_ON 655.Lio_tif: 656 TSTMSK __TI_flags(%r12),_TIF_WORK 657 jnz .Lio_work # there is work to do (signals etc.) 658 TSTMSK __LC_CPU_FLAGS,_CIF_WORK 659 jnz .Lio_work 660.Lio_restore: 661 lg %r14,__LC_VDSO_PER_CPU 662 lmg %r0,%r10,__PT_R0(%r11) 663 mvc __LC_RETURN_PSW(16),__PT_PSW(%r11) 664.Lio_exit_timer: 665 stpt __LC_EXIT_TIMER 666 mvc __VDSO_ECTG_BASE(16,%r14),__LC_EXIT_TIMER 667 lmg %r11,%r15,__PT_R11(%r11) 668 lpswe __LC_RETURN_PSW 669.Lio_done: 670 671# 672# There is work todo, find out in which context we have been interrupted: 673# 1) if we return to user space we can do all _TIF_WORK work 674# 2) if we return to kernel code and kvm is enabled check if we need to 675# modify the psw to leave SIE 676# 3) if we return to kernel code and preemptive scheduling is enabled check 677# the preemption counter and if it is zero call preempt_schedule_irq 678# Before any work can be done, a switch to the kernel stack is required. 679# 680.Lio_work: 681 tm __PT_PSW+1(%r11),0x01 # returning to user ? 682 jo .Lio_work_user # yes -> do resched & signal 683#ifdef CONFIG_PREEMPT 684 # check for preemptive scheduling 685 icm %r0,15,__LC_PREEMPT_COUNT 686 jnz .Lio_restore # preemption is disabled 687 TSTMSK __TI_flags(%r12),_TIF_NEED_RESCHED 688 jno .Lio_restore 689 # switch to kernel stack 690 lg %r1,__PT_R15(%r11) 691 aghi %r1,-(STACK_FRAME_OVERHEAD + __PT_SIZE) 692 mvc STACK_FRAME_OVERHEAD(__PT_SIZE,%r1),0(%r11) 693 xc __SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1) 694 la %r11,STACK_FRAME_OVERHEAD(%r1) 695 lgr %r15,%r1 696 # TRACE_IRQS_ON already done at .Lio_return, call 697 # TRACE_IRQS_OFF to keep things symmetrical 698 TRACE_IRQS_OFF 699 brasl %r14,preempt_schedule_irq 700 j .Lio_return 701#else 702 j .Lio_restore 703#endif 704 705# 706# Need to do work before returning to userspace, switch to kernel stack 707# 708.Lio_work_user: 709 lg %r1,__LC_KERNEL_STACK 710 mvc STACK_FRAME_OVERHEAD(__PT_SIZE,%r1),0(%r11) 711 xc __SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1) 712 la %r11,STACK_FRAME_OVERHEAD(%r1) 713 lgr %r15,%r1 714 715# 716# One of the work bits is on. Find out which one. 717# 718.Lio_work_tif: 719 TSTMSK __LC_CPU_FLAGS,_CIF_MCCK_PENDING 720 jo .Lio_mcck_pending 721 TSTMSK __TI_flags(%r12),_TIF_NEED_RESCHED 722 jo .Lio_reschedule 723#ifdef CONFIG_LIVEPATCH 724 TSTMSK __TI_flags(%r12),_TIF_PATCH_PENDING 725 jo .Lio_patch_pending 726#endif 727 TSTMSK __TI_flags(%r12),_TIF_SIGPENDING 728 jo .Lio_sigpending 729 TSTMSK __TI_flags(%r12),_TIF_NOTIFY_RESUME 730 jo .Lio_notify_resume 731 TSTMSK __TI_flags(%r12),_TIF_GUARDED_STORAGE 732 jo .Lio_guarded_storage 733 TSTMSK __LC_CPU_FLAGS,_CIF_FPU 734 jo .Lio_vxrs 735 TSTMSK __LC_CPU_FLAGS,(_CIF_ASCE_PRIMARY|_CIF_ASCE_SECONDARY) 736 jnz .Lio_asce 737 j .Lio_return # beware of critical section cleanup 738 739# 740# _CIF_MCCK_PENDING is set, call handler 741# 742.Lio_mcck_pending: 743 # TRACE_IRQS_ON already done at .Lio_return 744 brasl %r14,s390_handle_mcck # TIF bit will be cleared by handler 745 TRACE_IRQS_OFF 746 j .Lio_return 747 748# 749# _CIF_ASCE_PRIMARY and/or CIF_ASCE_SECONDARY set, load user space asce 750# 751.Lio_asce: 752 ni __LC_CPU_FLAGS+7,255-_CIF_ASCE_SECONDARY 753 lctlg %c7,%c7,__LC_VDSO_ASCE # load secondary asce 754 TSTMSK __LC_CPU_FLAGS,_CIF_ASCE_PRIMARY 755 jz .Lio_return 756#ifndef CONFIG_HAVE_MARCH_Z10_FEATURES 757 tm __LC_STFLE_FAC_LIST+3,0x10 # has MVCOS ? 758 jnz .Lio_set_fs_fixup 759 ni __LC_CPU_FLAGS+7,255-_CIF_ASCE_PRIMARY 760 lctlg %c1,%c1,__LC_USER_ASCE # load primary asce 761 j .Lio_return 762.Lio_set_fs_fixup: 763#endif 764 larl %r14,.Lio_return 765 jg set_fs_fixup 766 767# 768# CIF_FPU is set, restore floating-point controls and floating-point registers. 769# 770.Lio_vxrs: 771 larl %r14,.Lio_return 772 jg load_fpu_regs 773 774# 775# _TIF_GUARDED_STORAGE is set, call guarded_storage_load 776# 777.Lio_guarded_storage: 778 # TRACE_IRQS_ON already done at .Lio_return 779 ssm __LC_SVC_NEW_PSW # reenable interrupts 780 lgr %r2,%r11 # pass pointer to pt_regs 781 brasl %r14,gs_load_bc_cb 782 ssm __LC_PGM_NEW_PSW # disable I/O and ext. interrupts 783 TRACE_IRQS_OFF 784 j .Lio_return 785 786# 787# _TIF_NEED_RESCHED is set, call schedule 788# 789.Lio_reschedule: 790 # TRACE_IRQS_ON already done at .Lio_return 791 ssm __LC_SVC_NEW_PSW # reenable interrupts 792 brasl %r14,schedule # call scheduler 793 ssm __LC_PGM_NEW_PSW # disable I/O and ext. interrupts 794 TRACE_IRQS_OFF 795 j .Lio_return 796 797# 798# _TIF_PATCH_PENDING is set, call klp_update_patch_state 799# 800#ifdef CONFIG_LIVEPATCH 801.Lio_patch_pending: 802 lg %r2,__LC_CURRENT # pass pointer to task struct 803 larl %r14,.Lio_return 804 jg klp_update_patch_state 805#endif 806 807# 808# _TIF_SIGPENDING or is set, call do_signal 809# 810.Lio_sigpending: 811 # TRACE_IRQS_ON already done at .Lio_return 812 ssm __LC_SVC_NEW_PSW # reenable interrupts 813 lgr %r2,%r11 # pass pointer to pt_regs 814 brasl %r14,do_signal 815 ssm __LC_PGM_NEW_PSW # disable I/O and ext. interrupts 816 TRACE_IRQS_OFF 817 j .Lio_return 818 819# 820# _TIF_NOTIFY_RESUME or is set, call do_notify_resume 821# 822.Lio_notify_resume: 823 # TRACE_IRQS_ON already done at .Lio_return 824 ssm __LC_SVC_NEW_PSW # reenable interrupts 825 lgr %r2,%r11 # pass pointer to pt_regs 826 brasl %r14,do_notify_resume 827 ssm __LC_PGM_NEW_PSW # disable I/O and ext. interrupts 828 TRACE_IRQS_OFF 829 j .Lio_return 830 831/* 832 * External interrupt handler routine 833 */ 834ENTRY(ext_int_handler) 835 STCK __LC_INT_CLOCK 836 stpt __LC_ASYNC_ENTER_TIMER 837 stmg %r8,%r15,__LC_SAVE_AREA_ASYNC 838 lg %r12,__LC_CURRENT 839 larl %r13,cleanup_critical 840 lmg %r8,%r9,__LC_EXT_OLD_PSW 841 SWITCH_ASYNC __LC_SAVE_AREA_ASYNC,__LC_ASYNC_ENTER_TIMER 842 stmg %r0,%r7,__PT_R0(%r11) 843 mvc __PT_R8(64,%r11),__LC_SAVE_AREA_ASYNC 844 stmg %r8,%r9,__PT_PSW(%r11) 845 lghi %r1,__LC_EXT_PARAMS2 846 mvc __PT_INT_CODE(4,%r11),__LC_EXT_CPU_ADDR 847 mvc __PT_INT_PARM(4,%r11),__LC_EXT_PARAMS 848 mvc __PT_INT_PARM_LONG(8,%r11),0(%r1) 849 xc __PT_FLAGS(8,%r11),__PT_FLAGS(%r11) 850 TSTMSK __LC_CPU_FLAGS,_CIF_IGNORE_IRQ 851 jo .Lio_restore 852 TRACE_IRQS_OFF 853 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15) 854 lgr %r2,%r11 # pass pointer to pt_regs 855 lghi %r3,EXT_INTERRUPT 856 brasl %r14,do_IRQ 857 j .Lio_return 858 859/* 860 * Load idle PSW. The second "half" of this function is in .Lcleanup_idle. 861 */ 862ENTRY(psw_idle) 863 stg %r3,__SF_EMPTY(%r15) 864 larl %r1,.Lpsw_idle_lpsw+4 865 stg %r1,__SF_EMPTY+8(%r15) 866#ifdef CONFIG_SMP 867 larl %r1,smp_cpu_mtid 868 llgf %r1,0(%r1) 869 ltgr %r1,%r1 870 jz .Lpsw_idle_stcctm 871 .insn rsy,0xeb0000000017,%r1,5,__SF_EMPTY+16(%r15) 872.Lpsw_idle_stcctm: 873#endif 874 oi __LC_CPU_FLAGS+7,_CIF_ENABLED_WAIT 875 STCK __CLOCK_IDLE_ENTER(%r2) 876 stpt __TIMER_IDLE_ENTER(%r2) 877.Lpsw_idle_lpsw: 878 lpswe __SF_EMPTY(%r15) 879 br %r14 880.Lpsw_idle_end: 881 882/* 883 * Store floating-point controls and floating-point or vector register 884 * depending whether the vector facility is available. A critical section 885 * cleanup assures that the registers are stored even if interrupted for 886 * some other work. The CIF_FPU flag is set to trigger a lazy restore 887 * of the register contents at return from io or a system call. 888 */ 889ENTRY(save_fpu_regs) 890 lg %r2,__LC_CURRENT 891 aghi %r2,__TASK_thread 892 TSTMSK __LC_CPU_FLAGS,_CIF_FPU 893 bor %r14 894 stfpc __THREAD_FPU_fpc(%r2) 895 lg %r3,__THREAD_FPU_regs(%r2) 896 TSTMSK __LC_MACHINE_FLAGS,MACHINE_FLAG_VX 897 jz .Lsave_fpu_regs_fp # no -> store FP regs 898 VSTM %v0,%v15,0,%r3 # vstm 0,15,0(3) 899 VSTM %v16,%v31,256,%r3 # vstm 16,31,256(3) 900 j .Lsave_fpu_regs_done # -> set CIF_FPU flag 901.Lsave_fpu_regs_fp: 902 std 0,0(%r3) 903 std 1,8(%r3) 904 std 2,16(%r3) 905 std 3,24(%r3) 906 std 4,32(%r3) 907 std 5,40(%r3) 908 std 6,48(%r3) 909 std 7,56(%r3) 910 std 8,64(%r3) 911 std 9,72(%r3) 912 std 10,80(%r3) 913 std 11,88(%r3) 914 std 12,96(%r3) 915 std 13,104(%r3) 916 std 14,112(%r3) 917 std 15,120(%r3) 918.Lsave_fpu_regs_done: 919 oi __LC_CPU_FLAGS+7,_CIF_FPU 920 br %r14 921.Lsave_fpu_regs_end: 922EXPORT_SYMBOL(save_fpu_regs) 923 924/* 925 * Load floating-point controls and floating-point or vector registers. 926 * A critical section cleanup assures that the register contents are 927 * loaded even if interrupted for some other work. 928 * 929 * There are special calling conventions to fit into sysc and io return work: 930 * %r15: <kernel stack> 931 * The function requires: 932 * %r4 933 */ 934load_fpu_regs: 935 lg %r4,__LC_CURRENT 936 aghi %r4,__TASK_thread 937 TSTMSK __LC_CPU_FLAGS,_CIF_FPU 938 bnor %r14 939 lfpc __THREAD_FPU_fpc(%r4) 940 TSTMSK __LC_MACHINE_FLAGS,MACHINE_FLAG_VX 941 lg %r4,__THREAD_FPU_regs(%r4) # %r4 <- reg save area 942 jz .Lload_fpu_regs_fp # -> no VX, load FP regs 943 VLM %v0,%v15,0,%r4 944 VLM %v16,%v31,256,%r4 945 j .Lload_fpu_regs_done 946.Lload_fpu_regs_fp: 947 ld 0,0(%r4) 948 ld 1,8(%r4) 949 ld 2,16(%r4) 950 ld 3,24(%r4) 951 ld 4,32(%r4) 952 ld 5,40(%r4) 953 ld 6,48(%r4) 954 ld 7,56(%r4) 955 ld 8,64(%r4) 956 ld 9,72(%r4) 957 ld 10,80(%r4) 958 ld 11,88(%r4) 959 ld 12,96(%r4) 960 ld 13,104(%r4) 961 ld 14,112(%r4) 962 ld 15,120(%r4) 963.Lload_fpu_regs_done: 964 ni __LC_CPU_FLAGS+7,255-_CIF_FPU 965 br %r14 966.Lload_fpu_regs_end: 967 968.L__critical_end: 969 970/* 971 * Machine check handler routines 972 */ 973ENTRY(mcck_int_handler) 974 STCK __LC_MCCK_CLOCK 975 la %r1,4095 # validate r1 976 spt __LC_CPU_TIMER_SAVE_AREA-4095(%r1) # validate cpu timer 977 sckc __LC_CLOCK_COMPARATOR # validate comparator 978 lam %a0,%a15,__LC_AREGS_SAVE_AREA-4095(%r1) # validate acrs 979 lmg %r0,%r15,__LC_GPREGS_SAVE_AREA-4095(%r1)# validate gprs 980 lg %r12,__LC_CURRENT 981 larl %r13,cleanup_critical 982 lmg %r8,%r9,__LC_MCK_OLD_PSW 983 TSTMSK __LC_MCCK_CODE,MCCK_CODE_SYSTEM_DAMAGE 984 jo .Lmcck_panic # yes -> rest of mcck code invalid 985 TSTMSK __LC_MCCK_CODE,MCCK_CODE_CR_VALID 986 jno .Lmcck_panic # control registers invalid -> panic 987 la %r14,4095 988 lctlg %c0,%c15,__LC_CREGS_SAVE_AREA-4095(%r14) # validate ctl regs 989 ptlb 990 lg %r11,__LC_MCESAD-4095(%r14) # extended machine check save area 991 nill %r11,0xfc00 # MCESA_ORIGIN_MASK 992 TSTMSK __LC_CREGS_SAVE_AREA+16-4095(%r14),CR2_GUARDED_STORAGE 993 jno 0f 994 TSTMSK __LC_MCCK_CODE,MCCK_CODE_GS_VALID 995 jno 0f 996 .insn rxy,0xe3000000004d,0,__MCESA_GS_SAVE_AREA(%r11) # LGSC 9970: l %r14,__LC_FP_CREG_SAVE_AREA-4095(%r14) 998 TSTMSK __LC_MCCK_CODE,MCCK_CODE_FC_VALID 999 jo 0f 1000 sr %r14,%r14 10010: sfpc %r14 1002 TSTMSK __LC_MACHINE_FLAGS,MACHINE_FLAG_VX 1003 jo 0f 1004 lghi %r14,__LC_FPREGS_SAVE_AREA 1005 ld %f0,0(%r14) 1006 ld %f1,8(%r14) 1007 ld %f2,16(%r14) 1008 ld %f3,24(%r14) 1009 ld %f4,32(%r14) 1010 ld %f5,40(%r14) 1011 ld %f6,48(%r14) 1012 ld %f7,56(%r14) 1013 ld %f8,64(%r14) 1014 ld %f9,72(%r14) 1015 ld %f10,80(%r14) 1016 ld %f11,88(%r14) 1017 ld %f12,96(%r14) 1018 ld %f13,104(%r14) 1019 ld %f14,112(%r14) 1020 ld %f15,120(%r14) 1021 j 1f 10220: VLM %v0,%v15,0,%r11 1023 VLM %v16,%v31,256,%r11 10241: lghi %r14,__LC_CPU_TIMER_SAVE_AREA 1025 mvc __LC_MCCK_ENTER_TIMER(8),0(%r14) 1026 TSTMSK __LC_MCCK_CODE,MCCK_CODE_CPU_TIMER_VALID 1027 jo 3f 1028 la %r14,__LC_SYNC_ENTER_TIMER 1029 clc 0(8,%r14),__LC_ASYNC_ENTER_TIMER 1030 jl 0f 1031 la %r14,__LC_ASYNC_ENTER_TIMER 10320: clc 0(8,%r14),__LC_EXIT_TIMER 1033 jl 1f 1034 la %r14,__LC_EXIT_TIMER 10351: clc 0(8,%r14),__LC_LAST_UPDATE_TIMER 1036 jl 2f 1037 la %r14,__LC_LAST_UPDATE_TIMER 10382: spt 0(%r14) 1039 mvc __LC_MCCK_ENTER_TIMER(8),0(%r14) 10403: TSTMSK __LC_MCCK_CODE,MCCK_CODE_PSW_MWP_VALID 1041 jno .Lmcck_panic 1042 tmhh %r8,0x0001 # interrupting from user ? 1043 jnz 4f 1044 TSTMSK __LC_MCCK_CODE,MCCK_CODE_PSW_IA_VALID 1045 jno .Lmcck_panic 10464: SWITCH_ASYNC __LC_GPREGS_SAVE_AREA+64,__LC_MCCK_ENTER_TIMER 1047.Lmcck_skip: 1048 lghi %r14,__LC_GPREGS_SAVE_AREA+64 1049 stmg %r0,%r7,__PT_R0(%r11) 1050 mvc __PT_R8(64,%r11),0(%r14) 1051 stmg %r8,%r9,__PT_PSW(%r11) 1052 xc __PT_FLAGS(8,%r11),__PT_FLAGS(%r11) 1053 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15) 1054 lgr %r2,%r11 # pass pointer to pt_regs 1055 brasl %r14,s390_do_machine_check 1056 tm __PT_PSW+1(%r11),0x01 # returning to user ? 1057 jno .Lmcck_return 1058 lg %r1,__LC_KERNEL_STACK # switch to kernel stack 1059 mvc STACK_FRAME_OVERHEAD(__PT_SIZE,%r1),0(%r11) 1060 xc __SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1) 1061 la %r11,STACK_FRAME_OVERHEAD(%r1) 1062 lgr %r15,%r1 1063 ssm __LC_PGM_NEW_PSW # turn dat on, keep irqs off 1064 TSTMSK __LC_CPU_FLAGS,_CIF_MCCK_PENDING 1065 jno .Lmcck_return 1066 TRACE_IRQS_OFF 1067 brasl %r14,s390_handle_mcck 1068 TRACE_IRQS_ON 1069.Lmcck_return: 1070 lg %r14,__LC_VDSO_PER_CPU 1071 lmg %r0,%r10,__PT_R0(%r11) 1072 mvc __LC_RETURN_MCCK_PSW(16),__PT_PSW(%r11) # move return PSW 1073 tm __LC_RETURN_MCCK_PSW+1,0x01 # returning to user ? 1074 jno 0f 1075 stpt __LC_EXIT_TIMER 1076 mvc __VDSO_ECTG_BASE(16,%r14),__LC_EXIT_TIMER 10770: lmg %r11,%r15,__PT_R11(%r11) 1078 lpswe __LC_RETURN_MCCK_PSW 1079 1080.Lmcck_panic: 1081 lg %r15,__LC_PANIC_STACK 1082 la %r11,STACK_FRAME_OVERHEAD(%r15) 1083 j .Lmcck_skip 1084 1085# 1086# PSW restart interrupt handler 1087# 1088ENTRY(restart_int_handler) 1089 TSTMSK __LC_MACHINE_FLAGS,MACHINE_FLAG_LPP 1090 jz 0f 1091 .insn s,0xb2800000,__LC_LPP 10920: stg %r15,__LC_SAVE_AREA_RESTART 1093 lg %r15,__LC_RESTART_STACK 1094 aghi %r15,-__PT_SIZE # create pt_regs on stack 1095 xc 0(__PT_SIZE,%r15),0(%r15) 1096 stmg %r0,%r14,__PT_R0(%r15) 1097 mvc __PT_R15(8,%r15),__LC_SAVE_AREA_RESTART 1098 mvc __PT_PSW(16,%r15),__LC_RST_OLD_PSW # store restart old psw 1099 aghi %r15,-STACK_FRAME_OVERHEAD # create stack frame on stack 1100 xc 0(STACK_FRAME_OVERHEAD,%r15),0(%r15) 1101 lg %r1,__LC_RESTART_FN # load fn, parm & source cpu 1102 lg %r2,__LC_RESTART_DATA 1103 lg %r3,__LC_RESTART_SOURCE 1104 ltgr %r3,%r3 # test source cpu address 1105 jm 1f # negative -> skip source stop 11060: sigp %r4,%r3,SIGP_SENSE # sigp sense to source cpu 1107 brc 10,0b # wait for status stored 11081: basr %r14,%r1 # call function 1109 stap __SF_EMPTY(%r15) # store cpu address 1110 llgh %r3,__SF_EMPTY(%r15) 11112: sigp %r4,%r3,SIGP_STOP # sigp stop to current cpu 1112 brc 2,2b 11133: j 3b 1114 1115 .section .kprobes.text, "ax" 1116 1117#ifdef CONFIG_CHECK_STACK 1118/* 1119 * The synchronous or the asynchronous stack overflowed. We are dead. 1120 * No need to properly save the registers, we are going to panic anyway. 1121 * Setup a pt_regs so that show_trace can provide a good call trace. 1122 */ 1123stack_overflow: 1124 lg %r15,__LC_PANIC_STACK # change to panic stack 1125 la %r11,STACK_FRAME_OVERHEAD(%r15) 1126 stmg %r0,%r7,__PT_R0(%r11) 1127 stmg %r8,%r9,__PT_PSW(%r11) 1128 mvc __PT_R8(64,%r11),0(%r14) 1129 stg %r10,__PT_ORIG_GPR2(%r11) # store last break to orig_gpr2 1130 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15) 1131 lgr %r2,%r11 # pass pointer to pt_regs 1132 jg kernel_stack_overflow 1133#endif 1134 1135cleanup_critical: 1136#if IS_ENABLED(CONFIG_KVM) 1137 clg %r9,BASED(.Lcleanup_table_sie) # .Lsie_gmap 1138 jl 0f 1139 clg %r9,BASED(.Lcleanup_table_sie+8)# .Lsie_done 1140 jl .Lcleanup_sie 1141#endif 1142 clg %r9,BASED(.Lcleanup_table) # system_call 1143 jl 0f 1144 clg %r9,BASED(.Lcleanup_table+8) # .Lsysc_do_svc 1145 jl .Lcleanup_system_call 1146 clg %r9,BASED(.Lcleanup_table+16) # .Lsysc_tif 1147 jl 0f 1148 clg %r9,BASED(.Lcleanup_table+24) # .Lsysc_restore 1149 jl .Lcleanup_sysc_tif 1150 clg %r9,BASED(.Lcleanup_table+32) # .Lsysc_done 1151 jl .Lcleanup_sysc_restore 1152 clg %r9,BASED(.Lcleanup_table+40) # .Lio_tif 1153 jl 0f 1154 clg %r9,BASED(.Lcleanup_table+48) # .Lio_restore 1155 jl .Lcleanup_io_tif 1156 clg %r9,BASED(.Lcleanup_table+56) # .Lio_done 1157 jl .Lcleanup_io_restore 1158 clg %r9,BASED(.Lcleanup_table+64) # psw_idle 1159 jl 0f 1160 clg %r9,BASED(.Lcleanup_table+72) # .Lpsw_idle_end 1161 jl .Lcleanup_idle 1162 clg %r9,BASED(.Lcleanup_table+80) # save_fpu_regs 1163 jl 0f 1164 clg %r9,BASED(.Lcleanup_table+88) # .Lsave_fpu_regs_end 1165 jl .Lcleanup_save_fpu_regs 1166 clg %r9,BASED(.Lcleanup_table+96) # load_fpu_regs 1167 jl 0f 1168 clg %r9,BASED(.Lcleanup_table+104) # .Lload_fpu_regs_end 1169 jl .Lcleanup_load_fpu_regs 11700: br %r14 1171 1172 .align 8 1173.Lcleanup_table: 1174 .quad system_call 1175 .quad .Lsysc_do_svc 1176 .quad .Lsysc_tif 1177 .quad .Lsysc_restore 1178 .quad .Lsysc_done 1179 .quad .Lio_tif 1180 .quad .Lio_restore 1181 .quad .Lio_done 1182 .quad psw_idle 1183 .quad .Lpsw_idle_end 1184 .quad save_fpu_regs 1185 .quad .Lsave_fpu_regs_end 1186 .quad load_fpu_regs 1187 .quad .Lload_fpu_regs_end 1188 1189#if IS_ENABLED(CONFIG_KVM) 1190.Lcleanup_table_sie: 1191 .quad .Lsie_gmap 1192 .quad .Lsie_done 1193 1194.Lcleanup_sie: 1195 cghi %r11,__LC_SAVE_AREA_ASYNC #Is this in normal interrupt? 1196 je 1f 1197 slg %r9,BASED(.Lsie_crit_mcck_start) 1198 clg %r9,BASED(.Lsie_crit_mcck_length) 1199 jh 1f 1200 oi __LC_CPU_FLAGS+7, _CIF_MCCK_GUEST 12011: lg %r9,__SF_EMPTY(%r15) # get control block pointer 1202 ni __SIE_PROG0C+3(%r9),0xfe # no longer in SIE 1203 lctlg %c1,%c1,__LC_USER_ASCE # load primary asce 1204 larl %r9,sie_exit # skip forward to sie_exit 1205 br %r14 1206#endif 1207 1208.Lcleanup_system_call: 1209 # check if stpt has been executed 1210 clg %r9,BASED(.Lcleanup_system_call_insn) 1211 jh 0f 1212 mvc __LC_SYNC_ENTER_TIMER(8),__LC_ASYNC_ENTER_TIMER 1213 cghi %r11,__LC_SAVE_AREA_ASYNC 1214 je 0f 1215 mvc __LC_SYNC_ENTER_TIMER(8),__LC_MCCK_ENTER_TIMER 12160: # check if stmg has been executed 1217 clg %r9,BASED(.Lcleanup_system_call_insn+8) 1218 jh 0f 1219 mvc __LC_SAVE_AREA_SYNC(64),0(%r11) 12200: # check if base register setup + TIF bit load has been done 1221 clg %r9,BASED(.Lcleanup_system_call_insn+16) 1222 jhe 0f 1223 # set up saved register r12 task struct pointer 1224 stg %r12,32(%r11) 1225 # set up saved register r13 __TASK_thread offset 1226 mvc 40(8,%r11),BASED(.Lcleanup_system_call_const) 12270: # check if the user time update has been done 1228 clg %r9,BASED(.Lcleanup_system_call_insn+24) 1229 jh 0f 1230 lg %r15,__LC_EXIT_TIMER 1231 slg %r15,__LC_SYNC_ENTER_TIMER 1232 alg %r15,__LC_USER_TIMER 1233 stg %r15,__LC_USER_TIMER 12340: # check if the system time update has been done 1235 clg %r9,BASED(.Lcleanup_system_call_insn+32) 1236 jh 0f 1237 lg %r15,__LC_LAST_UPDATE_TIMER 1238 slg %r15,__LC_EXIT_TIMER 1239 alg %r15,__LC_SYSTEM_TIMER 1240 stg %r15,__LC_SYSTEM_TIMER 12410: # update accounting time stamp 1242 mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER 1243 # set up saved register r11 1244 lg %r15,__LC_KERNEL_STACK 1245 la %r9,STACK_FRAME_OVERHEAD(%r15) 1246 stg %r9,24(%r11) # r11 pt_regs pointer 1247 # fill pt_regs 1248 mvc __PT_R8(64,%r9),__LC_SAVE_AREA_SYNC 1249 stmg %r0,%r7,__PT_R0(%r9) 1250 mvc __PT_PSW(16,%r9),__LC_SVC_OLD_PSW 1251 mvc __PT_INT_CODE(4,%r9),__LC_SVC_ILC 1252 xc __PT_FLAGS(8,%r9),__PT_FLAGS(%r9) 1253 mvi __PT_FLAGS+7(%r9),_PIF_SYSCALL 1254 # setup saved register r15 1255 stg %r15,56(%r11) # r15 stack pointer 1256 # set new psw address and exit 1257 larl %r9,.Lsysc_do_svc 1258 br %r14 1259.Lcleanup_system_call_insn: 1260 .quad system_call 1261 .quad .Lsysc_stmg 1262 .quad .Lsysc_per 1263 .quad .Lsysc_vtime+36 1264 .quad .Lsysc_vtime+42 1265.Lcleanup_system_call_const: 1266 .quad __TASK_thread 1267 1268.Lcleanup_sysc_tif: 1269 larl %r9,.Lsysc_tif 1270 br %r14 1271 1272.Lcleanup_sysc_restore: 1273 # check if stpt has been executed 1274 clg %r9,BASED(.Lcleanup_sysc_restore_insn) 1275 jh 0f 1276 mvc __LC_EXIT_TIMER(8),__LC_ASYNC_ENTER_TIMER 1277 cghi %r11,__LC_SAVE_AREA_ASYNC 1278 je 0f 1279 mvc __LC_EXIT_TIMER(8),__LC_MCCK_ENTER_TIMER 12800: clg %r9,BASED(.Lcleanup_sysc_restore_insn+8) 1281 je 1f 1282 lg %r9,24(%r11) # get saved pointer to pt_regs 1283 mvc __LC_RETURN_PSW(16),__PT_PSW(%r9) 1284 mvc 0(64,%r11),__PT_R8(%r9) 1285 lmg %r0,%r7,__PT_R0(%r9) 12861: lmg %r8,%r9,__LC_RETURN_PSW 1287 br %r14 1288.Lcleanup_sysc_restore_insn: 1289 .quad .Lsysc_exit_timer 1290 .quad .Lsysc_done - 4 1291 1292.Lcleanup_io_tif: 1293 larl %r9,.Lio_tif 1294 br %r14 1295 1296.Lcleanup_io_restore: 1297 # check if stpt has been executed 1298 clg %r9,BASED(.Lcleanup_io_restore_insn) 1299 jh 0f 1300 mvc __LC_EXIT_TIMER(8),__LC_MCCK_ENTER_TIMER 13010: clg %r9,BASED(.Lcleanup_io_restore_insn+8) 1302 je 1f 1303 lg %r9,24(%r11) # get saved r11 pointer to pt_regs 1304 mvc __LC_RETURN_PSW(16),__PT_PSW(%r9) 1305 mvc 0(64,%r11),__PT_R8(%r9) 1306 lmg %r0,%r7,__PT_R0(%r9) 13071: lmg %r8,%r9,__LC_RETURN_PSW 1308 br %r14 1309.Lcleanup_io_restore_insn: 1310 .quad .Lio_exit_timer 1311 .quad .Lio_done - 4 1312 1313.Lcleanup_idle: 1314 ni __LC_CPU_FLAGS+7,255-_CIF_ENABLED_WAIT 1315 # copy interrupt clock & cpu timer 1316 mvc __CLOCK_IDLE_EXIT(8,%r2),__LC_INT_CLOCK 1317 mvc __TIMER_IDLE_EXIT(8,%r2),__LC_ASYNC_ENTER_TIMER 1318 cghi %r11,__LC_SAVE_AREA_ASYNC 1319 je 0f 1320 mvc __CLOCK_IDLE_EXIT(8,%r2),__LC_MCCK_CLOCK 1321 mvc __TIMER_IDLE_EXIT(8,%r2),__LC_MCCK_ENTER_TIMER 13220: # check if stck & stpt have been executed 1323 clg %r9,BASED(.Lcleanup_idle_insn) 1324 jhe 1f 1325 mvc __CLOCK_IDLE_ENTER(8,%r2),__CLOCK_IDLE_EXIT(%r2) 1326 mvc __TIMER_IDLE_ENTER(8,%r2),__TIMER_IDLE_EXIT(%r2) 13271: # calculate idle cycles 1328#ifdef CONFIG_SMP 1329 clg %r9,BASED(.Lcleanup_idle_insn) 1330 jl 3f 1331 larl %r1,smp_cpu_mtid 1332 llgf %r1,0(%r1) 1333 ltgr %r1,%r1 1334 jz 3f 1335 .insn rsy,0xeb0000000017,%r1,5,__SF_EMPTY+80(%r15) 1336 larl %r3,mt_cycles 1337 ag %r3,__LC_PERCPU_OFFSET 1338 la %r4,__SF_EMPTY+16(%r15) 13392: lg %r0,0(%r3) 1340 slg %r0,0(%r4) 1341 alg %r0,64(%r4) 1342 stg %r0,0(%r3) 1343 la %r3,8(%r3) 1344 la %r4,8(%r4) 1345 brct %r1,2b 1346#endif 13473: # account system time going idle 1348 lg %r9,__LC_STEAL_TIMER 1349 alg %r9,__CLOCK_IDLE_ENTER(%r2) 1350 slg %r9,__LC_LAST_UPDATE_CLOCK 1351 stg %r9,__LC_STEAL_TIMER 1352 mvc __LC_LAST_UPDATE_CLOCK(8),__CLOCK_IDLE_EXIT(%r2) 1353 lg %r9,__LC_SYSTEM_TIMER 1354 alg %r9,__LC_LAST_UPDATE_TIMER 1355 slg %r9,__TIMER_IDLE_ENTER(%r2) 1356 stg %r9,__LC_SYSTEM_TIMER 1357 mvc __LC_LAST_UPDATE_TIMER(8),__TIMER_IDLE_EXIT(%r2) 1358 # prepare return psw 1359 nihh %r8,0xfcfd # clear irq & wait state bits 1360 lg %r9,48(%r11) # return from psw_idle 1361 br %r14 1362.Lcleanup_idle_insn: 1363 .quad .Lpsw_idle_lpsw 1364 1365.Lcleanup_save_fpu_regs: 1366 larl %r9,save_fpu_regs 1367 br %r14 1368 1369.Lcleanup_load_fpu_regs: 1370 larl %r9,load_fpu_regs 1371 br %r14 1372 1373/* 1374 * Integer constants 1375 */ 1376 .align 8 1377.Lcritical_start: 1378 .quad .L__critical_start 1379.Lcritical_length: 1380 .quad .L__critical_end - .L__critical_start 1381#if IS_ENABLED(CONFIG_KVM) 1382.Lsie_critical_start: 1383 .quad .Lsie_gmap 1384.Lsie_critical_length: 1385 .quad .Lsie_done - .Lsie_gmap 1386.Lsie_crit_mcck_start: 1387 .quad .Lsie_entry 1388.Lsie_crit_mcck_length: 1389 .quad .Lsie_skip - .Lsie_entry 1390#endif 1391 1392 .section .rodata, "a" 1393#define SYSCALL(esame,emu) .long esame 1394 .globl sys_call_table 1395sys_call_table: 1396#include "syscalls.S" 1397#undef SYSCALL 1398 1399#ifdef CONFIG_COMPAT 1400 1401#define SYSCALL(esame,emu) .long emu 1402 .globl sys_call_table_emu 1403sys_call_table_emu: 1404#include "syscalls.S" 1405#undef SYSCALL 1406#endif 1407