xref: /openbmc/linux/arch/s390/kernel/entry.S (revision 2c684d89) 
1/*
2 *    S390 low-level entry points.
3 *
4 *    Copyright IBM Corp. 1999, 2012
5 *    Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com),
6 *		 Hartmut Penner (hp@de.ibm.com),
7 *		 Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com),
8 *		 Heiko Carstens <heiko.carstens@de.ibm.com>
9 */
10
11#include <linux/init.h>
12#include <linux/linkage.h>
13#include <asm/processor.h>
14#include <asm/cache.h>
15#include <asm/errno.h>
16#include <asm/ptrace.h>
17#include <asm/thread_info.h>
18#include <asm/asm-offsets.h>
19#include <asm/unistd.h>
20#include <asm/page.h>
21#include <asm/sigp.h>
22#include <asm/irq.h>
23#include <asm/vx-insn.h>
24#include <asm/setup.h>
25#include <asm/nmi.h>
26
27__PT_R0      =	__PT_GPRS
28__PT_R1      =	__PT_GPRS + 8
29__PT_R2      =	__PT_GPRS + 16
30__PT_R3      =	__PT_GPRS + 24
31__PT_R4      =	__PT_GPRS + 32
32__PT_R5      =	__PT_GPRS + 40
33__PT_R6      =	__PT_GPRS + 48
34__PT_R7      =	__PT_GPRS + 56
35__PT_R8      =	__PT_GPRS + 64
36__PT_R9      =	__PT_GPRS + 72
37__PT_R10     =	__PT_GPRS + 80
38__PT_R11     =	__PT_GPRS + 88
39__PT_R12     =	__PT_GPRS + 96
40__PT_R13     =	__PT_GPRS + 104
41__PT_R14     =	__PT_GPRS + 112
42__PT_R15     =	__PT_GPRS + 120
43
44STACK_SHIFT = PAGE_SHIFT + THREAD_ORDER
45STACK_SIZE  = 1 << STACK_SHIFT
46STACK_INIT = STACK_SIZE - STACK_FRAME_OVERHEAD - __PT_SIZE
47
48_TIF_WORK	= (_TIF_SIGPENDING | _TIF_NOTIFY_RESUME | _TIF_NEED_RESCHED | \
49		   _TIF_UPROBE)
50_TIF_TRACE	= (_TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT | _TIF_SECCOMP | \
51		   _TIF_SYSCALL_TRACEPOINT)
52_CIF_WORK	= (_CIF_MCCK_PENDING | _CIF_ASCE | _CIF_FPU)
53_PIF_WORK	= (_PIF_PER_TRAP)
54
55#define BASED(name) name-cleanup_critical(%r13)
56
57	.macro	TRACE_IRQS_ON
58#ifdef CONFIG_TRACE_IRQFLAGS
59	basr	%r2,%r0
60	brasl	%r14,trace_hardirqs_on_caller
61#endif
62	.endm
63
64	.macro	TRACE_IRQS_OFF
65#ifdef CONFIG_TRACE_IRQFLAGS
66	basr	%r2,%r0
67	brasl	%r14,trace_hardirqs_off_caller
68#endif
69	.endm
70
71	.macro	LOCKDEP_SYS_EXIT
72#ifdef CONFIG_LOCKDEP
73	tm	__PT_PSW+1(%r11),0x01	# returning to user ?
74	jz	.+10
75	brasl	%r14,lockdep_sys_exit
76#endif
77	.endm
78
79	.macro	CHECK_STACK stacksize,savearea
80#ifdef CONFIG_CHECK_STACK
81	tml	%r15,\stacksize - CONFIG_STACK_GUARD
82	lghi	%r14,\savearea
83	jz	stack_overflow
84#endif
85	.endm
86
87	.macro	SWITCH_ASYNC savearea,timer
88	tmhh	%r8,0x0001		# interrupting from user ?
89	jnz	1f
90	lgr	%r14,%r9
91	slg	%r14,BASED(.Lcritical_start)
92	clg	%r14,BASED(.Lcritical_length)
93	jhe	0f
94	lghi	%r11,\savearea		# inside critical section, do cleanup
95	brasl	%r14,cleanup_critical
96	tmhh	%r8,0x0001		# retest problem state after cleanup
97	jnz	1f
980:	lg	%r14,__LC_ASYNC_STACK	# are we already on the async stack?
99	slgr	%r14,%r15
100	srag	%r14,%r14,STACK_SHIFT
101	jnz	2f
102	CHECK_STACK 1<<STACK_SHIFT,\savearea
103	aghi	%r15,-(STACK_FRAME_OVERHEAD + __PT_SIZE)
104	j	3f
1051:	LAST_BREAK %r14
106	UPDATE_VTIME %r14,%r15,\timer
1072:	lg	%r15,__LC_ASYNC_STACK	# load async stack
1083:	la	%r11,STACK_FRAME_OVERHEAD(%r15)
109	.endm
110
111	.macro UPDATE_VTIME w1,w2,enter_timer
112	lg	\w1,__LC_EXIT_TIMER
113	lg	\w2,__LC_LAST_UPDATE_TIMER
114	slg	\w1,\enter_timer
115	slg	\w2,__LC_EXIT_TIMER
116	alg	\w1,__LC_USER_TIMER
117	alg	\w2,__LC_SYSTEM_TIMER
118	stg	\w1,__LC_USER_TIMER
119	stg	\w2,__LC_SYSTEM_TIMER
120	mvc	__LC_LAST_UPDATE_TIMER(8),\enter_timer
121	.endm
122
123	.macro	LAST_BREAK scratch
124	srag	\scratch,%r10,23
125	jz	.+10
126	stg	%r10,__TI_last_break(%r12)
127	.endm
128
129	.macro REENABLE_IRQS
130	stg	%r8,__LC_RETURN_PSW
131	ni	__LC_RETURN_PSW,0xbf
132	ssm	__LC_RETURN_PSW
133	.endm
134
135	.macro STCK savearea
136#ifdef CONFIG_HAVE_MARCH_Z9_109_FEATURES
137	.insn	s,0xb27c0000,\savearea		# store clock fast
138#else
139	.insn	s,0xb2050000,\savearea		# store clock
140#endif
141	.endm
142
143	/*
144	 * The TSTMSK macro generates a test-under-mask instruction by
145	 * calculating the memory offset for the specified mask value.
146	 * Mask value can be any constant.  The macro shifts the mask
147	 * value to calculate the memory offset for the test-under-mask
148	 * instruction.
149	 */
150	.macro TSTMSK addr, mask, size=8, bytepos=0
151		.if (\bytepos < \size) && (\mask >> 8)
152			.if (\mask & 0xff)
153				.error "Mask exceeds byte boundary"
154			.endif
155			TSTMSK \addr, "(\mask >> 8)", \size, "(\bytepos + 1)"
156			.exitm
157		.endif
158		.ifeq \mask
159			.error "Mask must not be zero"
160		.endif
161		off = \size - \bytepos - 1
162		tm	off+\addr, \mask
163	.endm
164
165	.section .kprobes.text, "ax"
166
167/*
168 * Scheduler resume function, called by switch_to
169 *  gpr2 = (task_struct *) prev
170 *  gpr3 = (task_struct *) next
171 * Returns:
172 *  gpr2 = prev
173 */
174ENTRY(__switch_to)
175	stmg	%r6,%r15,__SF_GPRS(%r15)	# store gprs of prev task
176	lgr	%r1,%r2
177	aghi	%r1,__TASK_thread		# thread_struct of prev task
178	lg	%r4,__TASK_thread_info(%r2)	# get thread_info of prev
179	lg	%r5,__TASK_thread_info(%r3)	# get thread_info of next
180	stg	%r15,__THREAD_ksp(%r1)		# store kernel stack of prev
181	lgr	%r1,%r3
182	aghi	%r1,__TASK_thread		# thread_struct of next task
183	lgr	%r15,%r5
184	aghi	%r15,STACK_INIT			# end of kernel stack of next
185	stg	%r3,__LC_CURRENT		# store task struct of next
186	stg	%r5,__LC_THREAD_INFO		# store thread info of next
187	stg	%r15,__LC_KERNEL_STACK		# store end of kernel stack
188	lg	%r15,__THREAD_ksp(%r1)		# load kernel stack of next
189	lctl	%c4,%c4,__TASK_pid(%r3)		# load pid to control reg. 4
190	mvc	__LC_CURRENT_PID(4,%r0),__TASK_pid(%r3) # store pid of next
191	lmg	%r6,%r15,__SF_GPRS(%r15)	# load gprs of next task
192	TSTMSK	__LC_MACHINE_FLAGS,MACHINE_FLAG_LPP
193	bzr	%r14
194	.insn	s,0xb2800000,__LC_LPP		# set program parameter
195	br	%r14
196
197.L__critical_start:
198
199#if IS_ENABLED(CONFIG_KVM)
200/*
201 * sie64a calling convention:
202 * %r2 pointer to sie control block
203 * %r3 guest register save area
204 */
205ENTRY(sie64a)
206	stmg	%r6,%r14,__SF_GPRS(%r15)	# save kernel registers
207	stg	%r2,__SF_EMPTY(%r15)		# save control block pointer
208	stg	%r3,__SF_EMPTY+8(%r15)		# save guest register save area
209	xc	__SF_EMPTY+16(8,%r15),__SF_EMPTY+16(%r15) # reason code = 0
210	TSTMSK	__LC_CPU_FLAGS,_CIF_FPU		# load guest fp/vx registers ?
211	jno	.Lsie_load_guest_gprs
212	brasl	%r14,load_fpu_regs		# load guest fp/vx regs
213.Lsie_load_guest_gprs:
214	lmg	%r0,%r13,0(%r3)			# load guest gprs 0-13
215	lg	%r14,__LC_GMAP			# get gmap pointer
216	ltgr	%r14,%r14
217	jz	.Lsie_gmap
218	lctlg	%c1,%c1,__GMAP_ASCE(%r14)	# load primary asce
219.Lsie_gmap:
220	lg	%r14,__SF_EMPTY(%r15)		# get control block pointer
221	oi	__SIE_PROG0C+3(%r14),1		# we are going into SIE now
222	tm	__SIE_PROG20+3(%r14),3		# last exit...
223	jnz	.Lsie_skip
224	TSTMSK	__LC_CPU_FLAGS,_CIF_FPU
225	jo	.Lsie_skip			# exit if fp/vx regs changed
226	sie	0(%r14)
227.Lsie_skip:
228	ni	__SIE_PROG0C+3(%r14),0xfe	# no longer in SIE
229	lctlg	%c1,%c1,__LC_USER_ASCE		# load primary asce
230.Lsie_done:
231# some program checks are suppressing. C code (e.g. do_protection_exception)
232# will rewind the PSW by the ILC, which is 4 bytes in case of SIE. Other
233# instructions between sie64a and .Lsie_done should not cause program
234# interrupts. So lets use a nop (47 00 00 00) as a landing pad.
235# See also .Lcleanup_sie
236.Lrewind_pad:
237	nop	0
238	.globl sie_exit
239sie_exit:
240	lg	%r14,__SF_EMPTY+8(%r15)		# load guest register save area
241	stmg	%r0,%r13,0(%r14)		# save guest gprs 0-13
242	lmg	%r6,%r14,__SF_GPRS(%r15)	# restore kernel registers
243	lg	%r2,__SF_EMPTY+16(%r15)		# return exit reason code
244	br	%r14
245.Lsie_fault:
246	lghi	%r14,-EFAULT
247	stg	%r14,__SF_EMPTY+16(%r15)	# set exit reason code
248	j	sie_exit
249
250	EX_TABLE(.Lrewind_pad,.Lsie_fault)
251	EX_TABLE(sie_exit,.Lsie_fault)
252#endif
253
254/*
255 * SVC interrupt handler routine. System calls are synchronous events and
256 * are executed with interrupts enabled.
257 */
258
259ENTRY(system_call)
260	stpt	__LC_SYNC_ENTER_TIMER
261.Lsysc_stmg:
262	stmg	%r8,%r15,__LC_SAVE_AREA_SYNC
263	lg	%r10,__LC_LAST_BREAK
264	lg	%r12,__LC_THREAD_INFO
265	lghi	%r14,_PIF_SYSCALL
266.Lsysc_per:
267	lg	%r15,__LC_KERNEL_STACK
268	la	%r11,STACK_FRAME_OVERHEAD(%r15)	# pointer to pt_regs
269	LAST_BREAK %r13
270.Lsysc_vtime:
271	UPDATE_VTIME %r10,%r13,__LC_SYNC_ENTER_TIMER
272	stmg	%r0,%r7,__PT_R0(%r11)
273	mvc	__PT_R8(64,%r11),__LC_SAVE_AREA_SYNC
274	mvc	__PT_PSW(16,%r11),__LC_SVC_OLD_PSW
275	mvc	__PT_INT_CODE(4,%r11),__LC_SVC_ILC
276	stg	%r14,__PT_FLAGS(%r11)
277.Lsysc_do_svc:
278	lg	%r10,__TI_sysc_table(%r12)	# address of system call table
279	llgh	%r8,__PT_INT_CODE+2(%r11)
280	slag	%r8,%r8,2			# shift and test for svc 0
281	jnz	.Lsysc_nr_ok
282	# svc 0: system call number in %r1
283	llgfr	%r1,%r1				# clear high word in r1
284	cghi	%r1,NR_syscalls
285	jnl	.Lsysc_nr_ok
286	sth	%r1,__PT_INT_CODE+2(%r11)
287	slag	%r8,%r1,2
288.Lsysc_nr_ok:
289	xc	__SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
290	stg	%r2,__PT_ORIG_GPR2(%r11)
291	stg	%r7,STACK_FRAME_OVERHEAD(%r15)
292	lgf	%r9,0(%r8,%r10)			# get system call add.
293	TSTMSK	__TI_flags(%r12),_TIF_TRACE
294	jnz	.Lsysc_tracesys
295	basr	%r14,%r9			# call sys_xxxx
296	stg	%r2,__PT_R2(%r11)		# store return value
297
298.Lsysc_return:
299	LOCKDEP_SYS_EXIT
300.Lsysc_tif:
301	TSTMSK	__PT_FLAGS(%r11),_PIF_WORK
302	jnz	.Lsysc_work
303	TSTMSK	__TI_flags(%r12),_TIF_WORK
304	jnz	.Lsysc_work			# check for work
305	TSTMSK	__LC_CPU_FLAGS,_CIF_WORK
306	jnz	.Lsysc_work
307.Lsysc_restore:
308	lg	%r14,__LC_VDSO_PER_CPU
309	lmg	%r0,%r10,__PT_R0(%r11)
310	mvc	__LC_RETURN_PSW(16),__PT_PSW(%r11)
311	stpt	__LC_EXIT_TIMER
312	mvc	__VDSO_ECTG_BASE(16,%r14),__LC_EXIT_TIMER
313	lmg	%r11,%r15,__PT_R11(%r11)
314	lpswe	__LC_RETURN_PSW
315.Lsysc_done:
316
317#
318# One of the work bits is on. Find out which one.
319#
320.Lsysc_work:
321	TSTMSK	__LC_CPU_FLAGS,_CIF_MCCK_PENDING
322	jo	.Lsysc_mcck_pending
323	TSTMSK	__TI_flags(%r12),_TIF_NEED_RESCHED
324	jo	.Lsysc_reschedule
325#ifdef CONFIG_UPROBES
326	TSTMSK	__TI_flags(%r12),_TIF_UPROBE
327	jo	.Lsysc_uprobe_notify
328#endif
329	TSTMSK	__PT_FLAGS(%r11),_PIF_PER_TRAP
330	jo	.Lsysc_singlestep
331	TSTMSK	__TI_flags(%r12),_TIF_SIGPENDING
332	jo	.Lsysc_sigpending
333	TSTMSK	__TI_flags(%r12),_TIF_NOTIFY_RESUME
334	jo	.Lsysc_notify_resume
335	TSTMSK	__LC_CPU_FLAGS,_CIF_FPU
336	jo	.Lsysc_vxrs
337	TSTMSK	__LC_CPU_FLAGS,_CIF_ASCE
338	jo	.Lsysc_uaccess
339	j	.Lsysc_return		# beware of critical section cleanup
340
341#
342# _TIF_NEED_RESCHED is set, call schedule
343#
344.Lsysc_reschedule:
345	larl	%r14,.Lsysc_return
346	jg	schedule
347
348#
349# _CIF_MCCK_PENDING is set, call handler
350#
351.Lsysc_mcck_pending:
352	larl	%r14,.Lsysc_return
353	jg	s390_handle_mcck	# TIF bit will be cleared by handler
354
355#
356# _CIF_ASCE is set, load user space asce
357#
358.Lsysc_uaccess:
359	ni	__LC_CPU_FLAGS+7,255-_CIF_ASCE
360	lctlg	%c1,%c1,__LC_USER_ASCE		# load primary asce
361	j	.Lsysc_return
362
363#
364# CIF_FPU is set, restore floating-point controls and floating-point registers.
365#
366.Lsysc_vxrs:
367	larl	%r14,.Lsysc_return
368	jg	load_fpu_regs
369
370#
371# _TIF_SIGPENDING is set, call do_signal
372#
373.Lsysc_sigpending:
374	lgr	%r2,%r11		# pass pointer to pt_regs
375	brasl	%r14,do_signal
376	TSTMSK	__PT_FLAGS(%r11),_PIF_SYSCALL
377	jno	.Lsysc_return
378	lmg	%r2,%r7,__PT_R2(%r11)	# load svc arguments
379	lg	%r10,__TI_sysc_table(%r12)	# address of system call table
380	lghi	%r8,0			# svc 0 returns -ENOSYS
381	llgh	%r1,__PT_INT_CODE+2(%r11)	# load new svc number
382	cghi	%r1,NR_syscalls
383	jnl	.Lsysc_nr_ok		# invalid svc number -> do svc 0
384	slag	%r8,%r1,2
385	j	.Lsysc_nr_ok		# restart svc
386
387#
388# _TIF_NOTIFY_RESUME is set, call do_notify_resume
389#
390.Lsysc_notify_resume:
391	lgr	%r2,%r11		# pass pointer to pt_regs
392	larl	%r14,.Lsysc_return
393	jg	do_notify_resume
394
395#
396# _TIF_UPROBE is set, call uprobe_notify_resume
397#
398#ifdef CONFIG_UPROBES
399.Lsysc_uprobe_notify:
400	lgr	%r2,%r11		# pass pointer to pt_regs
401	larl	%r14,.Lsysc_return
402	jg	uprobe_notify_resume
403#endif
404
405#
406# _PIF_PER_TRAP is set, call do_per_trap
407#
408.Lsysc_singlestep:
409	ni	__PT_FLAGS+7(%r11),255-_PIF_PER_TRAP
410	lgr	%r2,%r11		# pass pointer to pt_regs
411	larl	%r14,.Lsysc_return
412	jg	do_per_trap
413
414#
415# call tracehook_report_syscall_entry/tracehook_report_syscall_exit before
416# and after the system call
417#
418.Lsysc_tracesys:
419	lgr	%r2,%r11		# pass pointer to pt_regs
420	la	%r3,0
421	llgh	%r0,__PT_INT_CODE+2(%r11)
422	stg	%r0,__PT_R2(%r11)
423	brasl	%r14,do_syscall_trace_enter
424	lghi	%r0,NR_syscalls
425	clgr	%r0,%r2
426	jnh	.Lsysc_tracenogo
427	sllg	%r8,%r2,2
428	lgf	%r9,0(%r8,%r10)
429.Lsysc_tracego:
430	lmg	%r3,%r7,__PT_R3(%r11)
431	stg	%r7,STACK_FRAME_OVERHEAD(%r15)
432	lg	%r2,__PT_ORIG_GPR2(%r11)
433	basr	%r14,%r9		# call sys_xxx
434	stg	%r2,__PT_R2(%r11)	# store return value
435.Lsysc_tracenogo:
436	TSTMSK	__TI_flags(%r12),_TIF_TRACE
437	jz	.Lsysc_return
438	lgr	%r2,%r11		# pass pointer to pt_regs
439	larl	%r14,.Lsysc_return
440	jg	do_syscall_trace_exit
441
442#
443# a new process exits the kernel with ret_from_fork
444#
445ENTRY(ret_from_fork)
446	la	%r11,STACK_FRAME_OVERHEAD(%r15)
447	lg	%r12,__LC_THREAD_INFO
448	brasl	%r14,schedule_tail
449	TRACE_IRQS_ON
450	ssm	__LC_SVC_NEW_PSW	# reenable interrupts
451	tm	__PT_PSW+1(%r11),0x01	# forking a kernel thread ?
452	jne	.Lsysc_tracenogo
453	# it's a kernel thread
454	lmg	%r9,%r10,__PT_R9(%r11)	# load gprs
455ENTRY(kernel_thread_starter)
456	la	%r2,0(%r10)
457	basr	%r14,%r9
458	j	.Lsysc_tracenogo
459
460/*
461 * Program check handler routine
462 */
463
464ENTRY(pgm_check_handler)
465	stpt	__LC_SYNC_ENTER_TIMER
466	stmg	%r8,%r15,__LC_SAVE_AREA_SYNC
467	lg	%r10,__LC_LAST_BREAK
468	lg	%r12,__LC_THREAD_INFO
469	larl	%r13,cleanup_critical
470	lmg	%r8,%r9,__LC_PGM_OLD_PSW
471	tmhh	%r8,0x0001		# test problem state bit
472	jnz	2f			# -> fault in user space
473#if IS_ENABLED(CONFIG_KVM)
474	# cleanup critical section for sie64a
475	lgr	%r14,%r9
476	slg	%r14,BASED(.Lsie_critical_start)
477	clg	%r14,BASED(.Lsie_critical_length)
478	jhe	0f
479	brasl	%r14,.Lcleanup_sie
480#endif
4810:	tmhh	%r8,0x4000		# PER bit set in old PSW ?
482	jnz	1f			# -> enabled, can't be a double fault
483	tm	__LC_PGM_ILC+3,0x80	# check for per exception
484	jnz	.Lpgm_svcper		# -> single stepped svc
4851:	CHECK_STACK STACK_SIZE,__LC_SAVE_AREA_SYNC
486	aghi	%r15,-(STACK_FRAME_OVERHEAD + __PT_SIZE)
487	j	3f
4882:	LAST_BREAK %r14
489	UPDATE_VTIME %r14,%r15,__LC_SYNC_ENTER_TIMER
490	lg	%r15,__LC_KERNEL_STACK
491	lg	%r14,__TI_task(%r12)
492	aghi	%r14,__TASK_thread	# pointer to thread_struct
493	lghi	%r13,__LC_PGM_TDB
494	tm	__LC_PGM_ILC+2,0x02	# check for transaction abort
495	jz	3f
496	mvc	__THREAD_trap_tdb(256,%r14),0(%r13)
4973:	la	%r11,STACK_FRAME_OVERHEAD(%r15)
498	stmg	%r0,%r7,__PT_R0(%r11)
499	mvc	__PT_R8(64,%r11),__LC_SAVE_AREA_SYNC
500	stmg	%r8,%r9,__PT_PSW(%r11)
501	mvc	__PT_INT_CODE(4,%r11),__LC_PGM_ILC
502	mvc	__PT_INT_PARM_LONG(8,%r11),__LC_TRANS_EXC_CODE
503	xc	__PT_FLAGS(8,%r11),__PT_FLAGS(%r11)
504	stg	%r10,__PT_ARGS(%r11)
505	tm	__LC_PGM_ILC+3,0x80	# check for per exception
506	jz	4f
507	tmhh	%r8,0x0001		# kernel per event ?
508	jz	.Lpgm_kprobe
509	oi	__PT_FLAGS+7(%r11),_PIF_PER_TRAP
510	mvc	__THREAD_per_address(8,%r14),__LC_PER_ADDRESS
511	mvc	__THREAD_per_cause(2,%r14),__LC_PER_CODE
512	mvc	__THREAD_per_paid(1,%r14),__LC_PER_ACCESS_ID
5134:	REENABLE_IRQS
514	xc	__SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
515	larl	%r1,pgm_check_table
516	llgh	%r10,__PT_INT_CODE+2(%r11)
517	nill	%r10,0x007f
518	sll	%r10,2
519	je	.Lpgm_return
520	lgf	%r1,0(%r10,%r1)		# load address of handler routine
521	lgr	%r2,%r11		# pass pointer to pt_regs
522	basr	%r14,%r1		# branch to interrupt-handler
523.Lpgm_return:
524	LOCKDEP_SYS_EXIT
525	tm	__PT_PSW+1(%r11),0x01	# returning to user ?
526	jno	.Lsysc_restore
527	j	.Lsysc_tif
528
529#
530# PER event in supervisor state, must be kprobes
531#
532.Lpgm_kprobe:
533	REENABLE_IRQS
534	xc	__SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
535	lgr	%r2,%r11		# pass pointer to pt_regs
536	brasl	%r14,do_per_trap
537	j	.Lpgm_return
538
539#
540# single stepped system call
541#
542.Lpgm_svcper:
543	mvc	__LC_RETURN_PSW(8),__LC_SVC_NEW_PSW
544	larl	%r14,.Lsysc_per
545	stg	%r14,__LC_RETURN_PSW+8
546	lghi	%r14,_PIF_SYSCALL | _PIF_PER_TRAP
547	lpswe	__LC_RETURN_PSW		# branch to .Lsysc_per and enable irqs
548
549/*
550 * IO interrupt handler routine
551 */
552ENTRY(io_int_handler)
553	STCK	__LC_INT_CLOCK
554	stpt	__LC_ASYNC_ENTER_TIMER
555	stmg	%r8,%r15,__LC_SAVE_AREA_ASYNC
556	lg	%r10,__LC_LAST_BREAK
557	lg	%r12,__LC_THREAD_INFO
558	larl	%r13,cleanup_critical
559	lmg	%r8,%r9,__LC_IO_OLD_PSW
560	SWITCH_ASYNC __LC_SAVE_AREA_ASYNC,__LC_ASYNC_ENTER_TIMER
561	stmg	%r0,%r7,__PT_R0(%r11)
562	mvc	__PT_R8(64,%r11),__LC_SAVE_AREA_ASYNC
563	stmg	%r8,%r9,__PT_PSW(%r11)
564	mvc	__PT_INT_CODE(12,%r11),__LC_SUBCHANNEL_ID
565	xc	__PT_FLAGS(8,%r11),__PT_FLAGS(%r11)
566	TSTMSK	__LC_CPU_FLAGS,_CIF_IGNORE_IRQ
567	jo	.Lio_restore
568	TRACE_IRQS_OFF
569	xc	__SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
570.Lio_loop:
571	lgr	%r2,%r11		# pass pointer to pt_regs
572	lghi	%r3,IO_INTERRUPT
573	tm	__PT_INT_CODE+8(%r11),0x80	# adapter interrupt ?
574	jz	.Lio_call
575	lghi	%r3,THIN_INTERRUPT
576.Lio_call:
577	brasl	%r14,do_IRQ
578	TSTMSK	__LC_MACHINE_FLAGS,MACHINE_FLAG_LPAR
579	jz	.Lio_return
580	tpi	0
581	jz	.Lio_return
582	mvc	__PT_INT_CODE(12,%r11),__LC_SUBCHANNEL_ID
583	j	.Lio_loop
584.Lio_return:
585	LOCKDEP_SYS_EXIT
586	TRACE_IRQS_ON
587.Lio_tif:
588	TSTMSK	__TI_flags(%r12),_TIF_WORK
589	jnz	.Lio_work		# there is work to do (signals etc.)
590	TSTMSK	__LC_CPU_FLAGS,_CIF_WORK
591	jnz	.Lio_work
592.Lio_restore:
593	lg	%r14,__LC_VDSO_PER_CPU
594	lmg	%r0,%r10,__PT_R0(%r11)
595	mvc	__LC_RETURN_PSW(16),__PT_PSW(%r11)
596	stpt	__LC_EXIT_TIMER
597	mvc	__VDSO_ECTG_BASE(16,%r14),__LC_EXIT_TIMER
598	lmg	%r11,%r15,__PT_R11(%r11)
599	lpswe	__LC_RETURN_PSW
600.Lio_done:
601
602#
603# There is work todo, find out in which context we have been interrupted:
604# 1) if we return to user space we can do all _TIF_WORK work
605# 2) if we return to kernel code and kvm is enabled check if we need to
606#    modify the psw to leave SIE
607# 3) if we return to kernel code and preemptive scheduling is enabled check
608#    the preemption counter and if it is zero call preempt_schedule_irq
609# Before any work can be done, a switch to the kernel stack is required.
610#
611.Lio_work:
612	tm	__PT_PSW+1(%r11),0x01	# returning to user ?
613	jo	.Lio_work_user		# yes -> do resched & signal
614#ifdef CONFIG_PREEMPT
615	# check for preemptive scheduling
616	icm	%r0,15,__TI_precount(%r12)
617	jnz	.Lio_restore		# preemption is disabled
618	TSTMSK	__TI_flags(%r12),_TIF_NEED_RESCHED
619	jno	.Lio_restore
620	# switch to kernel stack
621	lg	%r1,__PT_R15(%r11)
622	aghi	%r1,-(STACK_FRAME_OVERHEAD + __PT_SIZE)
623	mvc	STACK_FRAME_OVERHEAD(__PT_SIZE,%r1),0(%r11)
624	xc	__SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1)
625	la	%r11,STACK_FRAME_OVERHEAD(%r1)
626	lgr	%r15,%r1
627	# TRACE_IRQS_ON already done at .Lio_return, call
628	# TRACE_IRQS_OFF to keep things symmetrical
629	TRACE_IRQS_OFF
630	brasl	%r14,preempt_schedule_irq
631	j	.Lio_return
632#else
633	j	.Lio_restore
634#endif
635
636#
637# Need to do work before returning to userspace, switch to kernel stack
638#
639.Lio_work_user:
640	lg	%r1,__LC_KERNEL_STACK
641	mvc	STACK_FRAME_OVERHEAD(__PT_SIZE,%r1),0(%r11)
642	xc	__SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1)
643	la	%r11,STACK_FRAME_OVERHEAD(%r1)
644	lgr	%r15,%r1
645
646#
647# One of the work bits is on. Find out which one.
648#
649.Lio_work_tif:
650	TSTMSK	__LC_CPU_FLAGS,_CIF_MCCK_PENDING
651	jo	.Lio_mcck_pending
652	TSTMSK	__TI_flags(%r12),_TIF_NEED_RESCHED
653	jo	.Lio_reschedule
654	TSTMSK	__TI_flags(%r12),_TIF_SIGPENDING
655	jo	.Lio_sigpending
656	TSTMSK	__TI_flags(%r12),_TIF_NOTIFY_RESUME
657	jo	.Lio_notify_resume
658	TSTMSK	__LC_CPU_FLAGS,_CIF_FPU
659	jo	.Lio_vxrs
660	TSTMSK	__LC_CPU_FLAGS,_CIF_ASCE
661	jo	.Lio_uaccess
662	j	.Lio_return		# beware of critical section cleanup
663
664#
665# _CIF_MCCK_PENDING is set, call handler
666#
667.Lio_mcck_pending:
668	# TRACE_IRQS_ON already done at .Lio_return
669	brasl	%r14,s390_handle_mcck	# TIF bit will be cleared by handler
670	TRACE_IRQS_OFF
671	j	.Lio_return
672
673#
674# _CIF_ASCE is set, load user space asce
675#
676.Lio_uaccess:
677	ni	__LC_CPU_FLAGS+7,255-_CIF_ASCE
678	lctlg	%c1,%c1,__LC_USER_ASCE		# load primary asce
679	j	.Lio_return
680
681#
682# CIF_FPU is set, restore floating-point controls and floating-point registers.
683#
684.Lio_vxrs:
685	larl	%r14,.Lio_return
686	jg	load_fpu_regs
687
688#
689# _TIF_NEED_RESCHED is set, call schedule
690#
691.Lio_reschedule:
692	# TRACE_IRQS_ON already done at .Lio_return
693	ssm	__LC_SVC_NEW_PSW	# reenable interrupts
694	brasl	%r14,schedule		# call scheduler
695	ssm	__LC_PGM_NEW_PSW	# disable I/O and ext. interrupts
696	TRACE_IRQS_OFF
697	j	.Lio_return
698
699#
700# _TIF_SIGPENDING or is set, call do_signal
701#
702.Lio_sigpending:
703	# TRACE_IRQS_ON already done at .Lio_return
704	ssm	__LC_SVC_NEW_PSW	# reenable interrupts
705	lgr	%r2,%r11		# pass pointer to pt_regs
706	brasl	%r14,do_signal
707	ssm	__LC_PGM_NEW_PSW	# disable I/O and ext. interrupts
708	TRACE_IRQS_OFF
709	j	.Lio_return
710
711#
712# _TIF_NOTIFY_RESUME or is set, call do_notify_resume
713#
714.Lio_notify_resume:
715	# TRACE_IRQS_ON already done at .Lio_return
716	ssm	__LC_SVC_NEW_PSW	# reenable interrupts
717	lgr	%r2,%r11		# pass pointer to pt_regs
718	brasl	%r14,do_notify_resume
719	ssm	__LC_PGM_NEW_PSW	# disable I/O and ext. interrupts
720	TRACE_IRQS_OFF
721	j	.Lio_return
722
723/*
724 * External interrupt handler routine
725 */
726ENTRY(ext_int_handler)
727	STCK	__LC_INT_CLOCK
728	stpt	__LC_ASYNC_ENTER_TIMER
729	stmg	%r8,%r15,__LC_SAVE_AREA_ASYNC
730	lg	%r10,__LC_LAST_BREAK
731	lg	%r12,__LC_THREAD_INFO
732	larl	%r13,cleanup_critical
733	lmg	%r8,%r9,__LC_EXT_OLD_PSW
734	SWITCH_ASYNC __LC_SAVE_AREA_ASYNC,__LC_ASYNC_ENTER_TIMER
735	stmg	%r0,%r7,__PT_R0(%r11)
736	mvc	__PT_R8(64,%r11),__LC_SAVE_AREA_ASYNC
737	stmg	%r8,%r9,__PT_PSW(%r11)
738	lghi	%r1,__LC_EXT_PARAMS2
739	mvc	__PT_INT_CODE(4,%r11),__LC_EXT_CPU_ADDR
740	mvc	__PT_INT_PARM(4,%r11),__LC_EXT_PARAMS
741	mvc	__PT_INT_PARM_LONG(8,%r11),0(%r1)
742	xc	__PT_FLAGS(8,%r11),__PT_FLAGS(%r11)
743	TSTMSK	__LC_CPU_FLAGS,_CIF_IGNORE_IRQ
744	jo	.Lio_restore
745	TRACE_IRQS_OFF
746	xc	__SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
747	lgr	%r2,%r11		# pass pointer to pt_regs
748	lghi	%r3,EXT_INTERRUPT
749	brasl	%r14,do_IRQ
750	j	.Lio_return
751
752/*
753 * Load idle PSW. The second "half" of this function is in .Lcleanup_idle.
754 */
755ENTRY(psw_idle)
756	stg	%r3,__SF_EMPTY(%r15)
757	larl	%r1,.Lpsw_idle_lpsw+4
758	stg	%r1,__SF_EMPTY+8(%r15)
759#ifdef CONFIG_SMP
760	larl	%r1,smp_cpu_mtid
761	llgf	%r1,0(%r1)
762	ltgr	%r1,%r1
763	jz	.Lpsw_idle_stcctm
764	.insn	rsy,0xeb0000000017,%r1,5,__SF_EMPTY+16(%r15)
765.Lpsw_idle_stcctm:
766#endif
767	STCK	__CLOCK_IDLE_ENTER(%r2)
768	stpt	__TIMER_IDLE_ENTER(%r2)
769.Lpsw_idle_lpsw:
770	lpswe	__SF_EMPTY(%r15)
771	br	%r14
772.Lpsw_idle_end:
773
774/*
775 * Store floating-point controls and floating-point or vector register
776 * depending whether the vector facility is available.	A critical section
777 * cleanup assures that the registers are stored even if interrupted for
778 * some other work.  The CIF_FPU flag is set to trigger a lazy restore
779 * of the register contents at return from io or a system call.
780 */
781ENTRY(save_fpu_regs)
782	lg	%r2,__LC_CURRENT
783	aghi	%r2,__TASK_thread
784	TSTMSK	__LC_CPU_FLAGS,_CIF_FPU
785	bor	%r14
786	stfpc	__THREAD_FPU_fpc(%r2)
787.Lsave_fpu_regs_fpc_end:
788	lg	%r3,__THREAD_FPU_regs(%r2)
789	TSTMSK	__LC_MACHINE_FLAGS,MACHINE_FLAG_VX
790	jz	.Lsave_fpu_regs_fp	  # no -> store FP regs
791.Lsave_fpu_regs_vx_low:
792	VSTM	%v0,%v15,0,%r3		  # vstm 0,15,0(3)
793.Lsave_fpu_regs_vx_high:
794	VSTM	%v16,%v31,256,%r3	  # vstm 16,31,256(3)
795	j	.Lsave_fpu_regs_done	  # -> set CIF_FPU flag
796.Lsave_fpu_regs_fp:
797	std	0,0(%r3)
798	std	1,8(%r3)
799	std	2,16(%r3)
800	std	3,24(%r3)
801	std	4,32(%r3)
802	std	5,40(%r3)
803	std	6,48(%r3)
804	std	7,56(%r3)
805	std	8,64(%r3)
806	std	9,72(%r3)
807	std	10,80(%r3)
808	std	11,88(%r3)
809	std	12,96(%r3)
810	std	13,104(%r3)
811	std	14,112(%r3)
812	std	15,120(%r3)
813.Lsave_fpu_regs_done:
814	oi	__LC_CPU_FLAGS+7,_CIF_FPU
815	br	%r14
816.Lsave_fpu_regs_end:
817
818/*
819 * Load floating-point controls and floating-point or vector registers.
820 * A critical section cleanup assures that the register contents are
821 * loaded even if interrupted for some other work.
822 *
823 * There are special calling conventions to fit into sysc and io return work:
824 *	%r15:	<kernel stack>
825 * The function requires:
826 *	%r4
827 */
828load_fpu_regs:
829	lg	%r4,__LC_CURRENT
830	aghi	%r4,__TASK_thread
831	TSTMSK	__LC_CPU_FLAGS,_CIF_FPU
832	bnor	%r14
833	lfpc	__THREAD_FPU_fpc(%r4)
834	TSTMSK	__LC_MACHINE_FLAGS,MACHINE_FLAG_VX
835	lg	%r4,__THREAD_FPU_regs(%r4)	# %r4 <- reg save area
836	jz	.Lload_fpu_regs_fp		# -> no VX, load FP regs
837.Lload_fpu_regs_vx:
838	VLM	%v0,%v15,0,%r4
839.Lload_fpu_regs_vx_high:
840	VLM	%v16,%v31,256,%r4
841	j	.Lload_fpu_regs_done
842.Lload_fpu_regs_fp:
843	ld	0,0(%r4)
844	ld	1,8(%r4)
845	ld	2,16(%r4)
846	ld	3,24(%r4)
847	ld	4,32(%r4)
848	ld	5,40(%r4)
849	ld	6,48(%r4)
850	ld	7,56(%r4)
851	ld	8,64(%r4)
852	ld	9,72(%r4)
853	ld	10,80(%r4)
854	ld	11,88(%r4)
855	ld	12,96(%r4)
856	ld	13,104(%r4)
857	ld	14,112(%r4)
858	ld	15,120(%r4)
859.Lload_fpu_regs_done:
860	ni	__LC_CPU_FLAGS+7,255-_CIF_FPU
861	br	%r14
862.Lload_fpu_regs_end:
863
864.L__critical_end:
865
866/*
867 * Machine check handler routines
868 */
869ENTRY(mcck_int_handler)
870	STCK	__LC_MCCK_CLOCK
871	la	%r1,4095		# revalidate r1
872	spt	__LC_CPU_TIMER_SAVE_AREA-4095(%r1)	# revalidate cpu timer
873	lmg	%r0,%r15,__LC_GPREGS_SAVE_AREA-4095(%r1)# revalidate gprs
874	lg	%r10,__LC_LAST_BREAK
875	lg	%r12,__LC_THREAD_INFO
876	larl	%r13,cleanup_critical
877	lmg	%r8,%r9,__LC_MCK_OLD_PSW
878	TSTMSK	__LC_MCCK_CODE,MCCK_CODE_SYSTEM_DAMAGE
879	jo	.Lmcck_panic		# yes -> rest of mcck code invalid
880	lghi	%r14,__LC_CPU_TIMER_SAVE_AREA
881	mvc	__LC_MCCK_ENTER_TIMER(8),0(%r14)
882	TSTMSK	__LC_MCCK_CODE,MCCK_CODE_CPU_TIMER_VALID
883	jo	3f
884	la	%r14,__LC_SYNC_ENTER_TIMER
885	clc	0(8,%r14),__LC_ASYNC_ENTER_TIMER
886	jl	0f
887	la	%r14,__LC_ASYNC_ENTER_TIMER
8880:	clc	0(8,%r14),__LC_EXIT_TIMER
889	jl	1f
890	la	%r14,__LC_EXIT_TIMER
8911:	clc	0(8,%r14),__LC_LAST_UPDATE_TIMER
892	jl	2f
893	la	%r14,__LC_LAST_UPDATE_TIMER
8942:	spt	0(%r14)
895	mvc	__LC_MCCK_ENTER_TIMER(8),0(%r14)
8963:	TSTMSK	__LC_MCCK_CODE,(MCCK_CODE_PSW_MWP_VALID|MCCK_CODE_PSW_IA_VALID)
897	jno	.Lmcck_panic		# no -> skip cleanup critical
898	SWITCH_ASYNC __LC_GPREGS_SAVE_AREA+64,__LC_MCCK_ENTER_TIMER
899.Lmcck_skip:
900	lghi	%r14,__LC_GPREGS_SAVE_AREA+64
901	stmg	%r0,%r7,__PT_R0(%r11)
902	mvc	__PT_R8(64,%r11),0(%r14)
903	stmg	%r8,%r9,__PT_PSW(%r11)
904	xc	__PT_FLAGS(8,%r11),__PT_FLAGS(%r11)
905	xc	__SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
906	lgr	%r2,%r11		# pass pointer to pt_regs
907	brasl	%r14,s390_do_machine_check
908	tm	__PT_PSW+1(%r11),0x01	# returning to user ?
909	jno	.Lmcck_return
910	lg	%r1,__LC_KERNEL_STACK	# switch to kernel stack
911	mvc	STACK_FRAME_OVERHEAD(__PT_SIZE,%r1),0(%r11)
912	xc	__SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1)
913	la	%r11,STACK_FRAME_OVERHEAD(%r1)
914	lgr	%r15,%r1
915	ssm	__LC_PGM_NEW_PSW	# turn dat on, keep irqs off
916	TSTMSK	__LC_CPU_FLAGS,_CIF_MCCK_PENDING
917	jno	.Lmcck_return
918	TRACE_IRQS_OFF
919	brasl	%r14,s390_handle_mcck
920	TRACE_IRQS_ON
921.Lmcck_return:
922	lg	%r14,__LC_VDSO_PER_CPU
923	lmg	%r0,%r10,__PT_R0(%r11)
924	mvc	__LC_RETURN_MCCK_PSW(16),__PT_PSW(%r11) # move return PSW
925	tm	__LC_RETURN_MCCK_PSW+1,0x01 # returning to user ?
926	jno	0f
927	stpt	__LC_EXIT_TIMER
928	mvc	__VDSO_ECTG_BASE(16,%r14),__LC_EXIT_TIMER
9290:	lmg	%r11,%r15,__PT_R11(%r11)
930	lpswe	__LC_RETURN_MCCK_PSW
931
932.Lmcck_panic:
933	lg	%r15,__LC_PANIC_STACK
934	aghi	%r15,-(STACK_FRAME_OVERHEAD + __PT_SIZE)
935	j	.Lmcck_skip
936
937#
938# PSW restart interrupt handler
939#
940ENTRY(restart_int_handler)
941	TSTMSK	__LC_MACHINE_FLAGS,MACHINE_FLAG_LPP
942	jz	0f
943	.insn	s,0xb2800000,__LC_LPP
9440:	stg	%r15,__LC_SAVE_AREA_RESTART
945	lg	%r15,__LC_RESTART_STACK
946	aghi	%r15,-__PT_SIZE			# create pt_regs on stack
947	xc	0(__PT_SIZE,%r15),0(%r15)
948	stmg	%r0,%r14,__PT_R0(%r15)
949	mvc	__PT_R15(8,%r15),__LC_SAVE_AREA_RESTART
950	mvc	__PT_PSW(16,%r15),__LC_RST_OLD_PSW # store restart old psw
951	aghi	%r15,-STACK_FRAME_OVERHEAD	# create stack frame on stack
952	xc	0(STACK_FRAME_OVERHEAD,%r15),0(%r15)
953	lg	%r1,__LC_RESTART_FN		# load fn, parm & source cpu
954	lg	%r2,__LC_RESTART_DATA
955	lg	%r3,__LC_RESTART_SOURCE
956	ltgr	%r3,%r3				# test source cpu address
957	jm	1f				# negative -> skip source stop
9580:	sigp	%r4,%r3,SIGP_SENSE		# sigp sense to source cpu
959	brc	10,0b				# wait for status stored
9601:	basr	%r14,%r1			# call function
961	stap	__SF_EMPTY(%r15)		# store cpu address
962	llgh	%r3,__SF_EMPTY(%r15)
9632:	sigp	%r4,%r3,SIGP_STOP		# sigp stop to current cpu
964	brc	2,2b
9653:	j	3b
966
967	.section .kprobes.text, "ax"
968
969#ifdef CONFIG_CHECK_STACK
970/*
971 * The synchronous or the asynchronous stack overflowed. We are dead.
972 * No need to properly save the registers, we are going to panic anyway.
973 * Setup a pt_regs so that show_trace can provide a good call trace.
974 */
975stack_overflow:
976	lg	%r15,__LC_PANIC_STACK	# change to panic stack
977	la	%r11,STACK_FRAME_OVERHEAD(%r15)
978	stmg	%r0,%r7,__PT_R0(%r11)
979	stmg	%r8,%r9,__PT_PSW(%r11)
980	mvc	__PT_R8(64,%r11),0(%r14)
981	stg	%r10,__PT_ORIG_GPR2(%r11) # store last break to orig_gpr2
982	xc	__SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
983	lgr	%r2,%r11		# pass pointer to pt_regs
984	jg	kernel_stack_overflow
985#endif
986
987cleanup_critical:
988#if IS_ENABLED(CONFIG_KVM)
989	clg	%r9,BASED(.Lcleanup_table_sie)	# .Lsie_gmap
990	jl	0f
991	clg	%r9,BASED(.Lcleanup_table_sie+8)# .Lsie_done
992	jl	.Lcleanup_sie
993#endif
994	clg	%r9,BASED(.Lcleanup_table)	# system_call
995	jl	0f
996	clg	%r9,BASED(.Lcleanup_table+8)	# .Lsysc_do_svc
997	jl	.Lcleanup_system_call
998	clg	%r9,BASED(.Lcleanup_table+16)	# .Lsysc_tif
999	jl	0f
1000	clg	%r9,BASED(.Lcleanup_table+24)	# .Lsysc_restore
1001	jl	.Lcleanup_sysc_tif
1002	clg	%r9,BASED(.Lcleanup_table+32)	# .Lsysc_done
1003	jl	.Lcleanup_sysc_restore
1004	clg	%r9,BASED(.Lcleanup_table+40)	# .Lio_tif
1005	jl	0f
1006	clg	%r9,BASED(.Lcleanup_table+48)	# .Lio_restore
1007	jl	.Lcleanup_io_tif
1008	clg	%r9,BASED(.Lcleanup_table+56)	# .Lio_done
1009	jl	.Lcleanup_io_restore
1010	clg	%r9,BASED(.Lcleanup_table+64)	# psw_idle
1011	jl	0f
1012	clg	%r9,BASED(.Lcleanup_table+72)	# .Lpsw_idle_end
1013	jl	.Lcleanup_idle
1014	clg	%r9,BASED(.Lcleanup_table+80)	# save_fpu_regs
1015	jl	0f
1016	clg	%r9,BASED(.Lcleanup_table+88)	# .Lsave_fpu_regs_end
1017	jl	.Lcleanup_save_fpu_regs
1018	clg	%r9,BASED(.Lcleanup_table+96)	# load_fpu_regs
1019	jl	0f
1020	clg	%r9,BASED(.Lcleanup_table+104)	# .Lload_fpu_regs_end
1021	jl	.Lcleanup_load_fpu_regs
10220:	br	%r14
1023
1024	.align	8
1025.Lcleanup_table:
1026	.quad	system_call
1027	.quad	.Lsysc_do_svc
1028	.quad	.Lsysc_tif
1029	.quad	.Lsysc_restore
1030	.quad	.Lsysc_done
1031	.quad	.Lio_tif
1032	.quad	.Lio_restore
1033	.quad	.Lio_done
1034	.quad	psw_idle
1035	.quad	.Lpsw_idle_end
1036	.quad	save_fpu_regs
1037	.quad	.Lsave_fpu_regs_end
1038	.quad	load_fpu_regs
1039	.quad	.Lload_fpu_regs_end
1040
1041#if IS_ENABLED(CONFIG_KVM)
1042.Lcleanup_table_sie:
1043	.quad	.Lsie_gmap
1044	.quad	.Lsie_done
1045
1046.Lcleanup_sie:
1047	lg	%r9,__SF_EMPTY(%r15)		# get control block pointer
1048	ni	__SIE_PROG0C+3(%r9),0xfe	# no longer in SIE
1049	lctlg	%c1,%c1,__LC_USER_ASCE		# load primary asce
1050	larl	%r9,sie_exit			# skip forward to sie_exit
1051	br	%r14
1052#endif
1053
1054.Lcleanup_system_call:
1055	# check if stpt has been executed
1056	clg	%r9,BASED(.Lcleanup_system_call_insn)
1057	jh	0f
1058	mvc	__LC_SYNC_ENTER_TIMER(8),__LC_ASYNC_ENTER_TIMER
1059	cghi	%r11,__LC_SAVE_AREA_ASYNC
1060	je	0f
1061	mvc	__LC_SYNC_ENTER_TIMER(8),__LC_MCCK_ENTER_TIMER
10620:	# check if stmg has been executed
1063	clg	%r9,BASED(.Lcleanup_system_call_insn+8)
1064	jh	0f
1065	mvc	__LC_SAVE_AREA_SYNC(64),0(%r11)
10660:	# check if base register setup + TIF bit load has been done
1067	clg	%r9,BASED(.Lcleanup_system_call_insn+16)
1068	jhe	0f
1069	# set up saved registers r10 and r12
1070	stg	%r10,16(%r11)		# r10 last break
1071	stg	%r12,32(%r11)		# r12 thread-info pointer
10720:	# check if the user time update has been done
1073	clg	%r9,BASED(.Lcleanup_system_call_insn+24)
1074	jh	0f
1075	lg	%r15,__LC_EXIT_TIMER
1076	slg	%r15,__LC_SYNC_ENTER_TIMER
1077	alg	%r15,__LC_USER_TIMER
1078	stg	%r15,__LC_USER_TIMER
10790:	# check if the system time update has been done
1080	clg	%r9,BASED(.Lcleanup_system_call_insn+32)
1081	jh	0f
1082	lg	%r15,__LC_LAST_UPDATE_TIMER
1083	slg	%r15,__LC_EXIT_TIMER
1084	alg	%r15,__LC_SYSTEM_TIMER
1085	stg	%r15,__LC_SYSTEM_TIMER
10860:	# update accounting time stamp
1087	mvc	__LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER
1088	# do LAST_BREAK
1089	lg	%r9,16(%r11)
1090	srag	%r9,%r9,23
1091	jz	0f
1092	mvc	__TI_last_break(8,%r12),16(%r11)
10930:	# set up saved register r11
1094	lg	%r15,__LC_KERNEL_STACK
1095	la	%r9,STACK_FRAME_OVERHEAD(%r15)
1096	stg	%r9,24(%r11)		# r11 pt_regs pointer
1097	# fill pt_regs
1098	mvc	__PT_R8(64,%r9),__LC_SAVE_AREA_SYNC
1099	stmg	%r0,%r7,__PT_R0(%r9)
1100	mvc	__PT_PSW(16,%r9),__LC_SVC_OLD_PSW
1101	mvc	__PT_INT_CODE(4,%r9),__LC_SVC_ILC
1102	xc	__PT_FLAGS(8,%r9),__PT_FLAGS(%r9)
1103	mvi	__PT_FLAGS+7(%r9),_PIF_SYSCALL
1104	# setup saved register r15
1105	stg	%r15,56(%r11)		# r15 stack pointer
1106	# set new psw address and exit
1107	larl	%r9,.Lsysc_do_svc
1108	br	%r14
1109.Lcleanup_system_call_insn:
1110	.quad	system_call
1111	.quad	.Lsysc_stmg
1112	.quad	.Lsysc_per
1113	.quad	.Lsysc_vtime+36
1114	.quad	.Lsysc_vtime+42
1115
1116.Lcleanup_sysc_tif:
1117	larl	%r9,.Lsysc_tif
1118	br	%r14
1119
1120.Lcleanup_sysc_restore:
1121	clg	%r9,BASED(.Lcleanup_sysc_restore_insn)
1122	je	0f
1123	lg	%r9,24(%r11)		# get saved pointer to pt_regs
1124	mvc	__LC_RETURN_PSW(16),__PT_PSW(%r9)
1125	mvc	0(64,%r11),__PT_R8(%r9)
1126	lmg	%r0,%r7,__PT_R0(%r9)
11270:	lmg	%r8,%r9,__LC_RETURN_PSW
1128	br	%r14
1129.Lcleanup_sysc_restore_insn:
1130	.quad	.Lsysc_done - 4
1131
1132.Lcleanup_io_tif:
1133	larl	%r9,.Lio_tif
1134	br	%r14
1135
1136.Lcleanup_io_restore:
1137	clg	%r9,BASED(.Lcleanup_io_restore_insn)
1138	je	0f
1139	lg	%r9,24(%r11)		# get saved r11 pointer to pt_regs
1140	mvc	__LC_RETURN_PSW(16),__PT_PSW(%r9)
1141	mvc	0(64,%r11),__PT_R8(%r9)
1142	lmg	%r0,%r7,__PT_R0(%r9)
11430:	lmg	%r8,%r9,__LC_RETURN_PSW
1144	br	%r14
1145.Lcleanup_io_restore_insn:
1146	.quad	.Lio_done - 4
1147
1148.Lcleanup_idle:
1149	# copy interrupt clock & cpu timer
1150	mvc	__CLOCK_IDLE_EXIT(8,%r2),__LC_INT_CLOCK
1151	mvc	__TIMER_IDLE_EXIT(8,%r2),__LC_ASYNC_ENTER_TIMER
1152	cghi	%r11,__LC_SAVE_AREA_ASYNC
1153	je	0f
1154	mvc	__CLOCK_IDLE_EXIT(8,%r2),__LC_MCCK_CLOCK
1155	mvc	__TIMER_IDLE_EXIT(8,%r2),__LC_MCCK_ENTER_TIMER
11560:	# check if stck & stpt have been executed
1157	clg	%r9,BASED(.Lcleanup_idle_insn)
1158	jhe	1f
1159	mvc	__CLOCK_IDLE_ENTER(8,%r2),__CLOCK_IDLE_EXIT(%r2)
1160	mvc	__TIMER_IDLE_ENTER(8,%r2),__TIMER_IDLE_EXIT(%r2)
11611:	# calculate idle cycles
1162#ifdef CONFIG_SMP
1163	clg	%r9,BASED(.Lcleanup_idle_insn)
1164	jl	3f
1165	larl	%r1,smp_cpu_mtid
1166	llgf	%r1,0(%r1)
1167	ltgr	%r1,%r1
1168	jz	3f
1169	.insn	rsy,0xeb0000000017,%r1,5,__SF_EMPTY+80(%r15)
1170	larl	%r3,mt_cycles
1171	ag	%r3,__LC_PERCPU_OFFSET
1172	la	%r4,__SF_EMPTY+16(%r15)
11732:	lg	%r0,0(%r3)
1174	slg	%r0,0(%r4)
1175	alg	%r0,64(%r4)
1176	stg	%r0,0(%r3)
1177	la	%r3,8(%r3)
1178	la	%r4,8(%r4)
1179	brct	%r1,2b
1180#endif
11813:	# account system time going idle
1182	lg	%r9,__LC_STEAL_TIMER
1183	alg	%r9,__CLOCK_IDLE_ENTER(%r2)
1184	slg	%r9,__LC_LAST_UPDATE_CLOCK
1185	stg	%r9,__LC_STEAL_TIMER
1186	mvc	__LC_LAST_UPDATE_CLOCK(8),__CLOCK_IDLE_EXIT(%r2)
1187	lg	%r9,__LC_SYSTEM_TIMER
1188	alg	%r9,__LC_LAST_UPDATE_TIMER
1189	slg	%r9,__TIMER_IDLE_ENTER(%r2)
1190	stg	%r9,__LC_SYSTEM_TIMER
1191	mvc	__LC_LAST_UPDATE_TIMER(8),__TIMER_IDLE_EXIT(%r2)
1192	# prepare return psw
1193	nihh	%r8,0xfcfd		# clear irq & wait state bits
1194	lg	%r9,48(%r11)		# return from psw_idle
1195	br	%r14
1196.Lcleanup_idle_insn:
1197	.quad	.Lpsw_idle_lpsw
1198
1199.Lcleanup_save_fpu_regs:
1200	TSTMSK	__LC_CPU_FLAGS,_CIF_FPU
1201	bor	%r14
1202	clg	%r9,BASED(.Lcleanup_save_fpu_regs_done)
1203	jhe	5f
1204	clg	%r9,BASED(.Lcleanup_save_fpu_regs_fp)
1205	jhe	4f
1206	clg	%r9,BASED(.Lcleanup_save_fpu_regs_vx_high)
1207	jhe	3f
1208	clg	%r9,BASED(.Lcleanup_save_fpu_regs_vx_low)
1209	jhe	2f
1210	clg	%r9,BASED(.Lcleanup_save_fpu_fpc_end)
1211	jhe	1f
1212	lg	%r2,__LC_CURRENT
1213	aghi	%r2,__TASK_thread
12140:	# Store floating-point controls
1215	stfpc	__THREAD_FPU_fpc(%r2)
12161:	# Load register save area and check if VX is active
1217	lg	%r3,__THREAD_FPU_regs(%r2)
1218	TSTMSK	__LC_MACHINE_FLAGS,MACHINE_FLAG_VX
1219	jz	4f			  # no VX -> store FP regs
12202:	# Store vector registers (V0-V15)
1221	VSTM	%v0,%v15,0,%r3		  # vstm 0,15,0(3)
12223:	# Store vector registers (V16-V31)
1223	VSTM	%v16,%v31,256,%r3	  # vstm 16,31,256(3)
1224	j	5f			  # -> done, set CIF_FPU flag
12254:	# Store floating-point registers
1226	std	0,0(%r3)
1227	std	1,8(%r3)
1228	std	2,16(%r3)
1229	std	3,24(%r3)
1230	std	4,32(%r3)
1231	std	5,40(%r3)
1232	std	6,48(%r3)
1233	std	7,56(%r3)
1234	std	8,64(%r3)
1235	std	9,72(%r3)
1236	std	10,80(%r3)
1237	std	11,88(%r3)
1238	std	12,96(%r3)
1239	std	13,104(%r3)
1240	std	14,112(%r3)
1241	std	15,120(%r3)
12425:	# Set CIF_FPU flag
1243	oi	__LC_CPU_FLAGS+7,_CIF_FPU
1244	lg	%r9,48(%r11)		# return from save_fpu_regs
1245	br	%r14
1246.Lcleanup_save_fpu_fpc_end:
1247	.quad	.Lsave_fpu_regs_fpc_end
1248.Lcleanup_save_fpu_regs_vx_low:
1249	.quad	.Lsave_fpu_regs_vx_low
1250.Lcleanup_save_fpu_regs_vx_high:
1251	.quad	.Lsave_fpu_regs_vx_high
1252.Lcleanup_save_fpu_regs_fp:
1253	.quad	.Lsave_fpu_regs_fp
1254.Lcleanup_save_fpu_regs_done:
1255	.quad	.Lsave_fpu_regs_done
1256
1257.Lcleanup_load_fpu_regs:
1258	TSTMSK	__LC_CPU_FLAGS,_CIF_FPU
1259	bnor	%r14
1260	clg	%r9,BASED(.Lcleanup_load_fpu_regs_done)
1261	jhe	1f
1262	clg	%r9,BASED(.Lcleanup_load_fpu_regs_fp)
1263	jhe	2f
1264	clg	%r9,BASED(.Lcleanup_load_fpu_regs_vx_high)
1265	jhe	3f
1266	clg	%r9,BASED(.Lcleanup_load_fpu_regs_vx)
1267	jhe	4f
1268	lg	%r4,__LC_CURRENT
1269	aghi	%r4,__TASK_thread
1270	lfpc	__THREAD_FPU_fpc(%r4)
1271	TSTMSK	__LC_MACHINE_FLAGS,MACHINE_FLAG_VX
1272	lg	%r4,__THREAD_FPU_regs(%r4)	# %r4 <- reg save area
1273	jz	2f				# -> no VX, load FP regs
12744:	# Load V0 ..V15 registers
1275	VLM	%v0,%v15,0,%r4
12763:	# Load V16..V31 registers
1277	VLM	%v16,%v31,256,%r4
1278	j	1f
12792:	# Load floating-point registers
1280	ld	0,0(%r4)
1281	ld	1,8(%r4)
1282	ld	2,16(%r4)
1283	ld	3,24(%r4)
1284	ld	4,32(%r4)
1285	ld	5,40(%r4)
1286	ld	6,48(%r4)
1287	ld	7,56(%r4)
1288	ld	8,64(%r4)
1289	ld	9,72(%r4)
1290	ld	10,80(%r4)
1291	ld	11,88(%r4)
1292	ld	12,96(%r4)
1293	ld	13,104(%r4)
1294	ld	14,112(%r4)
1295	ld	15,120(%r4)
12961:	# Clear CIF_FPU bit
1297	ni	__LC_CPU_FLAGS+7,255-_CIF_FPU
1298	lg	%r9,48(%r11)		# return from load_fpu_regs
1299	br	%r14
1300.Lcleanup_load_fpu_regs_vx:
1301	.quad	.Lload_fpu_regs_vx
1302.Lcleanup_load_fpu_regs_vx_high:
1303	.quad	.Lload_fpu_regs_vx_high
1304.Lcleanup_load_fpu_regs_fp:
1305	.quad	.Lload_fpu_regs_fp
1306.Lcleanup_load_fpu_regs_done:
1307	.quad	.Lload_fpu_regs_done
1308
1309/*
1310 * Integer constants
1311 */
1312	.align	8
1313.Lcritical_start:
1314	.quad	.L__critical_start
1315.Lcritical_length:
1316	.quad	.L__critical_end - .L__critical_start
1317#if IS_ENABLED(CONFIG_KVM)
1318.Lsie_critical_start:
1319	.quad	.Lsie_gmap
1320.Lsie_critical_length:
1321	.quad	.Lsie_done - .Lsie_gmap
1322#endif
1323
1324	.section .rodata, "a"
1325#define SYSCALL(esame,emu)	.long esame
1326	.globl	sys_call_table
1327sys_call_table:
1328#include "syscalls.S"
1329#undef SYSCALL
1330
1331#ifdef CONFIG_COMPAT
1332
1333#define SYSCALL(esame,emu)	.long emu
1334	.globl	sys_call_table_emu
1335sys_call_table_emu:
1336#include "syscalls.S"
1337#undef SYSCALL
1338#endif
1339