1 /* 2 * arch/s390/kernel/dis.c 3 * 4 * Disassemble s390 instructions. 5 * 6 * Copyright IBM Corp. 2007 7 * Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com), 8 */ 9 10 #include <linux/sched.h> 11 #include <linux/kernel.h> 12 #include <linux/string.h> 13 #include <linux/errno.h> 14 #include <linux/ptrace.h> 15 #include <linux/timer.h> 16 #include <linux/mm.h> 17 #include <linux/smp.h> 18 #include <linux/init.h> 19 #include <linux/interrupt.h> 20 #include <linux/delay.h> 21 #include <linux/module.h> 22 #include <linux/kallsyms.h> 23 #include <linux/reboot.h> 24 #include <linux/kprobes.h> 25 #include <linux/kdebug.h> 26 27 #include <asm/system.h> 28 #include <asm/uaccess.h> 29 #include <asm/io.h> 30 #include <asm/atomic.h> 31 #include <asm/mathemu.h> 32 #include <asm/cpcmd.h> 33 #include <asm/s390_ext.h> 34 #include <asm/lowcore.h> 35 #include <asm/debug.h> 36 37 #ifndef CONFIG_64BIT 38 #define ONELONG "%08lx: " 39 #else /* CONFIG_64BIT */ 40 #define ONELONG "%016lx: " 41 #endif /* CONFIG_64BIT */ 42 43 #define OPERAND_GPR 0x1 /* Operand printed as %rx */ 44 #define OPERAND_FPR 0x2 /* Operand printed as %fx */ 45 #define OPERAND_AR 0x4 /* Operand printed as %ax */ 46 #define OPERAND_CR 0x8 /* Operand printed as %cx */ 47 #define OPERAND_DISP 0x10 /* Operand printed as displacement */ 48 #define OPERAND_BASE 0x20 /* Operand printed as base register */ 49 #define OPERAND_INDEX 0x40 /* Operand printed as index register */ 50 #define OPERAND_PCREL 0x80 /* Operand printed as pc-relative symbol */ 51 #define OPERAND_SIGNED 0x100 /* Operand printed as signed value */ 52 #define OPERAND_LENGTH 0x200 /* Operand printed as length (+1) */ 53 54 enum { 55 UNUSED, /* Indicates the end of the operand list */ 56 R_8, /* GPR starting at position 8 */ 57 R_12, /* GPR starting at position 12 */ 58 R_16, /* GPR starting at position 16 */ 59 R_20, /* GPR starting at position 20 */ 60 R_24, /* GPR starting at position 24 */ 61 R_28, /* GPR starting at position 28 */ 62 R_32, /* GPR starting at position 32 */ 63 F_8, /* FPR starting at position 8 */ 64 F_12, /* FPR starting at position 12 */ 65 F_16, /* FPR starting at position 16 */ 66 F_20, /* FPR starting at position 16 */ 67 F_24, /* FPR starting at position 24 */ 68 F_28, /* FPR starting at position 28 */ 69 F_32, /* FPR starting at position 32 */ 70 A_8, /* Access reg. starting at position 8 */ 71 A_12, /* Access reg. starting at position 12 */ 72 A_24, /* Access reg. starting at position 24 */ 73 A_28, /* Access reg. starting at position 28 */ 74 C_8, /* Control reg. starting at position 8 */ 75 C_12, /* Control reg. starting at position 12 */ 76 B_16, /* Base register starting at position 16 */ 77 B_32, /* Base register starting at position 32 */ 78 X_12, /* Index register starting at position 12 */ 79 D_20, /* Displacement starting at position 20 */ 80 D_36, /* Displacement starting at position 36 */ 81 D20_20, /* 20 bit displacement starting at 20 */ 82 L4_8, /* 4 bit length starting at position 8 */ 83 L4_12, /* 4 bit length starting at position 12 */ 84 L8_8, /* 8 bit length starting at position 8 */ 85 U4_8, /* 4 bit unsigned value starting at 8 */ 86 U4_12, /* 4 bit unsigned value starting at 12 */ 87 U4_16, /* 4 bit unsigned value starting at 16 */ 88 U4_20, /* 4 bit unsigned value starting at 20 */ 89 U8_8, /* 8 bit unsigned value starting at 8 */ 90 U8_16, /* 8 bit unsigned value starting at 16 */ 91 I16_16, /* 16 bit signed value starting at 16 */ 92 U16_16, /* 16 bit unsigned value starting at 16 */ 93 J16_16, /* PC relative jump offset at 16 */ 94 J32_16, /* PC relative long offset at 16 */ 95 I32_16, /* 32 bit signed value starting at 16 */ 96 U32_16, /* 32 bit unsigned value starting at 16 */ 97 M_16, /* 4 bit optional mask starting at 16 */ 98 RO_28, /* optional GPR starting at position 28 */ 99 }; 100 101 /* 102 * Enumeration of the different instruction formats. 103 * For details consult the principles of operation. 104 */ 105 enum { 106 INSTR_INVALID, 107 INSTR_E, INSTR_RIE_RRP, INSTR_RIL_RI, INSTR_RIL_RP, INSTR_RIL_RU, 108 INSTR_RIL_UP, INSTR_RI_RI, INSTR_RI_RP, INSTR_RI_RU, INSTR_RI_UP, 109 INSTR_RRE_00, INSTR_RRE_0R, INSTR_RRE_AA, INSTR_RRE_AR, INSTR_RRE_F0, 110 INSTR_RRE_FF, INSTR_RRE_R0, INSTR_RRE_RA, INSTR_RRE_RF, INSTR_RRE_RR, 111 INSTR_RRE_RR_OPT, INSTR_RRF_F0FF, INSTR_RRF_FUFF, INSTR_RRF_M0RR, 112 INSTR_RRF_R0RR, INSTR_RRF_RURR, INSTR_RRF_U0FF, INSTR_RRF_U0RF, 113 INSTR_RR_FF, INSTR_RR_R0, INSTR_RR_RR, INSTR_RR_U0, INSTR_RR_UR, 114 INSTR_RSE_CCRD, INSTR_RSE_RRRD, INSTR_RSE_RURD, INSTR_RSI_RRP, 115 INSTR_RSL_R0RD, INSTR_RSY_AARD, INSTR_RSY_CCRD, INSTR_RSY_RRRD, 116 INSTR_RSY_RURD, INSTR_RS_AARD, INSTR_RS_CCRD, INSTR_RS_R0RD, 117 INSTR_RS_RRRD, INSTR_RS_RURD, INSTR_RXE_FRRD, INSTR_RXE_RRRD, 118 INSTR_RXF_FRRDF, INSTR_RXY_FRRD, INSTR_RXY_RRRD, INSTR_RX_FRRD, 119 INSTR_RX_RRRD, INSTR_RX_URRD, INSTR_SIY_URD, INSTR_SI_URD, 120 INSTR_SSE_RDRD, INSTR_SSF_RRDRD, INSTR_SS_L0RDRD, INSTR_SS_LIRDRD, 121 INSTR_SS_LLRDRD, INSTR_SS_RRRDRD, INSTR_SS_RRRDRD2, INSTR_SS_RRRDRD3, 122 INSTR_S_00, INSTR_S_RD, 123 }; 124 125 struct operand { 126 int bits; /* The number of bits in the operand. */ 127 int shift; /* The number of bits to shift. */ 128 int flags; /* One bit syntax flags. */ 129 }; 130 131 struct insn { 132 const char name[5]; 133 unsigned char opfrag; 134 unsigned char format; 135 }; 136 137 static const struct operand operands[] = 138 { 139 [UNUSED] = { 0, 0, 0 }, 140 [R_8] = { 4, 8, OPERAND_GPR }, 141 [R_12] = { 4, 12, OPERAND_GPR }, 142 [R_16] = { 4, 16, OPERAND_GPR }, 143 [R_20] = { 4, 20, OPERAND_GPR }, 144 [R_24] = { 4, 24, OPERAND_GPR }, 145 [R_28] = { 4, 28, OPERAND_GPR }, 146 [R_32] = { 4, 32, OPERAND_GPR }, 147 [F_8] = { 4, 8, OPERAND_FPR }, 148 [F_12] = { 4, 12, OPERAND_FPR }, 149 [F_16] = { 4, 16, OPERAND_FPR }, 150 [F_20] = { 4, 16, OPERAND_FPR }, 151 [F_24] = { 4, 24, OPERAND_FPR }, 152 [F_28] = { 4, 28, OPERAND_FPR }, 153 [F_32] = { 4, 32, OPERAND_FPR }, 154 [A_8] = { 4, 8, OPERAND_AR }, 155 [A_12] = { 4, 12, OPERAND_AR }, 156 [A_24] = { 4, 24, OPERAND_AR }, 157 [A_28] = { 4, 28, OPERAND_AR }, 158 [C_8] = { 4, 8, OPERAND_CR }, 159 [C_12] = { 4, 12, OPERAND_CR }, 160 [B_16] = { 4, 16, OPERAND_BASE | OPERAND_GPR }, 161 [B_32] = { 4, 32, OPERAND_BASE | OPERAND_GPR }, 162 [X_12] = { 4, 12, OPERAND_INDEX | OPERAND_GPR }, 163 [D_20] = { 12, 20, OPERAND_DISP }, 164 [D_36] = { 12, 36, OPERAND_DISP }, 165 [D20_20] = { 20, 20, OPERAND_DISP | OPERAND_SIGNED }, 166 [L4_8] = { 4, 8, OPERAND_LENGTH }, 167 [L4_12] = { 4, 12, OPERAND_LENGTH }, 168 [L8_8] = { 8, 8, OPERAND_LENGTH }, 169 [U4_8] = { 4, 8, 0 }, 170 [U4_12] = { 4, 12, 0 }, 171 [U4_16] = { 4, 16, 0 }, 172 [U4_20] = { 4, 20, 0 }, 173 [U8_8] = { 8, 8, 0 }, 174 [U8_16] = { 8, 16, 0 }, 175 [I16_16] = { 16, 16, OPERAND_SIGNED }, 176 [U16_16] = { 16, 16, 0 }, 177 [J16_16] = { 16, 16, OPERAND_PCREL }, 178 [J32_16] = { 32, 16, OPERAND_PCREL }, 179 [I32_16] = { 32, 16, OPERAND_SIGNED }, 180 [U32_16] = { 32, 16, 0 }, 181 [M_16] = { 4, 16, 0 }, 182 [RO_28] = { 4, 28, OPERAND_GPR } 183 }; 184 185 static const unsigned char formats[][7] = { 186 [INSTR_E] = { 0xff, 0,0,0,0,0,0 }, /* e.g. pr */ 187 [INSTR_RIE_RRP] = { 0xff, R_8,R_12,J16_16,0,0,0 }, /* e.g. brxhg */ 188 [INSTR_RIL_RP] = { 0x0f, R_8,J32_16,0,0,0,0 }, /* e.g. brasl */ 189 [INSTR_RIL_UP] = { 0x0f, U4_8,J32_16,0,0,0,0 }, /* e.g. brcl */ 190 [INSTR_RIL_RI] = { 0x0f, R_8,I32_16,0,0,0,0 }, /* e.g. afi */ 191 [INSTR_RIL_RU] = { 0x0f, R_8,U32_16,0,0,0,0 }, /* e.g. alfi */ 192 [INSTR_RI_RI] = { 0x0f, R_8,I16_16,0,0,0,0 }, /* e.g. ahi */ 193 [INSTR_RI_RP] = { 0x0f, R_8,J16_16,0,0,0,0 }, /* e.g. brct */ 194 [INSTR_RI_RU] = { 0x0f, R_8,U16_16,0,0,0,0 }, /* e.g. tml */ 195 [INSTR_RI_UP] = { 0x0f, U4_8,J16_16,0,0,0,0 }, /* e.g. brc */ 196 [INSTR_RRE_00] = { 0xff, 0,0,0,0,0,0 }, /* e.g. palb */ 197 [INSTR_RRE_0R] = { 0xff, R_28,0,0,0,0,0 }, /* e.g. tb */ 198 [INSTR_RRE_AA] = { 0xff, A_24,A_28,0,0,0,0 }, /* e.g. cpya */ 199 [INSTR_RRE_AR] = { 0xff, A_24,R_28,0,0,0,0 }, /* e.g. sar */ 200 [INSTR_RRE_F0] = { 0xff, F_24,0,0,0,0,0 }, /* e.g. sqer */ 201 [INSTR_RRE_FF] = { 0xff, F_24,F_28,0,0,0,0 }, /* e.g. debr */ 202 [INSTR_RRE_R0] = { 0xff, R_24,0,0,0,0,0 }, /* e.g. ipm */ 203 [INSTR_RRE_RA] = { 0xff, R_24,A_28,0,0,0,0 }, /* e.g. ear */ 204 [INSTR_RRE_RF] = { 0xff, R_24,F_28,0,0,0,0 }, /* e.g. cefbr */ 205 [INSTR_RRE_RR] = { 0xff, R_24,R_28,0,0,0,0 }, /* e.g. lura */ 206 [INSTR_RRE_RR_OPT]= { 0xff, R_24,RO_28,0,0,0,0 }, /* efpc, sfpc */ 207 [INSTR_RRF_F0FF] = { 0xff, F_16,F_24,F_28,0,0,0 }, /* e.g. madbr */ 208 [INSTR_RRF_FUFF] = { 0xff, F_24,F_16,F_28,U4_20,0,0 },/* e.g. didbr */ 209 [INSTR_RRF_RURR] = { 0xff, R_24,R_28,R_16,U4_20,0,0 },/* e.g. .insn */ 210 [INSTR_RRF_R0RR] = { 0xff, R_24,R_16,R_28,0,0,0 }, /* e.g. idte */ 211 [INSTR_RRF_U0FF] = { 0xff, F_24,U4_16,F_28,0,0,0 }, /* e.g. fixr */ 212 [INSTR_RRF_U0RF] = { 0xff, R_24,U4_16,F_28,0,0,0 }, /* e.g. cfebr */ 213 [INSTR_RRF_M0RR] = { 0xff, R_24,R_28,M_16,0,0,0 }, /* e.g. sske */ 214 [INSTR_RR_FF] = { 0xff, F_8,F_12,0,0,0,0 }, /* e.g. adr */ 215 [INSTR_RR_R0] = { 0xff, R_8, 0,0,0,0,0 }, /* e.g. spm */ 216 [INSTR_RR_RR] = { 0xff, R_8,R_12,0,0,0,0 }, /* e.g. lr */ 217 [INSTR_RR_U0] = { 0xff, U8_8, 0,0,0,0,0 }, /* e.g. svc */ 218 [INSTR_RR_UR] = { 0xff, U4_8,R_12,0,0,0,0 }, /* e.g. bcr */ 219 [INSTR_RSE_RRRD] = { 0xff, R_8,R_12,D_20,B_16,0,0 }, /* e.g. lmh */ 220 [INSTR_RSE_CCRD] = { 0xff, C_8,C_12,D_20,B_16,0,0 }, /* e.g. lmh */ 221 [INSTR_RSE_RURD] = { 0xff, R_8,U4_12,D_20,B_16,0,0 }, /* e.g. icmh */ 222 [INSTR_RSL_R0RD] = { 0xff, R_8,D_20,B_16,0,0,0 }, /* e.g. tp */ 223 [INSTR_RSI_RRP] = { 0xff, R_8,R_12,J16_16,0,0,0 }, /* e.g. brxh */ 224 [INSTR_RSY_RRRD] = { 0xff, R_8,R_12,D20_20,B_16,0,0 },/* e.g. stmy */ 225 [INSTR_RSY_RURD] = { 0xff, R_8,U4_12,D20_20,B_16,0,0 }, 226 /* e.g. icmh */ 227 [INSTR_RSY_AARD] = { 0xff, A_8,A_12,D20_20,B_16,0,0 },/* e.g. lamy */ 228 [INSTR_RSY_CCRD] = { 0xff, C_8,C_12,D20_20,B_16,0,0 },/* e.g. lamy */ 229 [INSTR_RS_AARD] = { 0xff, A_8,A_12,D_20,B_16,0,0 }, /* e.g. lam */ 230 [INSTR_RS_CCRD] = { 0xff, C_8,C_12,D_20,B_16,0,0 }, /* e.g. lctl */ 231 [INSTR_RS_R0RD] = { 0xff, R_8,D_20,B_16,0,0,0 }, /* e.g. sll */ 232 [INSTR_RS_RRRD] = { 0xff, R_8,R_12,D_20,B_16,0,0 }, /* e.g. cs */ 233 [INSTR_RS_RURD] = { 0xff, R_8,U4_12,D_20,B_16,0,0 }, /* e.g. icm */ 234 [INSTR_RXE_FRRD] = { 0xff, F_8,D_20,X_12,B_16,0,0 }, /* e.g. axbr */ 235 [INSTR_RXE_RRRD] = { 0xff, R_8,D_20,X_12,B_16,0,0 }, /* e.g. lg */ 236 [INSTR_RXF_FRRDF] = { 0xff, F_32,F_8,D_20,X_12,B_16,0 }, 237 /* e.g. madb */ 238 [INSTR_RXY_RRRD] = { 0xff, R_8,D20_20,X_12,B_16,0,0 },/* e.g. ly */ 239 [INSTR_RXY_FRRD] = { 0xff, F_8,D20_20,X_12,B_16,0,0 },/* e.g. ley */ 240 [INSTR_RX_FRRD] = { 0xff, F_8,D_20,X_12,B_16,0,0 }, /* e.g. ae */ 241 [INSTR_RX_RRRD] = { 0xff, R_8,D_20,X_12,B_16,0,0 }, /* e.g. l */ 242 [INSTR_RX_URRD] = { 0xff, U4_8,D_20,X_12,B_16,0,0 }, /* e.g. bc */ 243 [INSTR_SI_URD] = { 0xff, D_20,B_16,U8_8,0,0,0 }, /* e.g. cli */ 244 [INSTR_SIY_URD] = { 0xff, D20_20,B_16,U8_8,0,0,0 }, /* e.g. tmy */ 245 [INSTR_SSE_RDRD] = { 0xff, D_20,B_16,D_36,B_32,0,0 }, /* e.g. mvsdk */ 246 [INSTR_SS_L0RDRD] = { 0xff, D_20,L8_8,B_16,D_36,B_32,0 }, 247 /* e.g. mvc */ 248 [INSTR_SS_LIRDRD] = { 0xff, D_20,L4_8,B_16,D_36,B_32,U4_12 }, 249 /* e.g. srp */ 250 [INSTR_SS_LLRDRD] = { 0xff, D_20,L4_8,B_16,D_36,L4_12,B_32 }, 251 /* e.g. pack */ 252 [INSTR_SS_RRRDRD] = { 0xff, D_20,R_8,B_16,D_36,B_32,R_12 }, 253 /* e.g. mvck */ 254 [INSTR_SS_RRRDRD2]= { 0xff, R_8,D_20,B_16,R_12,D_36,B_32 }, 255 /* e.g. plo */ 256 [INSTR_SS_RRRDRD3]= { 0xff, R_8,R_12,D_20,B_16,D_36,B_32 }, 257 /* e.g. lmd */ 258 [INSTR_S_00] = { 0xff, 0,0,0,0,0,0 }, /* e.g. hsch */ 259 [INSTR_S_RD] = { 0xff, D_20,B_16,0,0,0,0 }, /* e.g. lpsw */ 260 [INSTR_SSF_RRDRD] = { 0x00, D_20,B_16,D_36,B_32,R_8,0 }, 261 /* e.g. mvcos */ 262 }; 263 264 static struct insn opcode[] = { 265 #ifdef CONFIG_64BIT 266 { "lmd", 0xef, INSTR_SS_RRRDRD3 }, 267 #endif 268 { "spm", 0x04, INSTR_RR_R0 }, 269 { "balr", 0x05, INSTR_RR_RR }, 270 { "bctr", 0x06, INSTR_RR_RR }, 271 { "bcr", 0x07, INSTR_RR_UR }, 272 { "svc", 0x0a, INSTR_RR_U0 }, 273 { "bsm", 0x0b, INSTR_RR_RR }, 274 { "bassm", 0x0c, INSTR_RR_RR }, 275 { "basr", 0x0d, INSTR_RR_RR }, 276 { "mvcl", 0x0e, INSTR_RR_RR }, 277 { "clcl", 0x0f, INSTR_RR_RR }, 278 { "lpr", 0x10, INSTR_RR_RR }, 279 { "lnr", 0x11, INSTR_RR_RR }, 280 { "ltr", 0x12, INSTR_RR_RR }, 281 { "lcr", 0x13, INSTR_RR_RR }, 282 { "nr", 0x14, INSTR_RR_RR }, 283 { "clr", 0x15, INSTR_RR_RR }, 284 { "or", 0x16, INSTR_RR_RR }, 285 { "xr", 0x17, INSTR_RR_RR }, 286 { "lr", 0x18, INSTR_RR_RR }, 287 { "cr", 0x19, INSTR_RR_RR }, 288 { "ar", 0x1a, INSTR_RR_RR }, 289 { "sr", 0x1b, INSTR_RR_RR }, 290 { "mr", 0x1c, INSTR_RR_RR }, 291 { "dr", 0x1d, INSTR_RR_RR }, 292 { "alr", 0x1e, INSTR_RR_RR }, 293 { "slr", 0x1f, INSTR_RR_RR }, 294 { "lpdr", 0x20, INSTR_RR_FF }, 295 { "lndr", 0x21, INSTR_RR_FF }, 296 { "ltdr", 0x22, INSTR_RR_FF }, 297 { "lcdr", 0x23, INSTR_RR_FF }, 298 { "hdr", 0x24, INSTR_RR_FF }, 299 { "ldxr", 0x25, INSTR_RR_FF }, 300 { "lrdr", 0x25, INSTR_RR_FF }, 301 { "mxr", 0x26, INSTR_RR_FF }, 302 { "mxdr", 0x27, INSTR_RR_FF }, 303 { "ldr", 0x28, INSTR_RR_FF }, 304 { "cdr", 0x29, INSTR_RR_FF }, 305 { "adr", 0x2a, INSTR_RR_FF }, 306 { "sdr", 0x2b, INSTR_RR_FF }, 307 { "mdr", 0x2c, INSTR_RR_FF }, 308 { "ddr", 0x2d, INSTR_RR_FF }, 309 { "awr", 0x2e, INSTR_RR_FF }, 310 { "swr", 0x2f, INSTR_RR_FF }, 311 { "lper", 0x30, INSTR_RR_FF }, 312 { "lner", 0x31, INSTR_RR_FF }, 313 { "lter", 0x32, INSTR_RR_FF }, 314 { "lcer", 0x33, INSTR_RR_FF }, 315 { "her", 0x34, INSTR_RR_FF }, 316 { "ledr", 0x35, INSTR_RR_FF }, 317 { "lrer", 0x35, INSTR_RR_FF }, 318 { "axr", 0x36, INSTR_RR_FF }, 319 { "sxr", 0x37, INSTR_RR_FF }, 320 { "ler", 0x38, INSTR_RR_FF }, 321 { "cer", 0x39, INSTR_RR_FF }, 322 { "aer", 0x3a, INSTR_RR_FF }, 323 { "ser", 0x3b, INSTR_RR_FF }, 324 { "mder", 0x3c, INSTR_RR_FF }, 325 { "mer", 0x3c, INSTR_RR_FF }, 326 { "der", 0x3d, INSTR_RR_FF }, 327 { "aur", 0x3e, INSTR_RR_FF }, 328 { "sur", 0x3f, INSTR_RR_FF }, 329 { "sth", 0x40, INSTR_RX_RRRD }, 330 { "la", 0x41, INSTR_RX_RRRD }, 331 { "stc", 0x42, INSTR_RX_RRRD }, 332 { "ic", 0x43, INSTR_RX_RRRD }, 333 { "ex", 0x44, INSTR_RX_RRRD }, 334 { "bal", 0x45, INSTR_RX_RRRD }, 335 { "bct", 0x46, INSTR_RX_RRRD }, 336 { "bc", 0x47, INSTR_RX_URRD }, 337 { "lh", 0x48, INSTR_RX_RRRD }, 338 { "ch", 0x49, INSTR_RX_RRRD }, 339 { "ah", 0x4a, INSTR_RX_RRRD }, 340 { "sh", 0x4b, INSTR_RX_RRRD }, 341 { "mh", 0x4c, INSTR_RX_RRRD }, 342 { "bas", 0x4d, INSTR_RX_RRRD }, 343 { "cvd", 0x4e, INSTR_RX_RRRD }, 344 { "cvb", 0x4f, INSTR_RX_RRRD }, 345 { "st", 0x50, INSTR_RX_RRRD }, 346 { "lae", 0x51, INSTR_RX_RRRD }, 347 { "n", 0x54, INSTR_RX_RRRD }, 348 { "cl", 0x55, INSTR_RX_RRRD }, 349 { "o", 0x56, INSTR_RX_RRRD }, 350 { "x", 0x57, INSTR_RX_RRRD }, 351 { "l", 0x58, INSTR_RX_RRRD }, 352 { "c", 0x59, INSTR_RX_RRRD }, 353 { "a", 0x5a, INSTR_RX_RRRD }, 354 { "s", 0x5b, INSTR_RX_RRRD }, 355 { "m", 0x5c, INSTR_RX_RRRD }, 356 { "d", 0x5d, INSTR_RX_RRRD }, 357 { "al", 0x5e, INSTR_RX_RRRD }, 358 { "sl", 0x5f, INSTR_RX_RRRD }, 359 { "std", 0x60, INSTR_RX_FRRD }, 360 { "mxd", 0x67, INSTR_RX_FRRD }, 361 { "ld", 0x68, INSTR_RX_FRRD }, 362 { "cd", 0x69, INSTR_RX_FRRD }, 363 { "ad", 0x6a, INSTR_RX_FRRD }, 364 { "sd", 0x6b, INSTR_RX_FRRD }, 365 { "md", 0x6c, INSTR_RX_FRRD }, 366 { "dd", 0x6d, INSTR_RX_FRRD }, 367 { "aw", 0x6e, INSTR_RX_FRRD }, 368 { "sw", 0x6f, INSTR_RX_FRRD }, 369 { "ste", 0x70, INSTR_RX_FRRD }, 370 { "ms", 0x71, INSTR_RX_RRRD }, 371 { "le", 0x78, INSTR_RX_FRRD }, 372 { "ce", 0x79, INSTR_RX_FRRD }, 373 { "ae", 0x7a, INSTR_RX_FRRD }, 374 { "se", 0x7b, INSTR_RX_FRRD }, 375 { "mde", 0x7c, INSTR_RX_FRRD }, 376 { "me", 0x7c, INSTR_RX_FRRD }, 377 { "de", 0x7d, INSTR_RX_FRRD }, 378 { "au", 0x7e, INSTR_RX_FRRD }, 379 { "su", 0x7f, INSTR_RX_FRRD }, 380 { "ssm", 0x80, INSTR_S_RD }, 381 { "lpsw", 0x82, INSTR_S_RD }, 382 { "diag", 0x83, INSTR_RS_RRRD }, 383 { "brxh", 0x84, INSTR_RSI_RRP }, 384 { "brxle", 0x85, INSTR_RSI_RRP }, 385 { "bxh", 0x86, INSTR_RS_RRRD }, 386 { "bxle", 0x87, INSTR_RS_RRRD }, 387 { "srl", 0x88, INSTR_RS_R0RD }, 388 { "sll", 0x89, INSTR_RS_R0RD }, 389 { "sra", 0x8a, INSTR_RS_R0RD }, 390 { "sla", 0x8b, INSTR_RS_R0RD }, 391 { "srdl", 0x8c, INSTR_RS_R0RD }, 392 { "sldl", 0x8d, INSTR_RS_R0RD }, 393 { "srda", 0x8e, INSTR_RS_R0RD }, 394 { "slda", 0x8f, INSTR_RS_R0RD }, 395 { "stm", 0x90, INSTR_RS_RRRD }, 396 { "tm", 0x91, INSTR_SI_URD }, 397 { "mvi", 0x92, INSTR_SI_URD }, 398 { "ts", 0x93, INSTR_S_RD }, 399 { "ni", 0x94, INSTR_SI_URD }, 400 { "cli", 0x95, INSTR_SI_URD }, 401 { "oi", 0x96, INSTR_SI_URD }, 402 { "xi", 0x97, INSTR_SI_URD }, 403 { "lm", 0x98, INSTR_RS_RRRD }, 404 { "trace", 0x99, INSTR_RS_RRRD }, 405 { "lam", 0x9a, INSTR_RS_AARD }, 406 { "stam", 0x9b, INSTR_RS_AARD }, 407 { "mvcle", 0xa8, INSTR_RS_RRRD }, 408 { "clcle", 0xa9, INSTR_RS_RRRD }, 409 { "stnsm", 0xac, INSTR_SI_URD }, 410 { "stosm", 0xad, INSTR_SI_URD }, 411 { "sigp", 0xae, INSTR_RS_RRRD }, 412 { "mc", 0xaf, INSTR_SI_URD }, 413 { "lra", 0xb1, INSTR_RX_RRRD }, 414 { "stctl", 0xb6, INSTR_RS_CCRD }, 415 { "lctl", 0xb7, INSTR_RS_CCRD }, 416 { "cs", 0xba, INSTR_RS_RRRD }, 417 { "cds", 0xbb, INSTR_RS_RRRD }, 418 { "clm", 0xbd, INSTR_RS_RURD }, 419 { "stcm", 0xbe, INSTR_RS_RURD }, 420 { "icm", 0xbf, INSTR_RS_RURD }, 421 { "mvn", 0xd1, INSTR_SS_L0RDRD }, 422 { "mvc", 0xd2, INSTR_SS_L0RDRD }, 423 { "mvz", 0xd3, INSTR_SS_L0RDRD }, 424 { "nc", 0xd4, INSTR_SS_L0RDRD }, 425 { "clc", 0xd5, INSTR_SS_L0RDRD }, 426 { "oc", 0xd6, INSTR_SS_L0RDRD }, 427 { "xc", 0xd7, INSTR_SS_L0RDRD }, 428 { "mvck", 0xd9, INSTR_SS_RRRDRD }, 429 { "mvcp", 0xda, INSTR_SS_RRRDRD }, 430 { "mvcs", 0xdb, INSTR_SS_RRRDRD }, 431 { "tr", 0xdc, INSTR_SS_L0RDRD }, 432 { "trt", 0xdd, INSTR_SS_L0RDRD }, 433 { "ed", 0xde, INSTR_SS_L0RDRD }, 434 { "edmk", 0xdf, INSTR_SS_L0RDRD }, 435 { "pku", 0xe1, INSTR_SS_L0RDRD }, 436 { "unpku", 0xe2, INSTR_SS_L0RDRD }, 437 { "mvcin", 0xe8, INSTR_SS_L0RDRD }, 438 { "pka", 0xe9, INSTR_SS_L0RDRD }, 439 { "unpka", 0xea, INSTR_SS_L0RDRD }, 440 { "plo", 0xee, INSTR_SS_RRRDRD2 }, 441 { "srp", 0xf0, INSTR_SS_LIRDRD }, 442 { "mvo", 0xf1, INSTR_SS_LLRDRD }, 443 { "pack", 0xf2, INSTR_SS_LLRDRD }, 444 { "unpk", 0xf3, INSTR_SS_LLRDRD }, 445 { "zap", 0xf8, INSTR_SS_LLRDRD }, 446 { "cp", 0xf9, INSTR_SS_LLRDRD }, 447 { "ap", 0xfa, INSTR_SS_LLRDRD }, 448 { "sp", 0xfb, INSTR_SS_LLRDRD }, 449 { "mp", 0xfc, INSTR_SS_LLRDRD }, 450 { "dp", 0xfd, INSTR_SS_LLRDRD }, 451 { "", 0, INSTR_INVALID } 452 }; 453 454 static struct insn opcode_01[] = { 455 #ifdef CONFIG_64BIT 456 { "sam64", 0x0e, INSTR_E }, 457 #endif 458 { "pr", 0x01, INSTR_E }, 459 { "upt", 0x02, INSTR_E }, 460 { "sckpf", 0x07, INSTR_E }, 461 { "tam", 0x0b, INSTR_E }, 462 { "sam24", 0x0c, INSTR_E }, 463 { "sam31", 0x0d, INSTR_E }, 464 { "trap2", 0xff, INSTR_E }, 465 { "", 0, INSTR_INVALID } 466 }; 467 468 static struct insn opcode_a5[] = { 469 #ifdef CONFIG_64BIT 470 { "iihh", 0x00, INSTR_RI_RU }, 471 { "iihl", 0x01, INSTR_RI_RU }, 472 { "iilh", 0x02, INSTR_RI_RU }, 473 { "iill", 0x03, INSTR_RI_RU }, 474 { "nihh", 0x04, INSTR_RI_RU }, 475 { "nihl", 0x05, INSTR_RI_RU }, 476 { "nilh", 0x06, INSTR_RI_RU }, 477 { "nill", 0x07, INSTR_RI_RU }, 478 { "oihh", 0x08, INSTR_RI_RU }, 479 { "oihl", 0x09, INSTR_RI_RU }, 480 { "oilh", 0x0a, INSTR_RI_RU }, 481 { "oill", 0x0b, INSTR_RI_RU }, 482 { "llihh", 0x0c, INSTR_RI_RU }, 483 { "llihl", 0x0d, INSTR_RI_RU }, 484 { "llilh", 0x0e, INSTR_RI_RU }, 485 { "llill", 0x0f, INSTR_RI_RU }, 486 #endif 487 { "", 0, INSTR_INVALID } 488 }; 489 490 static struct insn opcode_a7[] = { 491 #ifdef CONFIG_64BIT 492 { "tmhh", 0x02, INSTR_RI_RU }, 493 { "tmhl", 0x03, INSTR_RI_RU }, 494 { "brctg", 0x07, INSTR_RI_RP }, 495 { "lghi", 0x09, INSTR_RI_RI }, 496 { "aghi", 0x0b, INSTR_RI_RI }, 497 { "mghi", 0x0d, INSTR_RI_RI }, 498 { "cghi", 0x0f, INSTR_RI_RI }, 499 #endif 500 { "tmlh", 0x00, INSTR_RI_RU }, 501 { "tmll", 0x01, INSTR_RI_RU }, 502 { "brc", 0x04, INSTR_RI_UP }, 503 { "bras", 0x05, INSTR_RI_RP }, 504 { "brct", 0x06, INSTR_RI_RP }, 505 { "lhi", 0x08, INSTR_RI_RI }, 506 { "ahi", 0x0a, INSTR_RI_RI }, 507 { "mhi", 0x0c, INSTR_RI_RI }, 508 { "chi", 0x0e, INSTR_RI_RI }, 509 { "", 0, INSTR_INVALID } 510 }; 511 512 static struct insn opcode_b2[] = { 513 #ifdef CONFIG_64BIT 514 { "sske", 0x2b, INSTR_RRF_M0RR }, 515 { "stckf", 0x7c, INSTR_S_RD }, 516 { "cu21", 0xa6, INSTR_RRF_M0RR }, 517 { "cuutf", 0xa6, INSTR_RRF_M0RR }, 518 { "cu12", 0xa7, INSTR_RRF_M0RR }, 519 { "cutfu", 0xa7, INSTR_RRF_M0RR }, 520 { "stfle", 0xb0, INSTR_S_RD }, 521 { "lpswe", 0xb2, INSTR_S_RD }, 522 #endif 523 { "stidp", 0x02, INSTR_S_RD }, 524 { "sck", 0x04, INSTR_S_RD }, 525 { "stck", 0x05, INSTR_S_RD }, 526 { "sckc", 0x06, INSTR_S_RD }, 527 { "stckc", 0x07, INSTR_S_RD }, 528 { "spt", 0x08, INSTR_S_RD }, 529 { "stpt", 0x09, INSTR_S_RD }, 530 { "spka", 0x0a, INSTR_S_RD }, 531 { "ipk", 0x0b, INSTR_S_00 }, 532 { "ptlb", 0x0d, INSTR_S_00 }, 533 { "spx", 0x10, INSTR_S_RD }, 534 { "stpx", 0x11, INSTR_S_RD }, 535 { "stap", 0x12, INSTR_S_RD }, 536 { "sie", 0x14, INSTR_S_RD }, 537 { "pc", 0x18, INSTR_S_RD }, 538 { "sac", 0x19, INSTR_S_RD }, 539 { "cfc", 0x1a, INSTR_S_RD }, 540 { "ipte", 0x21, INSTR_RRE_RR }, 541 { "ipm", 0x22, INSTR_RRE_R0 }, 542 { "ivsk", 0x23, INSTR_RRE_RR }, 543 { "iac", 0x24, INSTR_RRE_R0 }, 544 { "ssar", 0x25, INSTR_RRE_R0 }, 545 { "epar", 0x26, INSTR_RRE_R0 }, 546 { "esar", 0x27, INSTR_RRE_R0 }, 547 { "pt", 0x28, INSTR_RRE_RR }, 548 { "iske", 0x29, INSTR_RRE_RR }, 549 { "rrbe", 0x2a, INSTR_RRE_RR }, 550 { "sske", 0x2b, INSTR_RRE_RR }, 551 { "tb", 0x2c, INSTR_RRE_0R }, 552 { "dxr", 0x2d, INSTR_RRE_F0 }, 553 { "pgin", 0x2e, INSTR_RRE_RR }, 554 { "pgout", 0x2f, INSTR_RRE_RR }, 555 { "csch", 0x30, INSTR_S_00 }, 556 { "hsch", 0x31, INSTR_S_00 }, 557 { "msch", 0x32, INSTR_S_RD }, 558 { "ssch", 0x33, INSTR_S_RD }, 559 { "stsch", 0x34, INSTR_S_RD }, 560 { "tsch", 0x35, INSTR_S_RD }, 561 { "tpi", 0x36, INSTR_S_RD }, 562 { "sal", 0x37, INSTR_S_00 }, 563 { "rsch", 0x38, INSTR_S_00 }, 564 { "stcrw", 0x39, INSTR_S_RD }, 565 { "stcps", 0x3a, INSTR_S_RD }, 566 { "rchp", 0x3b, INSTR_S_00 }, 567 { "schm", 0x3c, INSTR_S_00 }, 568 { "bakr", 0x40, INSTR_RRE_RR }, 569 { "cksm", 0x41, INSTR_RRE_RR }, 570 { "sqdr", 0x44, INSTR_RRE_F0 }, 571 { "sqer", 0x45, INSTR_RRE_F0 }, 572 { "stura", 0x46, INSTR_RRE_RR }, 573 { "msta", 0x47, INSTR_RRE_R0 }, 574 { "palb", 0x48, INSTR_RRE_00 }, 575 { "ereg", 0x49, INSTR_RRE_RR }, 576 { "esta", 0x4a, INSTR_RRE_RR }, 577 { "lura", 0x4b, INSTR_RRE_RR }, 578 { "tar", 0x4c, INSTR_RRE_AR }, 579 { "cpya", 0x4d, INSTR_RRE_AA }, 580 { "sar", 0x4e, INSTR_RRE_AR }, 581 { "ear", 0x4f, INSTR_RRE_RA }, 582 { "csp", 0x50, INSTR_RRE_RR }, 583 { "msr", 0x52, INSTR_RRE_RR }, 584 { "mvpg", 0x54, INSTR_RRE_RR }, 585 { "mvst", 0x55, INSTR_RRE_RR }, 586 { "cuse", 0x57, INSTR_RRE_RR }, 587 { "bsg", 0x58, INSTR_RRE_RR }, 588 { "bsa", 0x5a, INSTR_RRE_RR }, 589 { "clst", 0x5d, INSTR_RRE_RR }, 590 { "srst", 0x5e, INSTR_RRE_RR }, 591 { "cmpsc", 0x63, INSTR_RRE_RR }, 592 { "cmpsc", 0x63, INSTR_RRE_RR }, 593 { "siga", 0x74, INSTR_S_RD }, 594 { "xsch", 0x76, INSTR_S_00 }, 595 { "rp", 0x77, INSTR_S_RD }, 596 { "stcke", 0x78, INSTR_S_RD }, 597 { "sacf", 0x79, INSTR_S_RD }, 598 { "stsi", 0x7d, INSTR_S_RD }, 599 { "srnm", 0x99, INSTR_S_RD }, 600 { "stfpc", 0x9c, INSTR_S_RD }, 601 { "lfpc", 0x9d, INSTR_S_RD }, 602 { "tre", 0xa5, INSTR_RRE_RR }, 603 { "cuutf", 0xa6, INSTR_RRE_RR }, 604 { "cutfu", 0xa7, INSTR_RRE_RR }, 605 { "stfl", 0xb1, INSTR_S_RD }, 606 { "trap4", 0xff, INSTR_S_RD }, 607 { "", 0, INSTR_INVALID } 608 }; 609 610 static struct insn opcode_b3[] = { 611 #ifdef CONFIG_64BIT 612 { "maylr", 0x38, INSTR_RRF_F0FF }, 613 { "mylr", 0x39, INSTR_RRF_F0FF }, 614 { "mayr", 0x3a, INSTR_RRF_F0FF }, 615 { "myr", 0x3b, INSTR_RRF_F0FF }, 616 { "mayhr", 0x3c, INSTR_RRF_F0FF }, 617 { "myhr", 0x3d, INSTR_RRF_F0FF }, 618 { "cegbr", 0xa4, INSTR_RRE_RR }, 619 { "cdgbr", 0xa5, INSTR_RRE_RR }, 620 { "cxgbr", 0xa6, INSTR_RRE_RR }, 621 { "cgebr", 0xa8, INSTR_RRF_U0RF }, 622 { "cgdbr", 0xa9, INSTR_RRF_U0RF }, 623 { "cgxbr", 0xaa, INSTR_RRF_U0RF }, 624 { "cfer", 0xb8, INSTR_RRF_U0RF }, 625 { "cfdr", 0xb9, INSTR_RRF_U0RF }, 626 { "cfxr", 0xba, INSTR_RRF_U0RF }, 627 { "cegr", 0xc4, INSTR_RRE_RR }, 628 { "cdgr", 0xc5, INSTR_RRE_RR }, 629 { "cxgr", 0xc6, INSTR_RRE_RR }, 630 { "cger", 0xc8, INSTR_RRF_U0RF }, 631 { "cgdr", 0xc9, INSTR_RRF_U0RF }, 632 { "cgxr", 0xca, INSTR_RRF_U0RF }, 633 #endif 634 { "lpebr", 0x00, INSTR_RRE_FF }, 635 { "lnebr", 0x01, INSTR_RRE_FF }, 636 { "ltebr", 0x02, INSTR_RRE_FF }, 637 { "lcebr", 0x03, INSTR_RRE_FF }, 638 { "ldebr", 0x04, INSTR_RRE_FF }, 639 { "lxdbr", 0x05, INSTR_RRE_FF }, 640 { "lxebr", 0x06, INSTR_RRE_FF }, 641 { "mxdbr", 0x07, INSTR_RRE_FF }, 642 { "kebr", 0x08, INSTR_RRE_FF }, 643 { "cebr", 0x09, INSTR_RRE_FF }, 644 { "aebr", 0x0a, INSTR_RRE_FF }, 645 { "sebr", 0x0b, INSTR_RRE_FF }, 646 { "mdebr", 0x0c, INSTR_RRE_FF }, 647 { "debr", 0x0d, INSTR_RRE_FF }, 648 { "maebr", 0x0e, INSTR_RRF_F0FF }, 649 { "msebr", 0x0f, INSTR_RRF_F0FF }, 650 { "lpdbr", 0x10, INSTR_RRE_FF }, 651 { "lndbr", 0x11, INSTR_RRE_FF }, 652 { "ltdbr", 0x12, INSTR_RRE_FF }, 653 { "lcdbr", 0x13, INSTR_RRE_FF }, 654 { "sqebr", 0x14, INSTR_RRE_FF }, 655 { "sqdbr", 0x15, INSTR_RRE_FF }, 656 { "sqxbr", 0x16, INSTR_RRE_FF }, 657 { "meebr", 0x17, INSTR_RRE_FF }, 658 { "kdbr", 0x18, INSTR_RRE_FF }, 659 { "cdbr", 0x19, INSTR_RRE_FF }, 660 { "adbr", 0x1a, INSTR_RRE_FF }, 661 { "sdbr", 0x1b, INSTR_RRE_FF }, 662 { "mdbr", 0x1c, INSTR_RRE_FF }, 663 { "ddbr", 0x1d, INSTR_RRE_FF }, 664 { "madbr", 0x1e, INSTR_RRF_F0FF }, 665 { "msdbr", 0x1f, INSTR_RRF_F0FF }, 666 { "lder", 0x24, INSTR_RRE_FF }, 667 { "lxdr", 0x25, INSTR_RRE_FF }, 668 { "lxer", 0x26, INSTR_RRE_FF }, 669 { "maer", 0x2e, INSTR_RRF_F0FF }, 670 { "mser", 0x2f, INSTR_RRF_F0FF }, 671 { "sqxr", 0x36, INSTR_RRE_FF }, 672 { "meer", 0x37, INSTR_RRE_FF }, 673 { "madr", 0x3e, INSTR_RRF_F0FF }, 674 { "msdr", 0x3f, INSTR_RRF_F0FF }, 675 { "lpxbr", 0x40, INSTR_RRE_FF }, 676 { "lnxbr", 0x41, INSTR_RRE_FF }, 677 { "ltxbr", 0x42, INSTR_RRE_FF }, 678 { "lcxbr", 0x43, INSTR_RRE_FF }, 679 { "ledbr", 0x44, INSTR_RRE_FF }, 680 { "ldxbr", 0x45, INSTR_RRE_FF }, 681 { "lexbr", 0x46, INSTR_RRE_FF }, 682 { "fixbr", 0x47, INSTR_RRF_U0FF }, 683 { "kxbr", 0x48, INSTR_RRE_FF }, 684 { "cxbr", 0x49, INSTR_RRE_FF }, 685 { "axbr", 0x4a, INSTR_RRE_FF }, 686 { "sxbr", 0x4b, INSTR_RRE_FF }, 687 { "mxbr", 0x4c, INSTR_RRE_FF }, 688 { "dxbr", 0x4d, INSTR_RRE_FF }, 689 { "tbedr", 0x50, INSTR_RRF_U0FF }, 690 { "tbdr", 0x51, INSTR_RRF_U0FF }, 691 { "diebr", 0x53, INSTR_RRF_FUFF }, 692 { "fiebr", 0x57, INSTR_RRF_U0FF }, 693 { "thder", 0x58, INSTR_RRE_RR }, 694 { "thdr", 0x59, INSTR_RRE_RR }, 695 { "didbr", 0x5b, INSTR_RRF_FUFF }, 696 { "fidbr", 0x5f, INSTR_RRF_U0FF }, 697 { "lpxr", 0x60, INSTR_RRE_FF }, 698 { "lnxr", 0x61, INSTR_RRE_FF }, 699 { "ltxr", 0x62, INSTR_RRE_FF }, 700 { "lcxr", 0x63, INSTR_RRE_FF }, 701 { "lxr", 0x65, INSTR_RRE_RR }, 702 { "lexr", 0x66, INSTR_RRE_FF }, 703 { "fixr", 0x67, INSTR_RRF_U0FF }, 704 { "cxr", 0x69, INSTR_RRE_FF }, 705 { "lzer", 0x74, INSTR_RRE_R0 }, 706 { "lzdr", 0x75, INSTR_RRE_R0 }, 707 { "lzxr", 0x76, INSTR_RRE_R0 }, 708 { "fier", 0x77, INSTR_RRF_U0FF }, 709 { "fidr", 0x7f, INSTR_RRF_U0FF }, 710 { "sfpc", 0x84, INSTR_RRE_RR_OPT }, 711 { "efpc", 0x8c, INSTR_RRE_RR_OPT }, 712 { "cefbr", 0x94, INSTR_RRE_RF }, 713 { "cdfbr", 0x95, INSTR_RRE_RF }, 714 { "cxfbr", 0x96, INSTR_RRE_RF }, 715 { "cfebr", 0x98, INSTR_RRF_U0RF }, 716 { "cfdbr", 0x99, INSTR_RRF_U0RF }, 717 { "cfxbr", 0x9a, INSTR_RRF_U0RF }, 718 { "cefr", 0xb4, INSTR_RRE_RF }, 719 { "cdfr", 0xb5, INSTR_RRE_RF }, 720 { "cxfr", 0xb6, INSTR_RRE_RF }, 721 { "", 0, INSTR_INVALID } 722 }; 723 724 static struct insn opcode_b9[] = { 725 #ifdef CONFIG_64BIT 726 { "lpgr", 0x00, INSTR_RRE_RR }, 727 { "lngr", 0x01, INSTR_RRE_RR }, 728 { "ltgr", 0x02, INSTR_RRE_RR }, 729 { "lcgr", 0x03, INSTR_RRE_RR }, 730 { "lgr", 0x04, INSTR_RRE_RR }, 731 { "lurag", 0x05, INSTR_RRE_RR }, 732 { "lgbr", 0x06, INSTR_RRE_RR }, 733 { "lghr", 0x07, INSTR_RRE_RR }, 734 { "agr", 0x08, INSTR_RRE_RR }, 735 { "sgr", 0x09, INSTR_RRE_RR }, 736 { "algr", 0x0a, INSTR_RRE_RR }, 737 { "slgr", 0x0b, INSTR_RRE_RR }, 738 { "msgr", 0x0c, INSTR_RRE_RR }, 739 { "dsgr", 0x0d, INSTR_RRE_RR }, 740 { "eregg", 0x0e, INSTR_RRE_RR }, 741 { "lrvgr", 0x0f, INSTR_RRE_RR }, 742 { "lpgfr", 0x10, INSTR_RRE_RR }, 743 { "lngfr", 0x11, INSTR_RRE_RR }, 744 { "ltgfr", 0x12, INSTR_RRE_RR }, 745 { "lcgfr", 0x13, INSTR_RRE_RR }, 746 { "lgfr", 0x14, INSTR_RRE_RR }, 747 { "llgfr", 0x16, INSTR_RRE_RR }, 748 { "llgtr", 0x17, INSTR_RRE_RR }, 749 { "agfr", 0x18, INSTR_RRE_RR }, 750 { "sgfr", 0x19, INSTR_RRE_RR }, 751 { "algfr", 0x1a, INSTR_RRE_RR }, 752 { "slgfr", 0x1b, INSTR_RRE_RR }, 753 { "msgfr", 0x1c, INSTR_RRE_RR }, 754 { "dsgfr", 0x1d, INSTR_RRE_RR }, 755 { "cgr", 0x20, INSTR_RRE_RR }, 756 { "clgr", 0x21, INSTR_RRE_RR }, 757 { "sturg", 0x25, INSTR_RRE_RR }, 758 { "lbr", 0x26, INSTR_RRE_RR }, 759 { "lhr", 0x27, INSTR_RRE_RR }, 760 { "cgfr", 0x30, INSTR_RRE_RR }, 761 { "clgfr", 0x31, INSTR_RRE_RR }, 762 { "bctgr", 0x46, INSTR_RRE_RR }, 763 { "ngr", 0x80, INSTR_RRE_RR }, 764 { "ogr", 0x81, INSTR_RRE_RR }, 765 { "xgr", 0x82, INSTR_RRE_RR }, 766 { "flogr", 0x83, INSTR_RRE_RR }, 767 { "llgcr", 0x84, INSTR_RRE_RR }, 768 { "llghr", 0x85, INSTR_RRE_RR }, 769 { "mlgr", 0x86, INSTR_RRE_RR }, 770 { "dlgr", 0x87, INSTR_RRE_RR }, 771 { "alcgr", 0x88, INSTR_RRE_RR }, 772 { "slbgr", 0x89, INSTR_RRE_RR }, 773 { "cspg", 0x8a, INSTR_RRE_RR }, 774 { "idte", 0x8e, INSTR_RRF_R0RR }, 775 { "llcr", 0x94, INSTR_RRE_RR }, 776 { "llhr", 0x95, INSTR_RRE_RR }, 777 { "esea", 0x9d, INSTR_RRE_R0 }, 778 { "lptea", 0xaa, INSTR_RRF_RURR }, 779 { "cu14", 0xb0, INSTR_RRF_M0RR }, 780 { "cu24", 0xb1, INSTR_RRF_M0RR }, 781 { "cu41", 0xb2, INSTR_RRF_M0RR }, 782 { "cu42", 0xb3, INSTR_RRF_M0RR }, 783 #endif 784 { "kmac", 0x1e, INSTR_RRE_RR }, 785 { "lrvr", 0x1f, INSTR_RRE_RR }, 786 { "km", 0x2e, INSTR_RRE_RR }, 787 { "kmc", 0x2f, INSTR_RRE_RR }, 788 { "kimd", 0x3e, INSTR_RRE_RR }, 789 { "klmd", 0x3f, INSTR_RRE_RR }, 790 { "epsw", 0x8d, INSTR_RRE_RR }, 791 { "trtt", 0x90, INSTR_RRE_RR }, 792 { "trtt", 0x90, INSTR_RRF_M0RR }, 793 { "trto", 0x91, INSTR_RRE_RR }, 794 { "trto", 0x91, INSTR_RRF_M0RR }, 795 { "trot", 0x92, INSTR_RRE_RR }, 796 { "trot", 0x92, INSTR_RRF_M0RR }, 797 { "troo", 0x93, INSTR_RRE_RR }, 798 { "troo", 0x93, INSTR_RRF_M0RR }, 799 { "mlr", 0x96, INSTR_RRE_RR }, 800 { "dlr", 0x97, INSTR_RRE_RR }, 801 { "alcr", 0x98, INSTR_RRE_RR }, 802 { "slbr", 0x99, INSTR_RRE_RR }, 803 { "", 0, INSTR_INVALID } 804 }; 805 806 static struct insn opcode_c0[] = { 807 #ifdef CONFIG_64BIT 808 { "lgfi", 0x01, INSTR_RIL_RI }, 809 { "xihf", 0x06, INSTR_RIL_RU }, 810 { "xilf", 0x07, INSTR_RIL_RU }, 811 { "iihf", 0x08, INSTR_RIL_RU }, 812 { "iilf", 0x09, INSTR_RIL_RU }, 813 { "nihf", 0x0a, INSTR_RIL_RU }, 814 { "nilf", 0x0b, INSTR_RIL_RU }, 815 { "oihf", 0x0c, INSTR_RIL_RU }, 816 { "oilf", 0x0d, INSTR_RIL_RU }, 817 { "llihf", 0x0e, INSTR_RIL_RU }, 818 { "llilf", 0x0f, INSTR_RIL_RU }, 819 #endif 820 { "larl", 0x00, INSTR_RIL_RP }, 821 { "brcl", 0x04, INSTR_RIL_UP }, 822 { "brasl", 0x05, INSTR_RIL_RP }, 823 { "", 0, INSTR_INVALID } 824 }; 825 826 static struct insn opcode_c2[] = { 827 #ifdef CONFIG_64BIT 828 { "slgfi", 0x04, INSTR_RIL_RU }, 829 { "slfi", 0x05, INSTR_RIL_RU }, 830 { "agfi", 0x08, INSTR_RIL_RI }, 831 { "afi", 0x09, INSTR_RIL_RI }, 832 { "algfi", 0x0a, INSTR_RIL_RU }, 833 { "alfi", 0x0b, INSTR_RIL_RU }, 834 { "cgfi", 0x0c, INSTR_RIL_RI }, 835 { "cfi", 0x0d, INSTR_RIL_RI }, 836 { "clgfi", 0x0e, INSTR_RIL_RU }, 837 { "clfi", 0x0f, INSTR_RIL_RU }, 838 #endif 839 { "", 0, INSTR_INVALID } 840 }; 841 842 static struct insn opcode_c8[] = { 843 #ifdef CONFIG_64BIT 844 { "mvcos", 0x00, INSTR_SSF_RRDRD }, 845 #endif 846 { "", 0, INSTR_INVALID } 847 }; 848 849 static struct insn opcode_e3[] = { 850 #ifdef CONFIG_64BIT 851 { "ltg", 0x02, INSTR_RXY_RRRD }, 852 { "lrag", 0x03, INSTR_RXY_RRRD }, 853 { "lg", 0x04, INSTR_RXY_RRRD }, 854 { "cvby", 0x06, INSTR_RXY_RRRD }, 855 { "ag", 0x08, INSTR_RXY_RRRD }, 856 { "sg", 0x09, INSTR_RXY_RRRD }, 857 { "alg", 0x0a, INSTR_RXY_RRRD }, 858 { "slg", 0x0b, INSTR_RXY_RRRD }, 859 { "msg", 0x0c, INSTR_RXY_RRRD }, 860 { "dsg", 0x0d, INSTR_RXY_RRRD }, 861 { "cvbg", 0x0e, INSTR_RXY_RRRD }, 862 { "lrvg", 0x0f, INSTR_RXY_RRRD }, 863 { "lt", 0x12, INSTR_RXY_RRRD }, 864 { "lray", 0x13, INSTR_RXY_RRRD }, 865 { "lgf", 0x14, INSTR_RXY_RRRD }, 866 { "lgh", 0x15, INSTR_RXY_RRRD }, 867 { "llgf", 0x16, INSTR_RXY_RRRD }, 868 { "llgt", 0x17, INSTR_RXY_RRRD }, 869 { "agf", 0x18, INSTR_RXY_RRRD }, 870 { "sgf", 0x19, INSTR_RXY_RRRD }, 871 { "algf", 0x1a, INSTR_RXY_RRRD }, 872 { "slgf", 0x1b, INSTR_RXY_RRRD }, 873 { "msgf", 0x1c, INSTR_RXY_RRRD }, 874 { "dsgf", 0x1d, INSTR_RXY_RRRD }, 875 { "cg", 0x20, INSTR_RXY_RRRD }, 876 { "clg", 0x21, INSTR_RXY_RRRD }, 877 { "stg", 0x24, INSTR_RXY_RRRD }, 878 { "cvdy", 0x26, INSTR_RXY_RRRD }, 879 { "cvdg", 0x2e, INSTR_RXY_RRRD }, 880 { "strvg", 0x2f, INSTR_RXY_RRRD }, 881 { "cgf", 0x30, INSTR_RXY_RRRD }, 882 { "clgf", 0x31, INSTR_RXY_RRRD }, 883 { "strvh", 0x3f, INSTR_RXY_RRRD }, 884 { "bctg", 0x46, INSTR_RXY_RRRD }, 885 { "sty", 0x50, INSTR_RXY_RRRD }, 886 { "msy", 0x51, INSTR_RXY_RRRD }, 887 { "ny", 0x54, INSTR_RXY_RRRD }, 888 { "cly", 0x55, INSTR_RXY_RRRD }, 889 { "oy", 0x56, INSTR_RXY_RRRD }, 890 { "xy", 0x57, INSTR_RXY_RRRD }, 891 { "ly", 0x58, INSTR_RXY_RRRD }, 892 { "cy", 0x59, INSTR_RXY_RRRD }, 893 { "ay", 0x5a, INSTR_RXY_RRRD }, 894 { "sy", 0x5b, INSTR_RXY_RRRD }, 895 { "aly", 0x5e, INSTR_RXY_RRRD }, 896 { "sly", 0x5f, INSTR_RXY_RRRD }, 897 { "sthy", 0x70, INSTR_RXY_RRRD }, 898 { "lay", 0x71, INSTR_RXY_RRRD }, 899 { "stcy", 0x72, INSTR_RXY_RRRD }, 900 { "icy", 0x73, INSTR_RXY_RRRD }, 901 { "lb", 0x76, INSTR_RXY_RRRD }, 902 { "lgb", 0x77, INSTR_RXY_RRRD }, 903 { "lhy", 0x78, INSTR_RXY_RRRD }, 904 { "chy", 0x79, INSTR_RXY_RRRD }, 905 { "ahy", 0x7a, INSTR_RXY_RRRD }, 906 { "shy", 0x7b, INSTR_RXY_RRRD }, 907 { "ng", 0x80, INSTR_RXY_RRRD }, 908 { "og", 0x81, INSTR_RXY_RRRD }, 909 { "xg", 0x82, INSTR_RXY_RRRD }, 910 { "mlg", 0x86, INSTR_RXY_RRRD }, 911 { "dlg", 0x87, INSTR_RXY_RRRD }, 912 { "alcg", 0x88, INSTR_RXY_RRRD }, 913 { "slbg", 0x89, INSTR_RXY_RRRD }, 914 { "stpq", 0x8e, INSTR_RXY_RRRD }, 915 { "lpq", 0x8f, INSTR_RXY_RRRD }, 916 { "llgc", 0x90, INSTR_RXY_RRRD }, 917 { "llgh", 0x91, INSTR_RXY_RRRD }, 918 { "llc", 0x94, INSTR_RXY_RRRD }, 919 { "llh", 0x95, INSTR_RXY_RRRD }, 920 #endif 921 { "lrv", 0x1e, INSTR_RXY_RRRD }, 922 { "lrvh", 0x1f, INSTR_RXY_RRRD }, 923 { "strv", 0x3e, INSTR_RXY_RRRD }, 924 { "ml", 0x96, INSTR_RXY_RRRD }, 925 { "dl", 0x97, INSTR_RXY_RRRD }, 926 { "alc", 0x98, INSTR_RXY_RRRD }, 927 { "slb", 0x99, INSTR_RXY_RRRD }, 928 { "", 0, INSTR_INVALID } 929 }; 930 931 static struct insn opcode_e5[] = { 932 #ifdef CONFIG_64BIT 933 { "strag", 0x02, INSTR_SSE_RDRD }, 934 #endif 935 { "lasp", 0x00, INSTR_SSE_RDRD }, 936 { "tprot", 0x01, INSTR_SSE_RDRD }, 937 { "mvcsk", 0x0e, INSTR_SSE_RDRD }, 938 { "mvcdk", 0x0f, INSTR_SSE_RDRD }, 939 { "", 0, INSTR_INVALID } 940 }; 941 942 static struct insn opcode_eb[] = { 943 #ifdef CONFIG_64BIT 944 { "lmg", 0x04, INSTR_RSY_RRRD }, 945 { "srag", 0x0a, INSTR_RSY_RRRD }, 946 { "slag", 0x0b, INSTR_RSY_RRRD }, 947 { "srlg", 0x0c, INSTR_RSY_RRRD }, 948 { "sllg", 0x0d, INSTR_RSY_RRRD }, 949 { "tracg", 0x0f, INSTR_RSY_RRRD }, 950 { "csy", 0x14, INSTR_RSY_RRRD }, 951 { "rllg", 0x1c, INSTR_RSY_RRRD }, 952 { "clmh", 0x20, INSTR_RSY_RURD }, 953 { "clmy", 0x21, INSTR_RSY_RURD }, 954 { "stmg", 0x24, INSTR_RSY_RRRD }, 955 { "stctg", 0x25, INSTR_RSY_CCRD }, 956 { "stmh", 0x26, INSTR_RSY_RRRD }, 957 { "stcmh", 0x2c, INSTR_RSY_RURD }, 958 { "stcmy", 0x2d, INSTR_RSY_RURD }, 959 { "lctlg", 0x2f, INSTR_RSY_CCRD }, 960 { "csg", 0x30, INSTR_RSY_RRRD }, 961 { "cdsy", 0x31, INSTR_RSY_RRRD }, 962 { "cdsg", 0x3e, INSTR_RSY_RRRD }, 963 { "bxhg", 0x44, INSTR_RSY_RRRD }, 964 { "bxleg", 0x45, INSTR_RSY_RRRD }, 965 { "tmy", 0x51, INSTR_SIY_URD }, 966 { "mviy", 0x52, INSTR_SIY_URD }, 967 { "niy", 0x54, INSTR_SIY_URD }, 968 { "cliy", 0x55, INSTR_SIY_URD }, 969 { "oiy", 0x56, INSTR_SIY_URD }, 970 { "xiy", 0x57, INSTR_SIY_URD }, 971 { "icmh", 0x80, INSTR_RSE_RURD }, 972 { "icmh", 0x80, INSTR_RSY_RURD }, 973 { "icmy", 0x81, INSTR_RSY_RURD }, 974 { "clclu", 0x8f, INSTR_RSY_RRRD }, 975 { "stmy", 0x90, INSTR_RSY_RRRD }, 976 { "lmh", 0x96, INSTR_RSY_RRRD }, 977 { "lmy", 0x98, INSTR_RSY_RRRD }, 978 { "lamy", 0x9a, INSTR_RSY_AARD }, 979 { "stamy", 0x9b, INSTR_RSY_AARD }, 980 #endif 981 { "rll", 0x1d, INSTR_RSY_RRRD }, 982 { "mvclu", 0x8e, INSTR_RSY_RRRD }, 983 { "tp", 0xc0, INSTR_RSL_R0RD }, 984 { "", 0, INSTR_INVALID } 985 }; 986 987 static struct insn opcode_ec[] = { 988 #ifdef CONFIG_64BIT 989 { "brxhg", 0x44, INSTR_RIE_RRP }, 990 { "brxlg", 0x45, INSTR_RIE_RRP }, 991 #endif 992 { "", 0, INSTR_INVALID } 993 }; 994 995 static struct insn opcode_ed[] = { 996 #ifdef CONFIG_64BIT 997 { "mayl", 0x38, INSTR_RXF_FRRDF }, 998 { "myl", 0x39, INSTR_RXF_FRRDF }, 999 { "may", 0x3a, INSTR_RXF_FRRDF }, 1000 { "my", 0x3b, INSTR_RXF_FRRDF }, 1001 { "mayh", 0x3c, INSTR_RXF_FRRDF }, 1002 { "myh", 0x3d, INSTR_RXF_FRRDF }, 1003 { "ley", 0x64, INSTR_RXY_FRRD }, 1004 { "ldy", 0x65, INSTR_RXY_FRRD }, 1005 { "stey", 0x66, INSTR_RXY_FRRD }, 1006 { "stdy", 0x67, INSTR_RXY_FRRD }, 1007 #endif 1008 { "ldeb", 0x04, INSTR_RXE_FRRD }, 1009 { "lxdb", 0x05, INSTR_RXE_FRRD }, 1010 { "lxeb", 0x06, INSTR_RXE_FRRD }, 1011 { "mxdb", 0x07, INSTR_RXE_FRRD }, 1012 { "keb", 0x08, INSTR_RXE_FRRD }, 1013 { "ceb", 0x09, INSTR_RXE_FRRD }, 1014 { "aeb", 0x0a, INSTR_RXE_FRRD }, 1015 { "seb", 0x0b, INSTR_RXE_FRRD }, 1016 { "mdeb", 0x0c, INSTR_RXE_FRRD }, 1017 { "deb", 0x0d, INSTR_RXE_FRRD }, 1018 { "maeb", 0x0e, INSTR_RXF_FRRDF }, 1019 { "mseb", 0x0f, INSTR_RXF_FRRDF }, 1020 { "tceb", 0x10, INSTR_RXE_FRRD }, 1021 { "tcdb", 0x11, INSTR_RXE_FRRD }, 1022 { "tcxb", 0x12, INSTR_RXE_FRRD }, 1023 { "sqeb", 0x14, INSTR_RXE_FRRD }, 1024 { "sqdb", 0x15, INSTR_RXE_FRRD }, 1025 { "meeb", 0x17, INSTR_RXE_FRRD }, 1026 { "kdb", 0x18, INSTR_RXE_FRRD }, 1027 { "cdb", 0x19, INSTR_RXE_FRRD }, 1028 { "adb", 0x1a, INSTR_RXE_FRRD }, 1029 { "sdb", 0x1b, INSTR_RXE_FRRD }, 1030 { "mdb", 0x1c, INSTR_RXE_FRRD }, 1031 { "ddb", 0x1d, INSTR_RXE_FRRD }, 1032 { "madb", 0x1e, INSTR_RXF_FRRDF }, 1033 { "msdb", 0x1f, INSTR_RXF_FRRDF }, 1034 { "lde", 0x24, INSTR_RXE_FRRD }, 1035 { "lxd", 0x25, INSTR_RXE_FRRD }, 1036 { "lxe", 0x26, INSTR_RXE_FRRD }, 1037 { "mae", 0x2e, INSTR_RXF_FRRDF }, 1038 { "mse", 0x2f, INSTR_RXF_FRRDF }, 1039 { "sqe", 0x34, INSTR_RXE_FRRD }, 1040 { "mee", 0x37, INSTR_RXE_FRRD }, 1041 { "mad", 0x3e, INSTR_RXF_FRRDF }, 1042 { "msd", 0x3f, INSTR_RXF_FRRDF }, 1043 { "", 0, INSTR_INVALID } 1044 }; 1045 1046 /* Extracts an operand value from an instruction. */ 1047 static unsigned int extract_operand(unsigned char *code, 1048 const struct operand *operand) 1049 { 1050 unsigned int val; 1051 int bits; 1052 1053 /* Extract fragments of the operand byte for byte. */ 1054 code += operand->shift / 8; 1055 bits = (operand->shift & 7) + operand->bits; 1056 val = 0; 1057 do { 1058 val <<= 8; 1059 val |= (unsigned int) *code++; 1060 bits -= 8; 1061 } while (bits > 0); 1062 val >>= -bits; 1063 val &= ((1U << (operand->bits - 1)) << 1) - 1; 1064 1065 /* Check for special long displacement case. */ 1066 if (operand->bits == 20 && operand->shift == 20) 1067 val = (val & 0xff) << 12 | (val & 0xfff00) >> 8; 1068 1069 /* Sign extend value if the operand is signed or pc relative. */ 1070 if ((operand->flags & (OPERAND_SIGNED | OPERAND_PCREL)) && 1071 (val & (1U << (operand->bits - 1)))) 1072 val |= (-1U << (operand->bits - 1)) << 1; 1073 1074 /* Double value if the operand is pc relative. */ 1075 if (operand->flags & OPERAND_PCREL) 1076 val <<= 1; 1077 1078 /* Length x in an instructions has real length x + 1. */ 1079 if (operand->flags & OPERAND_LENGTH) 1080 val++; 1081 return val; 1082 } 1083 1084 static inline int insn_length(unsigned char code) 1085 { 1086 return ((((int) code + 64) >> 7) + 1) << 1; 1087 } 1088 1089 static struct insn *find_insn(unsigned char *code) 1090 { 1091 unsigned char opfrag = code[1]; 1092 unsigned char opmask; 1093 struct insn *table; 1094 1095 switch (code[0]) { 1096 case 0x01: 1097 table = opcode_01; 1098 break; 1099 case 0xa5: 1100 table = opcode_a5; 1101 break; 1102 case 0xa7: 1103 table = opcode_a7; 1104 break; 1105 case 0xb2: 1106 table = opcode_b2; 1107 break; 1108 case 0xb3: 1109 table = opcode_b3; 1110 break; 1111 case 0xb9: 1112 table = opcode_b9; 1113 break; 1114 case 0xc0: 1115 table = opcode_c0; 1116 break; 1117 case 0xc2: 1118 table = opcode_c2; 1119 break; 1120 case 0xc8: 1121 table = opcode_c8; 1122 break; 1123 case 0xe3: 1124 table = opcode_e3; 1125 opfrag = code[5]; 1126 break; 1127 case 0xe5: 1128 table = opcode_e5; 1129 break; 1130 case 0xeb: 1131 table = opcode_eb; 1132 opfrag = code[5]; 1133 break; 1134 case 0xec: 1135 table = opcode_ec; 1136 opfrag = code[5]; 1137 break; 1138 case 0xed: 1139 table = opcode_ed; 1140 opfrag = code[5]; 1141 break; 1142 default: 1143 table = opcode; 1144 opfrag = code[0]; 1145 break; 1146 } 1147 while (table->format != INSTR_INVALID) { 1148 opmask = formats[table->format][0]; 1149 if (table->opfrag == (opfrag & opmask)) 1150 return table; 1151 table++; 1152 } 1153 return NULL; 1154 } 1155 1156 static int print_insn(char *buffer, unsigned char *code, unsigned long addr) 1157 { 1158 struct insn *insn; 1159 const unsigned char *ops; 1160 const struct operand *operand; 1161 unsigned int value; 1162 char separator; 1163 char *ptr; 1164 int i; 1165 1166 ptr = buffer; 1167 insn = find_insn(code); 1168 if (insn) { 1169 ptr += sprintf(ptr, "%.5s\t", insn->name); 1170 /* Extract the operands. */ 1171 separator = 0; 1172 for (ops = formats[insn->format] + 1, i = 0; 1173 *ops != 0 && i < 6; ops++, i++) { 1174 operand = operands + *ops; 1175 value = extract_operand(code, operand); 1176 if ((operand->flags & OPERAND_INDEX) && value == 0) 1177 continue; 1178 if ((operand->flags & OPERAND_BASE) && 1179 value == 0 && separator == '(') { 1180 separator = ','; 1181 continue; 1182 } 1183 if (separator) 1184 ptr += sprintf(ptr, "%c", separator); 1185 if (operand->flags & OPERAND_GPR) 1186 ptr += sprintf(ptr, "%%r%i", value); 1187 else if (operand->flags & OPERAND_FPR) 1188 ptr += sprintf(ptr, "%%f%i", value); 1189 else if (operand->flags & OPERAND_AR) 1190 ptr += sprintf(ptr, "%%a%i", value); 1191 else if (operand->flags & OPERAND_CR) 1192 ptr += sprintf(ptr, "%%c%i", value); 1193 else if (operand->flags & OPERAND_PCREL) 1194 ptr += sprintf(ptr, "%lx", (signed int) value 1195 + addr); 1196 else if (operand->flags & OPERAND_SIGNED) 1197 ptr += sprintf(ptr, "%i", value); 1198 else 1199 ptr += sprintf(ptr, "%u", value); 1200 if (operand->flags & OPERAND_DISP) 1201 separator = '('; 1202 else if (operand->flags & OPERAND_BASE) { 1203 ptr += sprintf(ptr, ")"); 1204 separator = ','; 1205 } else 1206 separator = ','; 1207 } 1208 } else 1209 ptr += sprintf(ptr, "unknown"); 1210 return (int) (ptr - buffer); 1211 } 1212 1213 void show_code(struct pt_regs *regs) 1214 { 1215 char *mode = (regs->psw.mask & PSW_MASK_PSTATE) ? "User" : "Krnl"; 1216 unsigned char code[64]; 1217 char buffer[64], *ptr; 1218 mm_segment_t old_fs; 1219 unsigned long addr; 1220 int start, end, opsize, hops, i; 1221 1222 /* Get a snapshot of the 64 bytes surrounding the fault address. */ 1223 old_fs = get_fs(); 1224 set_fs((regs->psw.mask & PSW_MASK_PSTATE) ? USER_DS : KERNEL_DS); 1225 for (start = 32; start && regs->psw.addr >= 34 - start; start -= 2) { 1226 addr = regs->psw.addr - 34 + start; 1227 if (__copy_from_user(code + start - 2, 1228 (char __user *) addr, 2)) 1229 break; 1230 } 1231 for (end = 32; end < 64; end += 2) { 1232 addr = regs->psw.addr + end - 32; 1233 if (__copy_from_user(code + end, 1234 (char __user *) addr, 2)) 1235 break; 1236 } 1237 set_fs(old_fs); 1238 /* Code snapshot useable ? */ 1239 if ((regs->psw.addr & 1) || start >= end) { 1240 printk("%s Code: Bad PSW.\n", mode); 1241 return; 1242 } 1243 /* Find a starting point for the disassembly. */ 1244 while (start < 32) { 1245 for (i = 0, hops = 0; start + i < 32 && hops < 3; hops++) { 1246 if (!find_insn(code + start + i)) 1247 break; 1248 i += insn_length(code[start + i]); 1249 } 1250 if (start + i == 32) 1251 /* Looks good, sequence ends at PSW. */ 1252 break; 1253 start += 2; 1254 } 1255 /* Decode the instructions. */ 1256 ptr = buffer; 1257 ptr += sprintf(ptr, "%s Code:", mode); 1258 hops = 0; 1259 while (start < end && hops < 8) { 1260 *ptr++ = (start == 32) ? '>' : ' '; 1261 addr = regs->psw.addr + start - 32; 1262 ptr += sprintf(ptr, ONELONG, addr); 1263 opsize = insn_length(code[start]); 1264 if (start + opsize >= end) 1265 break; 1266 for (i = 0; i < opsize; i++) 1267 ptr += sprintf(ptr, "%02x", code[start + i]); 1268 *ptr++ = '\t'; 1269 if (i < 6) 1270 *ptr++ = '\t'; 1271 ptr += print_insn(ptr, code + start, addr); 1272 start += opsize; 1273 printk(buffer); 1274 ptr = buffer; 1275 ptr += sprintf(ptr, "\n "); 1276 hops++; 1277 } 1278 printk("\n"); 1279 } 1280