1 /* 2 * Disassemble s390 instructions. 3 * 4 * Copyright IBM Corp. 2007 5 * Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com), 6 */ 7 8 #include <linux/sched.h> 9 #include <linux/kernel.h> 10 #include <linux/string.h> 11 #include <linux/errno.h> 12 #include <linux/ptrace.h> 13 #include <linux/timer.h> 14 #include <linux/mm.h> 15 #include <linux/smp.h> 16 #include <linux/init.h> 17 #include <linux/interrupt.h> 18 #include <linux/delay.h> 19 #include <linux/module.h> 20 #include <linux/kallsyms.h> 21 #include <linux/reboot.h> 22 #include <linux/kprobes.h> 23 #include <linux/kdebug.h> 24 25 #include <asm/uaccess.h> 26 #include <asm/dis.h> 27 #include <asm/io.h> 28 #include <linux/atomic.h> 29 #include <asm/mathemu.h> 30 #include <asm/cpcmd.h> 31 #include <asm/lowcore.h> 32 #include <asm/debug.h> 33 #include <asm/irq.h> 34 35 enum { 36 UNUSED, /* Indicates the end of the operand list */ 37 R_8, /* GPR starting at position 8 */ 38 R_12, /* GPR starting at position 12 */ 39 R_16, /* GPR starting at position 16 */ 40 R_20, /* GPR starting at position 20 */ 41 R_24, /* GPR starting at position 24 */ 42 R_28, /* GPR starting at position 28 */ 43 R_32, /* GPR starting at position 32 */ 44 F_8, /* FPR starting at position 8 */ 45 F_12, /* FPR starting at position 12 */ 46 F_16, /* FPR starting at position 16 */ 47 F_20, /* FPR starting at position 16 */ 48 F_24, /* FPR starting at position 24 */ 49 F_28, /* FPR starting at position 28 */ 50 F_32, /* FPR starting at position 32 */ 51 A_8, /* Access reg. starting at position 8 */ 52 A_12, /* Access reg. starting at position 12 */ 53 A_24, /* Access reg. starting at position 24 */ 54 A_28, /* Access reg. starting at position 28 */ 55 C_8, /* Control reg. starting at position 8 */ 56 C_12, /* Control reg. starting at position 12 */ 57 V_8, /* Vector reg. starting at position 8, extension bit at 36 */ 58 V_12, /* Vector reg. starting at position 12, extension bit at 37 */ 59 V_16, /* Vector reg. starting at position 16, extension bit at 38 */ 60 V_32, /* Vector reg. starting at position 32, extension bit at 39 */ 61 W_12, /* Vector reg. at bit 12, extension at bit 37, used as index */ 62 B_16, /* Base register starting at position 16 */ 63 B_32, /* Base register starting at position 32 */ 64 X_12, /* Index register starting at position 12 */ 65 D_20, /* Displacement starting at position 20 */ 66 D_36, /* Displacement starting at position 36 */ 67 D20_20, /* 20 bit displacement starting at 20 */ 68 L4_8, /* 4 bit length starting at position 8 */ 69 L4_12, /* 4 bit length starting at position 12 */ 70 L8_8, /* 8 bit length starting at position 8 */ 71 U4_8, /* 4 bit unsigned value starting at 8 */ 72 U4_12, /* 4 bit unsigned value starting at 12 */ 73 U4_16, /* 4 bit unsigned value starting at 16 */ 74 U4_20, /* 4 bit unsigned value starting at 20 */ 75 U4_24, /* 4 bit unsigned value starting at 24 */ 76 U4_28, /* 4 bit unsigned value starting at 28 */ 77 U4_32, /* 4 bit unsigned value starting at 32 */ 78 U4_36, /* 4 bit unsigned value starting at 36 */ 79 U8_8, /* 8 bit unsigned value starting at 8 */ 80 U8_16, /* 8 bit unsigned value starting at 16 */ 81 U8_24, /* 8 bit unsigned value starting at 24 */ 82 U8_32, /* 8 bit unsigned value starting at 32 */ 83 I8_8, /* 8 bit signed value starting at 8 */ 84 I8_16, /* 8 bit signed value starting at 16 */ 85 I8_24, /* 8 bit signed value starting at 24 */ 86 I8_32, /* 8 bit signed value starting at 32 */ 87 J12_12, /* PC relative offset at 12 */ 88 I16_16, /* 16 bit signed value starting at 16 */ 89 I16_32, /* 32 bit signed value starting at 16 */ 90 U16_16, /* 16 bit unsigned value starting at 16 */ 91 U16_32, /* 32 bit unsigned value starting at 16 */ 92 J16_16, /* PC relative jump offset at 16 */ 93 J16_32, /* PC relative offset at 16 */ 94 I24_24, /* 24 bit signed value starting at 24 */ 95 J32_16, /* PC relative long offset at 16 */ 96 I32_16, /* 32 bit signed value starting at 16 */ 97 U32_16, /* 32 bit unsigned value starting at 16 */ 98 M_16, /* 4 bit optional mask starting at 16 */ 99 M_20, /* 4 bit optional mask starting at 20 */ 100 M_24, /* 4 bit optional mask starting at 24 */ 101 M_28, /* 4 bit optional mask starting at 28 */ 102 M_32, /* 4 bit optional mask starting at 32 */ 103 RO_28, /* optional GPR starting at position 28 */ 104 }; 105 106 /* 107 * Enumeration of the different instruction formats. 108 * For details consult the principles of operation. 109 */ 110 enum { 111 INSTR_INVALID, 112 INSTR_E, 113 INSTR_IE_UU, 114 INSTR_MII_UPI, 115 INSTR_RIE_R0IU, INSTR_RIE_R0UU, INSTR_RIE_RRP, INSTR_RIE_RRPU, 116 INSTR_RIE_RRUUU, INSTR_RIE_RUPI, INSTR_RIE_RUPU, INSTR_RIE_RRI0, 117 INSTR_RIL_RI, INSTR_RIL_RP, INSTR_RIL_RU, INSTR_RIL_UP, 118 INSTR_RIS_R0RDU, INSTR_RIS_R0UU, INSTR_RIS_RURDI, INSTR_RIS_RURDU, 119 INSTR_RI_RI, INSTR_RI_RP, INSTR_RI_RU, INSTR_RI_UP, 120 INSTR_RRE_00, INSTR_RRE_0R, INSTR_RRE_AA, INSTR_RRE_AR, INSTR_RRE_F0, 121 INSTR_RRE_FF, INSTR_RRE_FR, INSTR_RRE_R0, INSTR_RRE_RA, INSTR_RRE_RF, 122 INSTR_RRE_RR, INSTR_RRE_RR_OPT, 123 INSTR_RRF_0UFF, INSTR_RRF_F0FF, INSTR_RRF_F0FF2, INSTR_RRF_F0FR, 124 INSTR_RRF_FFRU, INSTR_RRF_FUFF, INSTR_RRF_FUFF2, INSTR_RRF_M0RR, 125 INSTR_RRF_R0RR, INSTR_RRF_R0RR2, INSTR_RRF_RMRR, INSTR_RRF_RURR, 126 INSTR_RRF_U0FF, INSTR_RRF_U0RF, INSTR_RRF_U0RR, INSTR_RRF_UUFF, 127 INSTR_RRF_UUFR, INSTR_RRF_UURF, 128 INSTR_RRR_F0FF, INSTR_RRS_RRRDU, 129 INSTR_RR_FF, INSTR_RR_R0, INSTR_RR_RR, INSTR_RR_U0, INSTR_RR_UR, 130 INSTR_RSE_CCRD, INSTR_RSE_RRRD, INSTR_RSE_RURD, 131 INSTR_RSI_RRP, 132 INSTR_RSL_LRDFU, INSTR_RSL_R0RD, 133 INSTR_RSY_AARD, INSTR_RSY_CCRD, INSTR_RSY_RRRD, INSTR_RSY_RURD, 134 INSTR_RSY_RDRM, INSTR_RSY_RMRD, 135 INSTR_RS_AARD, INSTR_RS_CCRD, INSTR_RS_R0RD, INSTR_RS_RRRD, 136 INSTR_RS_RURD, 137 INSTR_RXE_FRRD, INSTR_RXE_RRRD, INSTR_RXE_RRRDM, 138 INSTR_RXF_FRRDF, 139 INSTR_RXY_FRRD, INSTR_RXY_RRRD, INSTR_RXY_URRD, 140 INSTR_RX_FRRD, INSTR_RX_RRRD, INSTR_RX_URRD, 141 INSTR_SIL_RDI, INSTR_SIL_RDU, 142 INSTR_SIY_IRD, INSTR_SIY_URD, 143 INSTR_SI_URD, 144 INSTR_SMI_U0RDP, 145 INSTR_SSE_RDRD, 146 INSTR_SSF_RRDRD, INSTR_SSF_RRDRD2, 147 INSTR_SS_L0RDRD, INSTR_SS_LIRDRD, INSTR_SS_LLRDRD, INSTR_SS_RRRDRD, 148 INSTR_SS_RRRDRD2, INSTR_SS_RRRDRD3, 149 INSTR_S_00, INSTR_S_RD, 150 INSTR_VRI_V0IM, INSTR_VRI_V0I0, INSTR_VRI_V0IIM, INSTR_VRI_VVIM, 151 INSTR_VRI_VVV0IM, INSTR_VRI_VVV0I0, INSTR_VRI_VVIMM, 152 INSTR_VRR_VV00MMM, INSTR_VRR_VV000MM, INSTR_VRR_VV0000M, 153 INSTR_VRR_VV00000, INSTR_VRR_VVV0M0M, INSTR_VRR_VV00M0M, 154 INSTR_VRR_VVV000M, INSTR_VRR_VVV000V, INSTR_VRR_VVV0000, 155 INSTR_VRR_VVV0MMM, INSTR_VRR_VVV00MM, INSTR_VRR_VVVMM0V, 156 INSTR_VRR_VVVM0MV, INSTR_VRR_VVVM00V, INSTR_VRR_VRR0000, 157 INSTR_VRS_VVRDM, INSTR_VRS_VVRD0, INSTR_VRS_VRRDM, INSTR_VRS_VRRD0, 158 INSTR_VRS_RVRDM, 159 INSTR_VRV_VVRDM, INSTR_VRV_VWRDM, 160 INSTR_VRX_VRRDM, INSTR_VRX_VRRD0, 161 }; 162 163 static const struct s390_operand operands[] = 164 { 165 [UNUSED] = { 0, 0, 0 }, 166 [R_8] = { 4, 8, OPERAND_GPR }, 167 [R_12] = { 4, 12, OPERAND_GPR }, 168 [R_16] = { 4, 16, OPERAND_GPR }, 169 [R_20] = { 4, 20, OPERAND_GPR }, 170 [R_24] = { 4, 24, OPERAND_GPR }, 171 [R_28] = { 4, 28, OPERAND_GPR }, 172 [R_32] = { 4, 32, OPERAND_GPR }, 173 [F_8] = { 4, 8, OPERAND_FPR }, 174 [F_12] = { 4, 12, OPERAND_FPR }, 175 [F_16] = { 4, 16, OPERAND_FPR }, 176 [F_20] = { 4, 16, OPERAND_FPR }, 177 [F_24] = { 4, 24, OPERAND_FPR }, 178 [F_28] = { 4, 28, OPERAND_FPR }, 179 [F_32] = { 4, 32, OPERAND_FPR }, 180 [A_8] = { 4, 8, OPERAND_AR }, 181 [A_12] = { 4, 12, OPERAND_AR }, 182 [A_24] = { 4, 24, OPERAND_AR }, 183 [A_28] = { 4, 28, OPERAND_AR }, 184 [C_8] = { 4, 8, OPERAND_CR }, 185 [C_12] = { 4, 12, OPERAND_CR }, 186 [V_8] = { 4, 8, OPERAND_VR }, 187 [V_12] = { 4, 12, OPERAND_VR }, 188 [V_16] = { 4, 16, OPERAND_VR }, 189 [V_32] = { 4, 32, OPERAND_VR }, 190 [W_12] = { 4, 12, OPERAND_INDEX | OPERAND_VR }, 191 [B_16] = { 4, 16, OPERAND_BASE | OPERAND_GPR }, 192 [B_32] = { 4, 32, OPERAND_BASE | OPERAND_GPR }, 193 [X_12] = { 4, 12, OPERAND_INDEX | OPERAND_GPR }, 194 [D_20] = { 12, 20, OPERAND_DISP }, 195 [D_36] = { 12, 36, OPERAND_DISP }, 196 [D20_20] = { 20, 20, OPERAND_DISP | OPERAND_SIGNED }, 197 [L4_8] = { 4, 8, OPERAND_LENGTH }, 198 [L4_12] = { 4, 12, OPERAND_LENGTH }, 199 [L8_8] = { 8, 8, OPERAND_LENGTH }, 200 [U4_8] = { 4, 8, 0 }, 201 [U4_12] = { 4, 12, 0 }, 202 [U4_16] = { 4, 16, 0 }, 203 [U4_20] = { 4, 20, 0 }, 204 [U4_24] = { 4, 24, 0 }, 205 [U4_28] = { 4, 28, 0 }, 206 [U4_32] = { 4, 32, 0 }, 207 [U4_36] = { 4, 36, 0 }, 208 [U8_8] = { 8, 8, 0 }, 209 [U8_16] = { 8, 16, 0 }, 210 [U8_24] = { 8, 24, 0 }, 211 [U8_32] = { 8, 32, 0 }, 212 [J12_12] = { 12, 12, OPERAND_PCREL }, 213 [I8_8] = { 8, 8, OPERAND_SIGNED }, 214 [I8_16] = { 8, 16, OPERAND_SIGNED }, 215 [I8_24] = { 8, 24, OPERAND_SIGNED }, 216 [I8_32] = { 8, 32, OPERAND_SIGNED }, 217 [I16_32] = { 16, 32, OPERAND_SIGNED }, 218 [I16_16] = { 16, 16, OPERAND_SIGNED }, 219 [U16_16] = { 16, 16, 0 }, 220 [U16_32] = { 16, 32, 0 }, 221 [J16_16] = { 16, 16, OPERAND_PCREL }, 222 [J16_32] = { 16, 32, OPERAND_PCREL }, 223 [I24_24] = { 24, 24, OPERAND_SIGNED }, 224 [J32_16] = { 32, 16, OPERAND_PCREL }, 225 [I32_16] = { 32, 16, OPERAND_SIGNED }, 226 [U32_16] = { 32, 16, 0 }, 227 [M_16] = { 4, 16, 0 }, 228 [M_20] = { 4, 20, 0 }, 229 [M_24] = { 4, 24, 0 }, 230 [M_28] = { 4, 28, 0 }, 231 [M_32] = { 4, 32, 0 }, 232 [RO_28] = { 4, 28, OPERAND_GPR } 233 }; 234 235 static const unsigned char formats[][7] = { 236 [INSTR_E] = { 0xff, 0,0,0,0,0,0 }, 237 [INSTR_IE_UU] = { 0xff, U4_24,U4_28,0,0,0,0 }, 238 [INSTR_MII_UPI] = { 0xff, U4_8,J12_12,I24_24 }, 239 [INSTR_RIE_R0IU] = { 0xff, R_8,I16_16,U4_32,0,0,0 }, 240 [INSTR_RIE_R0UU] = { 0xff, R_8,U16_16,U4_32,0,0,0 }, 241 [INSTR_RIE_RRI0] = { 0xff, R_8,R_12,I16_16,0,0,0 }, 242 [INSTR_RIE_RRPU] = { 0xff, R_8,R_12,U4_32,J16_16,0,0 }, 243 [INSTR_RIE_RRP] = { 0xff, R_8,R_12,J16_16,0,0,0 }, 244 [INSTR_RIE_RRUUU] = { 0xff, R_8,R_12,U8_16,U8_24,U8_32,0 }, 245 [INSTR_RIE_RUPI] = { 0xff, R_8,I8_32,U4_12,J16_16,0,0 }, 246 [INSTR_RIE_RUPU] = { 0xff, R_8,U8_32,U4_12,J16_16,0,0 }, 247 [INSTR_RIL_RI] = { 0x0f, R_8,I32_16,0,0,0,0 }, 248 [INSTR_RIL_RP] = { 0x0f, R_8,J32_16,0,0,0,0 }, 249 [INSTR_RIL_RU] = { 0x0f, R_8,U32_16,0,0,0,0 }, 250 [INSTR_RIL_UP] = { 0x0f, U4_8,J32_16,0,0,0,0 }, 251 [INSTR_RIS_R0RDU] = { 0xff, R_8,U8_32,D_20,B_16,0,0 }, 252 [INSTR_RIS_RURDI] = { 0xff, R_8,I8_32,U4_12,D_20,B_16,0 }, 253 [INSTR_RIS_RURDU] = { 0xff, R_8,U8_32,U4_12,D_20,B_16,0 }, 254 [INSTR_RI_RI] = { 0x0f, R_8,I16_16,0,0,0,0 }, 255 [INSTR_RI_RP] = { 0x0f, R_8,J16_16,0,0,0,0 }, 256 [INSTR_RI_RU] = { 0x0f, R_8,U16_16,0,0,0,0 }, 257 [INSTR_RI_UP] = { 0x0f, U4_8,J16_16,0,0,0,0 }, 258 [INSTR_RRE_00] = { 0xff, 0,0,0,0,0,0 }, 259 [INSTR_RRE_0R] = { 0xff, R_28,0,0,0,0,0 }, 260 [INSTR_RRE_AA] = { 0xff, A_24,A_28,0,0,0,0 }, 261 [INSTR_RRE_AR] = { 0xff, A_24,R_28,0,0,0,0 }, 262 [INSTR_RRE_F0] = { 0xff, F_24,0,0,0,0,0 }, 263 [INSTR_RRE_FF] = { 0xff, F_24,F_28,0,0,0,0 }, 264 [INSTR_RRE_FR] = { 0xff, F_24,R_28,0,0,0,0 }, 265 [INSTR_RRE_R0] = { 0xff, R_24,0,0,0,0,0 }, 266 [INSTR_RRE_RA] = { 0xff, R_24,A_28,0,0,0,0 }, 267 [INSTR_RRE_RF] = { 0xff, R_24,F_28,0,0,0,0 }, 268 [INSTR_RRE_RR] = { 0xff, R_24,R_28,0,0,0,0 }, 269 [INSTR_RRE_RR_OPT]= { 0xff, R_24,RO_28,0,0,0,0 }, 270 [INSTR_RRF_0UFF] = { 0xff, F_24,F_28,U4_20,0,0,0 }, 271 [INSTR_RRF_F0FF2] = { 0xff, F_24,F_16,F_28,0,0,0 }, 272 [INSTR_RRF_F0FF] = { 0xff, F_16,F_24,F_28,0,0,0 }, 273 [INSTR_RRF_F0FR] = { 0xff, F_24,F_16,R_28,0,0,0 }, 274 [INSTR_RRF_FFRU] = { 0xff, F_24,F_16,R_28,U4_20,0,0 }, 275 [INSTR_RRF_FUFF] = { 0xff, F_24,F_16,F_28,U4_20,0,0 }, 276 [INSTR_RRF_FUFF2] = { 0xff, F_24,F_28,F_16,U4_20,0,0 }, 277 [INSTR_RRF_M0RR] = { 0xff, R_24,R_28,M_16,0,0,0 }, 278 [INSTR_RRF_R0RR] = { 0xff, R_24,R_16,R_28,0,0,0 }, 279 [INSTR_RRF_R0RR2] = { 0xff, R_24,R_28,R_16,0,0,0 }, 280 [INSTR_RRF_RMRR] = { 0xff, R_24,R_16,R_28,M_20,0,0 }, 281 [INSTR_RRF_RURR] = { 0xff, R_24,R_28,R_16,U4_20,0,0 }, 282 [INSTR_RRF_U0FF] = { 0xff, F_24,U4_16,F_28,0,0,0 }, 283 [INSTR_RRF_U0RF] = { 0xff, R_24,U4_16,F_28,0,0,0 }, 284 [INSTR_RRF_U0RR] = { 0xff, R_24,R_28,U4_16,0,0,0 }, 285 [INSTR_RRF_UUFF] = { 0xff, F_24,U4_16,F_28,U4_20,0,0 }, 286 [INSTR_RRF_UUFR] = { 0xff, F_24,U4_16,R_28,U4_20,0,0 }, 287 [INSTR_RRF_UURF] = { 0xff, R_24,U4_16,F_28,U4_20,0,0 }, 288 [INSTR_RRR_F0FF] = { 0xff, F_24,F_28,F_16,0,0,0 }, 289 [INSTR_RRS_RRRDU] = { 0xff, R_8,R_12,U4_32,D_20,B_16,0 }, 290 [INSTR_RR_FF] = { 0xff, F_8,F_12,0,0,0,0 }, 291 [INSTR_RR_R0] = { 0xff, R_8, 0,0,0,0,0 }, 292 [INSTR_RR_RR] = { 0xff, R_8,R_12,0,0,0,0 }, 293 [INSTR_RR_U0] = { 0xff, U8_8, 0,0,0,0,0 }, 294 [INSTR_RR_UR] = { 0xff, U4_8,R_12,0,0,0,0 }, 295 [INSTR_RSE_CCRD] = { 0xff, C_8,C_12,D_20,B_16,0,0 }, 296 [INSTR_RSE_RRRD] = { 0xff, R_8,R_12,D_20,B_16,0,0 }, 297 [INSTR_RSE_RURD] = { 0xff, R_8,U4_12,D_20,B_16,0,0 }, 298 [INSTR_RSI_RRP] = { 0xff, R_8,R_12,J16_16,0,0,0 }, 299 [INSTR_RSL_LRDFU] = { 0xff, F_32,D_20,L4_8,B_16,U4_36,0 }, 300 [INSTR_RSL_R0RD] = { 0xff, D_20,L4_8,B_16,0,0,0 }, 301 [INSTR_RSY_AARD] = { 0xff, A_8,A_12,D20_20,B_16,0,0 }, 302 [INSTR_RSY_CCRD] = { 0xff, C_8,C_12,D20_20,B_16,0,0 }, 303 [INSTR_RSY_RDRM] = { 0xff, R_8,D20_20,B_16,U4_12,0,0 }, 304 [INSTR_RSY_RMRD] = { 0xff, R_8,U4_12,D20_20,B_16,0,0 }, 305 [INSTR_RSY_RRRD] = { 0xff, R_8,R_12,D20_20,B_16,0,0 }, 306 [INSTR_RSY_RURD] = { 0xff, R_8,U4_12,D20_20,B_16,0,0 }, 307 [INSTR_RS_AARD] = { 0xff, A_8,A_12,D_20,B_16,0,0 }, 308 [INSTR_RS_CCRD] = { 0xff, C_8,C_12,D_20,B_16,0,0 }, 309 [INSTR_RS_R0RD] = { 0xff, R_8,D_20,B_16,0,0,0 }, 310 [INSTR_RS_RRRD] = { 0xff, R_8,R_12,D_20,B_16,0,0 }, 311 [INSTR_RS_RURD] = { 0xff, R_8,U4_12,D_20,B_16,0,0 }, 312 [INSTR_RXE_FRRD] = { 0xff, F_8,D_20,X_12,B_16,0,0 }, 313 [INSTR_RXE_RRRD] = { 0xff, R_8,D_20,X_12,B_16,0,0 }, 314 [INSTR_RXE_RRRDM] = { 0xff, R_8,D_20,X_12,B_16,M_32,0 }, 315 [INSTR_RXF_FRRDF] = { 0xff, F_32,F_8,D_20,X_12,B_16,0 }, 316 [INSTR_RXY_FRRD] = { 0xff, F_8,D20_20,X_12,B_16,0,0 }, 317 [INSTR_RXY_RRRD] = { 0xff, R_8,D20_20,X_12,B_16,0,0 }, 318 [INSTR_RXY_URRD] = { 0xff, U4_8,D20_20,X_12,B_16,0,0 }, 319 [INSTR_RX_FRRD] = { 0xff, F_8,D_20,X_12,B_16,0,0 }, 320 [INSTR_RX_RRRD] = { 0xff, R_8,D_20,X_12,B_16,0,0 }, 321 [INSTR_RX_URRD] = { 0xff, U4_8,D_20,X_12,B_16,0,0 }, 322 [INSTR_SIL_RDI] = { 0xff, D_20,B_16,I16_32,0,0,0 }, 323 [INSTR_SIL_RDU] = { 0xff, D_20,B_16,U16_32,0,0,0 }, 324 [INSTR_SIY_IRD] = { 0xff, D20_20,B_16,I8_8,0,0,0 }, 325 [INSTR_SIY_URD] = { 0xff, D20_20,B_16,U8_8,0,0,0 }, 326 [INSTR_SI_URD] = { 0xff, D_20,B_16,U8_8,0,0,0 }, 327 [INSTR_SMI_U0RDP] = { 0xff, U4_8,J16_32,D_20,B_16,0,0 }, 328 [INSTR_SSE_RDRD] = { 0xff, D_20,B_16,D_36,B_32,0,0 }, 329 [INSTR_SSF_RRDRD] = { 0x0f, D_20,B_16,D_36,B_32,R_8,0 }, 330 [INSTR_SSF_RRDRD2]= { 0x0f, R_8,D_20,B_16,D_36,B_32,0 }, 331 [INSTR_SS_L0RDRD] = { 0xff, D_20,L8_8,B_16,D_36,B_32,0 }, 332 [INSTR_SS_LIRDRD] = { 0xff, D_20,L4_8,B_16,D_36,B_32,U4_12 }, 333 [INSTR_SS_LLRDRD] = { 0xff, D_20,L4_8,B_16,D_36,L4_12,B_32 }, 334 [INSTR_SS_RRRDRD2]= { 0xff, R_8,D_20,B_16,R_12,D_36,B_32 }, 335 [INSTR_SS_RRRDRD3]= { 0xff, R_8,R_12,D_20,B_16,D_36,B_32 }, 336 [INSTR_SS_RRRDRD] = { 0xff, D_20,R_8,B_16,D_36,B_32,R_12 }, 337 [INSTR_S_00] = { 0xff, 0,0,0,0,0,0 }, 338 [INSTR_S_RD] = { 0xff, D_20,B_16,0,0,0,0 }, 339 [INSTR_VRI_V0IM] = { 0xff, V_8,I16_16,M_32,0,0,0 }, 340 [INSTR_VRI_V0I0] = { 0xff, V_8,I16_16,0,0,0,0 }, 341 [INSTR_VRI_V0IIM] = { 0xff, V_8,I8_16,I8_24,M_32,0,0 }, 342 [INSTR_VRI_VVIM] = { 0xff, V_8,I16_16,V_12,M_32,0,0 }, 343 [INSTR_VRI_VVV0IM]= { 0xff, V_8,V_12,V_16,I8_24,M_32,0 }, 344 [INSTR_VRI_VVV0I0]= { 0xff, V_8,V_12,V_16,I8_24,0,0 }, 345 [INSTR_VRI_VVIMM] = { 0xff, V_8,V_12,I16_16,M_32,M_28,0 }, 346 [INSTR_VRR_VV00MMM]={ 0xff, V_8,V_12,M_32,M_28,M_24,0 }, 347 [INSTR_VRR_VV000MM]={ 0xff, V_8,V_12,M_32,M_28,0,0 }, 348 [INSTR_VRR_VV0000M]={ 0xff, V_8,V_12,M_32,0,0,0 }, 349 [INSTR_VRR_VV00000]={ 0xff, V_8,V_12,0,0,0,0 }, 350 [INSTR_VRR_VVV0M0M]={ 0xff, V_8,V_12,V_16,M_32,M_24,0 }, 351 [INSTR_VRR_VV00M0M]={ 0xff, V_8,V_12,M_32,M_24,0,0 }, 352 [INSTR_VRR_VVV000M]={ 0xff, V_8,V_12,V_16,M_32,0,0 }, 353 [INSTR_VRR_VVV000V]={ 0xff, V_8,V_12,V_16,V_32,0,0 }, 354 [INSTR_VRR_VVV0000]={ 0xff, V_8,V_12,V_16,0,0,0 }, 355 [INSTR_VRR_VVV0MMM]={ 0xff, V_8,V_12,V_16,M_32,M_28,M_24 }, 356 [INSTR_VRR_VVV00MM]={ 0xff, V_8,V_12,V_16,M_32,M_28,0 }, 357 [INSTR_VRR_VVVMM0V]={ 0xff, V_8,V_12,V_16,V_32,M_20,M_24 }, 358 [INSTR_VRR_VVVM0MV]={ 0xff, V_8,V_12,V_16,V_32,M_28,M_20 }, 359 [INSTR_VRR_VVVM00V]={ 0xff, V_8,V_12,V_16,V_32,M_20,0 }, 360 [INSTR_VRR_VRR0000]={ 0xff, V_8,R_12,R_16,0,0,0 }, 361 [INSTR_VRS_VVRDM] = { 0xff, V_8,V_12,D_20,B_16,M_32,0 }, 362 [INSTR_VRS_VVRD0] = { 0xff, V_8,V_12,D_20,B_16,0,0 }, 363 [INSTR_VRS_VRRDM] = { 0xff, V_8,R_12,D_20,B_16,M_32,0 }, 364 [INSTR_VRS_VRRD0] = { 0xff, V_8,R_12,D_20,B_16,0,0 }, 365 [INSTR_VRS_RVRDM] = { 0xff, R_8,V_12,D_20,B_16,M_32,0 }, 366 [INSTR_VRV_VVRDM] = { 0xff, V_8,V_12,D_20,B_16,M_32,0 }, 367 [INSTR_VRV_VWRDM] = { 0xff, V_8,D_20,W_12,B_16,M_32,0 }, 368 [INSTR_VRX_VRRDM] = { 0xff, V_8,D_20,X_12,B_16,M_32,0 }, 369 [INSTR_VRX_VRRD0] = { 0xff, V_8,D_20,X_12,B_16,0,0 }, 370 }; 371 372 enum { 373 LONG_INSN_ALGHSIK, 374 LONG_INSN_ALHHHR, 375 LONG_INSN_ALHHLR, 376 LONG_INSN_ALHSIK, 377 LONG_INSN_ALSIHN, 378 LONG_INSN_CDFBRA, 379 LONG_INSN_CDGBRA, 380 LONG_INSN_CDGTRA, 381 LONG_INSN_CDLFBR, 382 LONG_INSN_CDLFTR, 383 LONG_INSN_CDLGBR, 384 LONG_INSN_CDLGTR, 385 LONG_INSN_CEFBRA, 386 LONG_INSN_CEGBRA, 387 LONG_INSN_CELFBR, 388 LONG_INSN_CELGBR, 389 LONG_INSN_CFDBRA, 390 LONG_INSN_CFEBRA, 391 LONG_INSN_CFXBRA, 392 LONG_INSN_CGDBRA, 393 LONG_INSN_CGDTRA, 394 LONG_INSN_CGEBRA, 395 LONG_INSN_CGXBRA, 396 LONG_INSN_CGXTRA, 397 LONG_INSN_CLFDBR, 398 LONG_INSN_CLFDTR, 399 LONG_INSN_CLFEBR, 400 LONG_INSN_CLFHSI, 401 LONG_INSN_CLFXBR, 402 LONG_INSN_CLFXTR, 403 LONG_INSN_CLGDBR, 404 LONG_INSN_CLGDTR, 405 LONG_INSN_CLGEBR, 406 LONG_INSN_CLGFRL, 407 LONG_INSN_CLGHRL, 408 LONG_INSN_CLGHSI, 409 LONG_INSN_CLGXBR, 410 LONG_INSN_CLGXTR, 411 LONG_INSN_CLHHSI, 412 LONG_INSN_CXFBRA, 413 LONG_INSN_CXGBRA, 414 LONG_INSN_CXGTRA, 415 LONG_INSN_CXLFBR, 416 LONG_INSN_CXLFTR, 417 LONG_INSN_CXLGBR, 418 LONG_INSN_CXLGTR, 419 LONG_INSN_FIDBRA, 420 LONG_INSN_FIEBRA, 421 LONG_INSN_FIXBRA, 422 LONG_INSN_LDXBRA, 423 LONG_INSN_LEDBRA, 424 LONG_INSN_LEXBRA, 425 LONG_INSN_LLGFAT, 426 LONG_INSN_LLGFRL, 427 LONG_INSN_LLGHRL, 428 LONG_INSN_LLGTAT, 429 LONG_INSN_POPCNT, 430 LONG_INSN_RIEMIT, 431 LONG_INSN_RINEXT, 432 LONG_INSN_RISBGN, 433 LONG_INSN_RISBHG, 434 LONG_INSN_RISBLG, 435 LONG_INSN_SLHHHR, 436 LONG_INSN_SLHHLR, 437 LONG_INSN_TABORT, 438 LONG_INSN_TBEGIN, 439 LONG_INSN_TBEGINC, 440 LONG_INSN_PCISTG, 441 LONG_INSN_MPCIFC, 442 LONG_INSN_STPCIFC, 443 LONG_INSN_PCISTB, 444 LONG_INSN_VPOPCT, 445 LONG_INSN_VERLLV, 446 LONG_INSN_VESRAV, 447 LONG_INSN_VESRLV, 448 LONG_INSN_VSBCBI, 449 LONG_INSN_STCCTM 450 }; 451 452 static char *long_insn_name[] = { 453 [LONG_INSN_ALGHSIK] = "alghsik", 454 [LONG_INSN_ALHHHR] = "alhhhr", 455 [LONG_INSN_ALHHLR] = "alhhlr", 456 [LONG_INSN_ALHSIK] = "alhsik", 457 [LONG_INSN_ALSIHN] = "alsihn", 458 [LONG_INSN_CDFBRA] = "cdfbra", 459 [LONG_INSN_CDGBRA] = "cdgbra", 460 [LONG_INSN_CDGTRA] = "cdgtra", 461 [LONG_INSN_CDLFBR] = "cdlfbr", 462 [LONG_INSN_CDLFTR] = "cdlftr", 463 [LONG_INSN_CDLGBR] = "cdlgbr", 464 [LONG_INSN_CDLGTR] = "cdlgtr", 465 [LONG_INSN_CEFBRA] = "cefbra", 466 [LONG_INSN_CEGBRA] = "cegbra", 467 [LONG_INSN_CELFBR] = "celfbr", 468 [LONG_INSN_CELGBR] = "celgbr", 469 [LONG_INSN_CFDBRA] = "cfdbra", 470 [LONG_INSN_CFEBRA] = "cfebra", 471 [LONG_INSN_CFXBRA] = "cfxbra", 472 [LONG_INSN_CGDBRA] = "cgdbra", 473 [LONG_INSN_CGDTRA] = "cgdtra", 474 [LONG_INSN_CGEBRA] = "cgebra", 475 [LONG_INSN_CGXBRA] = "cgxbra", 476 [LONG_INSN_CGXTRA] = "cgxtra", 477 [LONG_INSN_CLFDBR] = "clfdbr", 478 [LONG_INSN_CLFDTR] = "clfdtr", 479 [LONG_INSN_CLFEBR] = "clfebr", 480 [LONG_INSN_CLFHSI] = "clfhsi", 481 [LONG_INSN_CLFXBR] = "clfxbr", 482 [LONG_INSN_CLFXTR] = "clfxtr", 483 [LONG_INSN_CLGDBR] = "clgdbr", 484 [LONG_INSN_CLGDTR] = "clgdtr", 485 [LONG_INSN_CLGEBR] = "clgebr", 486 [LONG_INSN_CLGFRL] = "clgfrl", 487 [LONG_INSN_CLGHRL] = "clghrl", 488 [LONG_INSN_CLGHSI] = "clghsi", 489 [LONG_INSN_CLGXBR] = "clgxbr", 490 [LONG_INSN_CLGXTR] = "clgxtr", 491 [LONG_INSN_CLHHSI] = "clhhsi", 492 [LONG_INSN_CXFBRA] = "cxfbra", 493 [LONG_INSN_CXGBRA] = "cxgbra", 494 [LONG_INSN_CXGTRA] = "cxgtra", 495 [LONG_INSN_CXLFBR] = "cxlfbr", 496 [LONG_INSN_CXLFTR] = "cxlftr", 497 [LONG_INSN_CXLGBR] = "cxlgbr", 498 [LONG_INSN_CXLGTR] = "cxlgtr", 499 [LONG_INSN_FIDBRA] = "fidbra", 500 [LONG_INSN_FIEBRA] = "fiebra", 501 [LONG_INSN_FIXBRA] = "fixbra", 502 [LONG_INSN_LDXBRA] = "ldxbra", 503 [LONG_INSN_LEDBRA] = "ledbra", 504 [LONG_INSN_LEXBRA] = "lexbra", 505 [LONG_INSN_LLGFAT] = "llgfat", 506 [LONG_INSN_LLGFRL] = "llgfrl", 507 [LONG_INSN_LLGHRL] = "llghrl", 508 [LONG_INSN_LLGTAT] = "llgtat", 509 [LONG_INSN_POPCNT] = "popcnt", 510 [LONG_INSN_RIEMIT] = "riemit", 511 [LONG_INSN_RINEXT] = "rinext", 512 [LONG_INSN_RISBGN] = "risbgn", 513 [LONG_INSN_RISBHG] = "risbhg", 514 [LONG_INSN_RISBLG] = "risblg", 515 [LONG_INSN_SLHHHR] = "slhhhr", 516 [LONG_INSN_SLHHLR] = "slhhlr", 517 [LONG_INSN_TABORT] = "tabort", 518 [LONG_INSN_TBEGIN] = "tbegin", 519 [LONG_INSN_TBEGINC] = "tbeginc", 520 [LONG_INSN_PCISTG] = "pcistg", 521 [LONG_INSN_MPCIFC] = "mpcifc", 522 [LONG_INSN_STPCIFC] = "stpcifc", 523 [LONG_INSN_PCISTB] = "pcistb", 524 [LONG_INSN_VPOPCT] = "vpopct", 525 [LONG_INSN_VERLLV] = "verllv", 526 [LONG_INSN_VESRAV] = "vesrav", 527 [LONG_INSN_VESRLV] = "vesrlv", 528 [LONG_INSN_VSBCBI] = "vsbcbi", 529 [LONG_INSN_STCCTM] = "stcctm", 530 }; 531 532 static struct s390_insn opcode[] = { 533 { "bprp", 0xc5, INSTR_MII_UPI }, 534 { "bpp", 0xc7, INSTR_SMI_U0RDP }, 535 { "trtr", 0xd0, INSTR_SS_L0RDRD }, 536 { "lmd", 0xef, INSTR_SS_RRRDRD3 }, 537 { "spm", 0x04, INSTR_RR_R0 }, 538 { "balr", 0x05, INSTR_RR_RR }, 539 { "bctr", 0x06, INSTR_RR_RR }, 540 { "bcr", 0x07, INSTR_RR_UR }, 541 { "svc", 0x0a, INSTR_RR_U0 }, 542 { "bsm", 0x0b, INSTR_RR_RR }, 543 { "bassm", 0x0c, INSTR_RR_RR }, 544 { "basr", 0x0d, INSTR_RR_RR }, 545 { "mvcl", 0x0e, INSTR_RR_RR }, 546 { "clcl", 0x0f, INSTR_RR_RR }, 547 { "lpr", 0x10, INSTR_RR_RR }, 548 { "lnr", 0x11, INSTR_RR_RR }, 549 { "ltr", 0x12, INSTR_RR_RR }, 550 { "lcr", 0x13, INSTR_RR_RR }, 551 { "nr", 0x14, INSTR_RR_RR }, 552 { "clr", 0x15, INSTR_RR_RR }, 553 { "or", 0x16, INSTR_RR_RR }, 554 { "xr", 0x17, INSTR_RR_RR }, 555 { "lr", 0x18, INSTR_RR_RR }, 556 { "cr", 0x19, INSTR_RR_RR }, 557 { "ar", 0x1a, INSTR_RR_RR }, 558 { "sr", 0x1b, INSTR_RR_RR }, 559 { "mr", 0x1c, INSTR_RR_RR }, 560 { "dr", 0x1d, INSTR_RR_RR }, 561 { "alr", 0x1e, INSTR_RR_RR }, 562 { "slr", 0x1f, INSTR_RR_RR }, 563 { "lpdr", 0x20, INSTR_RR_FF }, 564 { "lndr", 0x21, INSTR_RR_FF }, 565 { "ltdr", 0x22, INSTR_RR_FF }, 566 { "lcdr", 0x23, INSTR_RR_FF }, 567 { "hdr", 0x24, INSTR_RR_FF }, 568 { "ldxr", 0x25, INSTR_RR_FF }, 569 { "mxr", 0x26, INSTR_RR_FF }, 570 { "mxdr", 0x27, INSTR_RR_FF }, 571 { "ldr", 0x28, INSTR_RR_FF }, 572 { "cdr", 0x29, INSTR_RR_FF }, 573 { "adr", 0x2a, INSTR_RR_FF }, 574 { "sdr", 0x2b, INSTR_RR_FF }, 575 { "mdr", 0x2c, INSTR_RR_FF }, 576 { "ddr", 0x2d, INSTR_RR_FF }, 577 { "awr", 0x2e, INSTR_RR_FF }, 578 { "swr", 0x2f, INSTR_RR_FF }, 579 { "lper", 0x30, INSTR_RR_FF }, 580 { "lner", 0x31, INSTR_RR_FF }, 581 { "lter", 0x32, INSTR_RR_FF }, 582 { "lcer", 0x33, INSTR_RR_FF }, 583 { "her", 0x34, INSTR_RR_FF }, 584 { "ledr", 0x35, INSTR_RR_FF }, 585 { "axr", 0x36, INSTR_RR_FF }, 586 { "sxr", 0x37, INSTR_RR_FF }, 587 { "ler", 0x38, INSTR_RR_FF }, 588 { "cer", 0x39, INSTR_RR_FF }, 589 { "aer", 0x3a, INSTR_RR_FF }, 590 { "ser", 0x3b, INSTR_RR_FF }, 591 { "mder", 0x3c, INSTR_RR_FF }, 592 { "der", 0x3d, INSTR_RR_FF }, 593 { "aur", 0x3e, INSTR_RR_FF }, 594 { "sur", 0x3f, INSTR_RR_FF }, 595 { "sth", 0x40, INSTR_RX_RRRD }, 596 { "la", 0x41, INSTR_RX_RRRD }, 597 { "stc", 0x42, INSTR_RX_RRRD }, 598 { "ic", 0x43, INSTR_RX_RRRD }, 599 { "ex", 0x44, INSTR_RX_RRRD }, 600 { "bal", 0x45, INSTR_RX_RRRD }, 601 { "bct", 0x46, INSTR_RX_RRRD }, 602 { "bc", 0x47, INSTR_RX_URRD }, 603 { "lh", 0x48, INSTR_RX_RRRD }, 604 { "ch", 0x49, INSTR_RX_RRRD }, 605 { "ah", 0x4a, INSTR_RX_RRRD }, 606 { "sh", 0x4b, INSTR_RX_RRRD }, 607 { "mh", 0x4c, INSTR_RX_RRRD }, 608 { "bas", 0x4d, INSTR_RX_RRRD }, 609 { "cvd", 0x4e, INSTR_RX_RRRD }, 610 { "cvb", 0x4f, INSTR_RX_RRRD }, 611 { "st", 0x50, INSTR_RX_RRRD }, 612 { "lae", 0x51, INSTR_RX_RRRD }, 613 { "n", 0x54, INSTR_RX_RRRD }, 614 { "cl", 0x55, INSTR_RX_RRRD }, 615 { "o", 0x56, INSTR_RX_RRRD }, 616 { "x", 0x57, INSTR_RX_RRRD }, 617 { "l", 0x58, INSTR_RX_RRRD }, 618 { "c", 0x59, INSTR_RX_RRRD }, 619 { "a", 0x5a, INSTR_RX_RRRD }, 620 { "s", 0x5b, INSTR_RX_RRRD }, 621 { "m", 0x5c, INSTR_RX_RRRD }, 622 { "d", 0x5d, INSTR_RX_RRRD }, 623 { "al", 0x5e, INSTR_RX_RRRD }, 624 { "sl", 0x5f, INSTR_RX_RRRD }, 625 { "std", 0x60, INSTR_RX_FRRD }, 626 { "mxd", 0x67, INSTR_RX_FRRD }, 627 { "ld", 0x68, INSTR_RX_FRRD }, 628 { "cd", 0x69, INSTR_RX_FRRD }, 629 { "ad", 0x6a, INSTR_RX_FRRD }, 630 { "sd", 0x6b, INSTR_RX_FRRD }, 631 { "md", 0x6c, INSTR_RX_FRRD }, 632 { "dd", 0x6d, INSTR_RX_FRRD }, 633 { "aw", 0x6e, INSTR_RX_FRRD }, 634 { "sw", 0x6f, INSTR_RX_FRRD }, 635 { "ste", 0x70, INSTR_RX_FRRD }, 636 { "ms", 0x71, INSTR_RX_RRRD }, 637 { "le", 0x78, INSTR_RX_FRRD }, 638 { "ce", 0x79, INSTR_RX_FRRD }, 639 { "ae", 0x7a, INSTR_RX_FRRD }, 640 { "se", 0x7b, INSTR_RX_FRRD }, 641 { "mde", 0x7c, INSTR_RX_FRRD }, 642 { "de", 0x7d, INSTR_RX_FRRD }, 643 { "au", 0x7e, INSTR_RX_FRRD }, 644 { "su", 0x7f, INSTR_RX_FRRD }, 645 { "ssm", 0x80, INSTR_S_RD }, 646 { "lpsw", 0x82, INSTR_S_RD }, 647 { "diag", 0x83, INSTR_RS_RRRD }, 648 { "brxh", 0x84, INSTR_RSI_RRP }, 649 { "brxle", 0x85, INSTR_RSI_RRP }, 650 { "bxh", 0x86, INSTR_RS_RRRD }, 651 { "bxle", 0x87, INSTR_RS_RRRD }, 652 { "srl", 0x88, INSTR_RS_R0RD }, 653 { "sll", 0x89, INSTR_RS_R0RD }, 654 { "sra", 0x8a, INSTR_RS_R0RD }, 655 { "sla", 0x8b, INSTR_RS_R0RD }, 656 { "srdl", 0x8c, INSTR_RS_R0RD }, 657 { "sldl", 0x8d, INSTR_RS_R0RD }, 658 { "srda", 0x8e, INSTR_RS_R0RD }, 659 { "slda", 0x8f, INSTR_RS_R0RD }, 660 { "stm", 0x90, INSTR_RS_RRRD }, 661 { "tm", 0x91, INSTR_SI_URD }, 662 { "mvi", 0x92, INSTR_SI_URD }, 663 { "ts", 0x93, INSTR_S_RD }, 664 { "ni", 0x94, INSTR_SI_URD }, 665 { "cli", 0x95, INSTR_SI_URD }, 666 { "oi", 0x96, INSTR_SI_URD }, 667 { "xi", 0x97, INSTR_SI_URD }, 668 { "lm", 0x98, INSTR_RS_RRRD }, 669 { "trace", 0x99, INSTR_RS_RRRD }, 670 { "lam", 0x9a, INSTR_RS_AARD }, 671 { "stam", 0x9b, INSTR_RS_AARD }, 672 { "mvcle", 0xa8, INSTR_RS_RRRD }, 673 { "clcle", 0xa9, INSTR_RS_RRRD }, 674 { "stnsm", 0xac, INSTR_SI_URD }, 675 { "stosm", 0xad, INSTR_SI_URD }, 676 { "sigp", 0xae, INSTR_RS_RRRD }, 677 { "mc", 0xaf, INSTR_SI_URD }, 678 { "lra", 0xb1, INSTR_RX_RRRD }, 679 { "stctl", 0xb6, INSTR_RS_CCRD }, 680 { "lctl", 0xb7, INSTR_RS_CCRD }, 681 { "cs", 0xba, INSTR_RS_RRRD }, 682 { "cds", 0xbb, INSTR_RS_RRRD }, 683 { "clm", 0xbd, INSTR_RS_RURD }, 684 { "stcm", 0xbe, INSTR_RS_RURD }, 685 { "icm", 0xbf, INSTR_RS_RURD }, 686 { "mvn", 0xd1, INSTR_SS_L0RDRD }, 687 { "mvc", 0xd2, INSTR_SS_L0RDRD }, 688 { "mvz", 0xd3, INSTR_SS_L0RDRD }, 689 { "nc", 0xd4, INSTR_SS_L0RDRD }, 690 { "clc", 0xd5, INSTR_SS_L0RDRD }, 691 { "oc", 0xd6, INSTR_SS_L0RDRD }, 692 { "xc", 0xd7, INSTR_SS_L0RDRD }, 693 { "mvck", 0xd9, INSTR_SS_RRRDRD }, 694 { "mvcp", 0xda, INSTR_SS_RRRDRD }, 695 { "mvcs", 0xdb, INSTR_SS_RRRDRD }, 696 { "tr", 0xdc, INSTR_SS_L0RDRD }, 697 { "trt", 0xdd, INSTR_SS_L0RDRD }, 698 { "ed", 0xde, INSTR_SS_L0RDRD }, 699 { "edmk", 0xdf, INSTR_SS_L0RDRD }, 700 { "pku", 0xe1, INSTR_SS_L0RDRD }, 701 { "unpku", 0xe2, INSTR_SS_L0RDRD }, 702 { "mvcin", 0xe8, INSTR_SS_L0RDRD }, 703 { "pka", 0xe9, INSTR_SS_L0RDRD }, 704 { "unpka", 0xea, INSTR_SS_L0RDRD }, 705 { "plo", 0xee, INSTR_SS_RRRDRD2 }, 706 { "srp", 0xf0, INSTR_SS_LIRDRD }, 707 { "mvo", 0xf1, INSTR_SS_LLRDRD }, 708 { "pack", 0xf2, INSTR_SS_LLRDRD }, 709 { "unpk", 0xf3, INSTR_SS_LLRDRD }, 710 { "zap", 0xf8, INSTR_SS_LLRDRD }, 711 { "cp", 0xf9, INSTR_SS_LLRDRD }, 712 { "ap", 0xfa, INSTR_SS_LLRDRD }, 713 { "sp", 0xfb, INSTR_SS_LLRDRD }, 714 { "mp", 0xfc, INSTR_SS_LLRDRD }, 715 { "dp", 0xfd, INSTR_SS_LLRDRD }, 716 { "", 0, INSTR_INVALID } 717 }; 718 719 static struct s390_insn opcode_01[] = { 720 { "ptff", 0x04, INSTR_E }, 721 { "pfpo", 0x0a, INSTR_E }, 722 { "sam64", 0x0e, INSTR_E }, 723 { "pr", 0x01, INSTR_E }, 724 { "upt", 0x02, INSTR_E }, 725 { "sckpf", 0x07, INSTR_E }, 726 { "tam", 0x0b, INSTR_E }, 727 { "sam24", 0x0c, INSTR_E }, 728 { "sam31", 0x0d, INSTR_E }, 729 { "trap2", 0xff, INSTR_E }, 730 { "", 0, INSTR_INVALID } 731 }; 732 733 static struct s390_insn opcode_a5[] = { 734 { "iihh", 0x00, INSTR_RI_RU }, 735 { "iihl", 0x01, INSTR_RI_RU }, 736 { "iilh", 0x02, INSTR_RI_RU }, 737 { "iill", 0x03, INSTR_RI_RU }, 738 { "nihh", 0x04, INSTR_RI_RU }, 739 { "nihl", 0x05, INSTR_RI_RU }, 740 { "nilh", 0x06, INSTR_RI_RU }, 741 { "nill", 0x07, INSTR_RI_RU }, 742 { "oihh", 0x08, INSTR_RI_RU }, 743 { "oihl", 0x09, INSTR_RI_RU }, 744 { "oilh", 0x0a, INSTR_RI_RU }, 745 { "oill", 0x0b, INSTR_RI_RU }, 746 { "llihh", 0x0c, INSTR_RI_RU }, 747 { "llihl", 0x0d, INSTR_RI_RU }, 748 { "llilh", 0x0e, INSTR_RI_RU }, 749 { "llill", 0x0f, INSTR_RI_RU }, 750 { "", 0, INSTR_INVALID } 751 }; 752 753 static struct s390_insn opcode_a7[] = { 754 { "tmhh", 0x02, INSTR_RI_RU }, 755 { "tmhl", 0x03, INSTR_RI_RU }, 756 { "brctg", 0x07, INSTR_RI_RP }, 757 { "lghi", 0x09, INSTR_RI_RI }, 758 { "aghi", 0x0b, INSTR_RI_RI }, 759 { "mghi", 0x0d, INSTR_RI_RI }, 760 { "cghi", 0x0f, INSTR_RI_RI }, 761 { "tmlh", 0x00, INSTR_RI_RU }, 762 { "tmll", 0x01, INSTR_RI_RU }, 763 { "brc", 0x04, INSTR_RI_UP }, 764 { "bras", 0x05, INSTR_RI_RP }, 765 { "brct", 0x06, INSTR_RI_RP }, 766 { "lhi", 0x08, INSTR_RI_RI }, 767 { "ahi", 0x0a, INSTR_RI_RI }, 768 { "mhi", 0x0c, INSTR_RI_RI }, 769 { "chi", 0x0e, INSTR_RI_RI }, 770 { "", 0, INSTR_INVALID } 771 }; 772 773 static struct s390_insn opcode_aa[] = { 774 { { 0, LONG_INSN_RINEXT }, 0x00, INSTR_RI_RI }, 775 { "rion", 0x01, INSTR_RI_RI }, 776 { "tric", 0x02, INSTR_RI_RI }, 777 { "rioff", 0x03, INSTR_RI_RI }, 778 { { 0, LONG_INSN_RIEMIT }, 0x04, INSTR_RI_RI }, 779 { "", 0, INSTR_INVALID } 780 }; 781 782 static struct s390_insn opcode_b2[] = { 783 { "stckf", 0x7c, INSTR_S_RD }, 784 { "lpp", 0x80, INSTR_S_RD }, 785 { "lcctl", 0x84, INSTR_S_RD }, 786 { "lpctl", 0x85, INSTR_S_RD }, 787 { "qsi", 0x86, INSTR_S_RD }, 788 { "lsctl", 0x87, INSTR_S_RD }, 789 { "qctri", 0x8e, INSTR_S_RD }, 790 { "stfle", 0xb0, INSTR_S_RD }, 791 { "lpswe", 0xb2, INSTR_S_RD }, 792 { "srnmb", 0xb8, INSTR_S_RD }, 793 { "srnmt", 0xb9, INSTR_S_RD }, 794 { "lfas", 0xbd, INSTR_S_RD }, 795 { "scctr", 0xe0, INSTR_RRE_RR }, 796 { "spctr", 0xe1, INSTR_RRE_RR }, 797 { "ecctr", 0xe4, INSTR_RRE_RR }, 798 { "epctr", 0xe5, INSTR_RRE_RR }, 799 { "ppa", 0xe8, INSTR_RRF_U0RR }, 800 { "etnd", 0xec, INSTR_RRE_R0 }, 801 { "ecpga", 0xed, INSTR_RRE_RR }, 802 { "tend", 0xf8, INSTR_S_00 }, 803 { "niai", 0xfa, INSTR_IE_UU }, 804 { { 0, LONG_INSN_TABORT }, 0xfc, INSTR_S_RD }, 805 { "stidp", 0x02, INSTR_S_RD }, 806 { "sck", 0x04, INSTR_S_RD }, 807 { "stck", 0x05, INSTR_S_RD }, 808 { "sckc", 0x06, INSTR_S_RD }, 809 { "stckc", 0x07, INSTR_S_RD }, 810 { "spt", 0x08, INSTR_S_RD }, 811 { "stpt", 0x09, INSTR_S_RD }, 812 { "spka", 0x0a, INSTR_S_RD }, 813 { "ipk", 0x0b, INSTR_S_00 }, 814 { "ptlb", 0x0d, INSTR_S_00 }, 815 { "spx", 0x10, INSTR_S_RD }, 816 { "stpx", 0x11, INSTR_S_RD }, 817 { "stap", 0x12, INSTR_S_RD }, 818 { "sie", 0x14, INSTR_S_RD }, 819 { "pc", 0x18, INSTR_S_RD }, 820 { "sac", 0x19, INSTR_S_RD }, 821 { "cfc", 0x1a, INSTR_S_RD }, 822 { "servc", 0x20, INSTR_RRE_RR }, 823 { "ipte", 0x21, INSTR_RRE_RR }, 824 { "ipm", 0x22, INSTR_RRE_R0 }, 825 { "ivsk", 0x23, INSTR_RRE_RR }, 826 { "iac", 0x24, INSTR_RRE_R0 }, 827 { "ssar", 0x25, INSTR_RRE_R0 }, 828 { "epar", 0x26, INSTR_RRE_R0 }, 829 { "esar", 0x27, INSTR_RRE_R0 }, 830 { "pt", 0x28, INSTR_RRE_RR }, 831 { "iske", 0x29, INSTR_RRE_RR }, 832 { "rrbe", 0x2a, INSTR_RRE_RR }, 833 { "sske", 0x2b, INSTR_RRF_M0RR }, 834 { "tb", 0x2c, INSTR_RRE_0R }, 835 { "dxr", 0x2d, INSTR_RRE_FF }, 836 { "pgin", 0x2e, INSTR_RRE_RR }, 837 { "pgout", 0x2f, INSTR_RRE_RR }, 838 { "csch", 0x30, INSTR_S_00 }, 839 { "hsch", 0x31, INSTR_S_00 }, 840 { "msch", 0x32, INSTR_S_RD }, 841 { "ssch", 0x33, INSTR_S_RD }, 842 { "stsch", 0x34, INSTR_S_RD }, 843 { "tsch", 0x35, INSTR_S_RD }, 844 { "tpi", 0x36, INSTR_S_RD }, 845 { "sal", 0x37, INSTR_S_00 }, 846 { "rsch", 0x38, INSTR_S_00 }, 847 { "stcrw", 0x39, INSTR_S_RD }, 848 { "stcps", 0x3a, INSTR_S_RD }, 849 { "rchp", 0x3b, INSTR_S_00 }, 850 { "schm", 0x3c, INSTR_S_00 }, 851 { "bakr", 0x40, INSTR_RRE_RR }, 852 { "cksm", 0x41, INSTR_RRE_RR }, 853 { "sqdr", 0x44, INSTR_RRE_FF }, 854 { "sqer", 0x45, INSTR_RRE_FF }, 855 { "stura", 0x46, INSTR_RRE_RR }, 856 { "msta", 0x47, INSTR_RRE_R0 }, 857 { "palb", 0x48, INSTR_RRE_00 }, 858 { "ereg", 0x49, INSTR_RRE_RR }, 859 { "esta", 0x4a, INSTR_RRE_RR }, 860 { "lura", 0x4b, INSTR_RRE_RR }, 861 { "tar", 0x4c, INSTR_RRE_AR }, 862 { "cpya", 0x4d, INSTR_RRE_AA }, 863 { "sar", 0x4e, INSTR_RRE_AR }, 864 { "ear", 0x4f, INSTR_RRE_RA }, 865 { "csp", 0x50, INSTR_RRE_RR }, 866 { "msr", 0x52, INSTR_RRE_RR }, 867 { "mvpg", 0x54, INSTR_RRE_RR }, 868 { "mvst", 0x55, INSTR_RRE_RR }, 869 { "cuse", 0x57, INSTR_RRE_RR }, 870 { "bsg", 0x58, INSTR_RRE_RR }, 871 { "bsa", 0x5a, INSTR_RRE_RR }, 872 { "clst", 0x5d, INSTR_RRE_RR }, 873 { "srst", 0x5e, INSTR_RRE_RR }, 874 { "cmpsc", 0x63, INSTR_RRE_RR }, 875 { "siga", 0x74, INSTR_S_RD }, 876 { "xsch", 0x76, INSTR_S_00 }, 877 { "rp", 0x77, INSTR_S_RD }, 878 { "stcke", 0x78, INSTR_S_RD }, 879 { "sacf", 0x79, INSTR_S_RD }, 880 { "stsi", 0x7d, INSTR_S_RD }, 881 { "srnm", 0x99, INSTR_S_RD }, 882 { "stfpc", 0x9c, INSTR_S_RD }, 883 { "lfpc", 0x9d, INSTR_S_RD }, 884 { "tre", 0xa5, INSTR_RRE_RR }, 885 { "cuutf", 0xa6, INSTR_RRF_M0RR }, 886 { "cutfu", 0xa7, INSTR_RRF_M0RR }, 887 { "stfl", 0xb1, INSTR_S_RD }, 888 { "trap4", 0xff, INSTR_S_RD }, 889 { "", 0, INSTR_INVALID } 890 }; 891 892 static struct s390_insn opcode_b3[] = { 893 { "maylr", 0x38, INSTR_RRF_F0FF }, 894 { "mylr", 0x39, INSTR_RRF_F0FF }, 895 { "mayr", 0x3a, INSTR_RRF_F0FF }, 896 { "myr", 0x3b, INSTR_RRF_F0FF }, 897 { "mayhr", 0x3c, INSTR_RRF_F0FF }, 898 { "myhr", 0x3d, INSTR_RRF_F0FF }, 899 { "lpdfr", 0x70, INSTR_RRE_FF }, 900 { "lndfr", 0x71, INSTR_RRE_FF }, 901 { "cpsdr", 0x72, INSTR_RRF_F0FF2 }, 902 { "lcdfr", 0x73, INSTR_RRE_FF }, 903 { "sfasr", 0x85, INSTR_RRE_R0 }, 904 { { 0, LONG_INSN_CELFBR }, 0x90, INSTR_RRF_UUFR }, 905 { { 0, LONG_INSN_CDLFBR }, 0x91, INSTR_RRF_UUFR }, 906 { { 0, LONG_INSN_CXLFBR }, 0x92, INSTR_RRF_UURF }, 907 { { 0, LONG_INSN_CEFBRA }, 0x94, INSTR_RRF_UUFR }, 908 { { 0, LONG_INSN_CDFBRA }, 0x95, INSTR_RRF_UUFR }, 909 { { 0, LONG_INSN_CXFBRA }, 0x96, INSTR_RRF_UURF }, 910 { { 0, LONG_INSN_CFEBRA }, 0x98, INSTR_RRF_UURF }, 911 { { 0, LONG_INSN_CFDBRA }, 0x99, INSTR_RRF_UURF }, 912 { { 0, LONG_INSN_CFXBRA }, 0x9a, INSTR_RRF_UUFR }, 913 { { 0, LONG_INSN_CLFEBR }, 0x9c, INSTR_RRF_UURF }, 914 { { 0, LONG_INSN_CLFDBR }, 0x9d, INSTR_RRF_UURF }, 915 { { 0, LONG_INSN_CLFXBR }, 0x9e, INSTR_RRF_UUFR }, 916 { { 0, LONG_INSN_CELGBR }, 0xa0, INSTR_RRF_UUFR }, 917 { { 0, LONG_INSN_CDLGBR }, 0xa1, INSTR_RRF_UUFR }, 918 { { 0, LONG_INSN_CXLGBR }, 0xa2, INSTR_RRF_UURF }, 919 { { 0, LONG_INSN_CEGBRA }, 0xa4, INSTR_RRF_UUFR }, 920 { { 0, LONG_INSN_CDGBRA }, 0xa5, INSTR_RRF_UUFR }, 921 { { 0, LONG_INSN_CXGBRA }, 0xa6, INSTR_RRF_UURF }, 922 { { 0, LONG_INSN_CGEBRA }, 0xa8, INSTR_RRF_UURF }, 923 { { 0, LONG_INSN_CGDBRA }, 0xa9, INSTR_RRF_UURF }, 924 { { 0, LONG_INSN_CGXBRA }, 0xaa, INSTR_RRF_UUFR }, 925 { { 0, LONG_INSN_CLGEBR }, 0xac, INSTR_RRF_UURF }, 926 { { 0, LONG_INSN_CLGDBR }, 0xad, INSTR_RRF_UURF }, 927 { { 0, LONG_INSN_CLGXBR }, 0xae, INSTR_RRF_UUFR }, 928 { "ldgr", 0xc1, INSTR_RRE_FR }, 929 { "cegr", 0xc4, INSTR_RRE_FR }, 930 { "cdgr", 0xc5, INSTR_RRE_FR }, 931 { "cxgr", 0xc6, INSTR_RRE_FR }, 932 { "cger", 0xc8, INSTR_RRF_U0RF }, 933 { "cgdr", 0xc9, INSTR_RRF_U0RF }, 934 { "cgxr", 0xca, INSTR_RRF_U0RF }, 935 { "lgdr", 0xcd, INSTR_RRE_RF }, 936 { "mdtra", 0xd0, INSTR_RRF_FUFF2 }, 937 { "ddtra", 0xd1, INSTR_RRF_FUFF2 }, 938 { "adtra", 0xd2, INSTR_RRF_FUFF2 }, 939 { "sdtra", 0xd3, INSTR_RRF_FUFF2 }, 940 { "ldetr", 0xd4, INSTR_RRF_0UFF }, 941 { "ledtr", 0xd5, INSTR_RRF_UUFF }, 942 { "ltdtr", 0xd6, INSTR_RRE_FF }, 943 { "fidtr", 0xd7, INSTR_RRF_UUFF }, 944 { "mxtra", 0xd8, INSTR_RRF_FUFF2 }, 945 { "dxtra", 0xd9, INSTR_RRF_FUFF2 }, 946 { "axtra", 0xda, INSTR_RRF_FUFF2 }, 947 { "sxtra", 0xdb, INSTR_RRF_FUFF2 }, 948 { "lxdtr", 0xdc, INSTR_RRF_0UFF }, 949 { "ldxtr", 0xdd, INSTR_RRF_UUFF }, 950 { "ltxtr", 0xde, INSTR_RRE_FF }, 951 { "fixtr", 0xdf, INSTR_RRF_UUFF }, 952 { "kdtr", 0xe0, INSTR_RRE_FF }, 953 { { 0, LONG_INSN_CGDTRA }, 0xe1, INSTR_RRF_UURF }, 954 { "cudtr", 0xe2, INSTR_RRE_RF }, 955 { "csdtr", 0xe3, INSTR_RRE_RF }, 956 { "cdtr", 0xe4, INSTR_RRE_FF }, 957 { "eedtr", 0xe5, INSTR_RRE_RF }, 958 { "esdtr", 0xe7, INSTR_RRE_RF }, 959 { "kxtr", 0xe8, INSTR_RRE_FF }, 960 { { 0, LONG_INSN_CGXTRA }, 0xe9, INSTR_RRF_UUFR }, 961 { "cuxtr", 0xea, INSTR_RRE_RF }, 962 { "csxtr", 0xeb, INSTR_RRE_RF }, 963 { "cxtr", 0xec, INSTR_RRE_FF }, 964 { "eextr", 0xed, INSTR_RRE_RF }, 965 { "esxtr", 0xef, INSTR_RRE_RF }, 966 { { 0, LONG_INSN_CDGTRA }, 0xf1, INSTR_RRF_UUFR }, 967 { "cdutr", 0xf2, INSTR_RRE_FR }, 968 { "cdstr", 0xf3, INSTR_RRE_FR }, 969 { "cedtr", 0xf4, INSTR_RRE_FF }, 970 { "qadtr", 0xf5, INSTR_RRF_FUFF }, 971 { "iedtr", 0xf6, INSTR_RRF_F0FR }, 972 { "rrdtr", 0xf7, INSTR_RRF_FFRU }, 973 { { 0, LONG_INSN_CXGTRA }, 0xf9, INSTR_RRF_UURF }, 974 { "cxutr", 0xfa, INSTR_RRE_FR }, 975 { "cxstr", 0xfb, INSTR_RRE_FR }, 976 { "cextr", 0xfc, INSTR_RRE_FF }, 977 { "qaxtr", 0xfd, INSTR_RRF_FUFF }, 978 { "iextr", 0xfe, INSTR_RRF_F0FR }, 979 { "rrxtr", 0xff, INSTR_RRF_FFRU }, 980 { "lpebr", 0x00, INSTR_RRE_FF }, 981 { "lnebr", 0x01, INSTR_RRE_FF }, 982 { "ltebr", 0x02, INSTR_RRE_FF }, 983 { "lcebr", 0x03, INSTR_RRE_FF }, 984 { "ldebr", 0x04, INSTR_RRE_FF }, 985 { "lxdbr", 0x05, INSTR_RRE_FF }, 986 { "lxebr", 0x06, INSTR_RRE_FF }, 987 { "mxdbr", 0x07, INSTR_RRE_FF }, 988 { "kebr", 0x08, INSTR_RRE_FF }, 989 { "cebr", 0x09, INSTR_RRE_FF }, 990 { "aebr", 0x0a, INSTR_RRE_FF }, 991 { "sebr", 0x0b, INSTR_RRE_FF }, 992 { "mdebr", 0x0c, INSTR_RRE_FF }, 993 { "debr", 0x0d, INSTR_RRE_FF }, 994 { "maebr", 0x0e, INSTR_RRF_F0FF }, 995 { "msebr", 0x0f, INSTR_RRF_F0FF }, 996 { "lpdbr", 0x10, INSTR_RRE_FF }, 997 { "lndbr", 0x11, INSTR_RRE_FF }, 998 { "ltdbr", 0x12, INSTR_RRE_FF }, 999 { "lcdbr", 0x13, INSTR_RRE_FF }, 1000 { "sqebr", 0x14, INSTR_RRE_FF }, 1001 { "sqdbr", 0x15, INSTR_RRE_FF }, 1002 { "sqxbr", 0x16, INSTR_RRE_FF }, 1003 { "meebr", 0x17, INSTR_RRE_FF }, 1004 { "kdbr", 0x18, INSTR_RRE_FF }, 1005 { "cdbr", 0x19, INSTR_RRE_FF }, 1006 { "adbr", 0x1a, INSTR_RRE_FF }, 1007 { "sdbr", 0x1b, INSTR_RRE_FF }, 1008 { "mdbr", 0x1c, INSTR_RRE_FF }, 1009 { "ddbr", 0x1d, INSTR_RRE_FF }, 1010 { "madbr", 0x1e, INSTR_RRF_F0FF }, 1011 { "msdbr", 0x1f, INSTR_RRF_F0FF }, 1012 { "lder", 0x24, INSTR_RRE_FF }, 1013 { "lxdr", 0x25, INSTR_RRE_FF }, 1014 { "lxer", 0x26, INSTR_RRE_FF }, 1015 { "maer", 0x2e, INSTR_RRF_F0FF }, 1016 { "mser", 0x2f, INSTR_RRF_F0FF }, 1017 { "sqxr", 0x36, INSTR_RRE_FF }, 1018 { "meer", 0x37, INSTR_RRE_FF }, 1019 { "madr", 0x3e, INSTR_RRF_F0FF }, 1020 { "msdr", 0x3f, INSTR_RRF_F0FF }, 1021 { "lpxbr", 0x40, INSTR_RRE_FF }, 1022 { "lnxbr", 0x41, INSTR_RRE_FF }, 1023 { "ltxbr", 0x42, INSTR_RRE_FF }, 1024 { "lcxbr", 0x43, INSTR_RRE_FF }, 1025 { { 0, LONG_INSN_LEDBRA }, 0x44, INSTR_RRF_UUFF }, 1026 { { 0, LONG_INSN_LDXBRA }, 0x45, INSTR_RRF_UUFF }, 1027 { { 0, LONG_INSN_LEXBRA }, 0x46, INSTR_RRF_UUFF }, 1028 { { 0, LONG_INSN_FIXBRA }, 0x47, INSTR_RRF_UUFF }, 1029 { "kxbr", 0x48, INSTR_RRE_FF }, 1030 { "cxbr", 0x49, INSTR_RRE_FF }, 1031 { "axbr", 0x4a, INSTR_RRE_FF }, 1032 { "sxbr", 0x4b, INSTR_RRE_FF }, 1033 { "mxbr", 0x4c, INSTR_RRE_FF }, 1034 { "dxbr", 0x4d, INSTR_RRE_FF }, 1035 { "tbedr", 0x50, INSTR_RRF_U0FF }, 1036 { "tbdr", 0x51, INSTR_RRF_U0FF }, 1037 { "diebr", 0x53, INSTR_RRF_FUFF }, 1038 { { 0, LONG_INSN_FIEBRA }, 0x57, INSTR_RRF_UUFF }, 1039 { "thder", 0x58, INSTR_RRE_FF }, 1040 { "thdr", 0x59, INSTR_RRE_FF }, 1041 { "didbr", 0x5b, INSTR_RRF_FUFF }, 1042 { { 0, LONG_INSN_FIDBRA }, 0x5f, INSTR_RRF_UUFF }, 1043 { "lpxr", 0x60, INSTR_RRE_FF }, 1044 { "lnxr", 0x61, INSTR_RRE_FF }, 1045 { "ltxr", 0x62, INSTR_RRE_FF }, 1046 { "lcxr", 0x63, INSTR_RRE_FF }, 1047 { "lxr", 0x65, INSTR_RRE_FF }, 1048 { "lexr", 0x66, INSTR_RRE_FF }, 1049 { "fixr", 0x67, INSTR_RRE_FF }, 1050 { "cxr", 0x69, INSTR_RRE_FF }, 1051 { "lzer", 0x74, INSTR_RRE_F0 }, 1052 { "lzdr", 0x75, INSTR_RRE_F0 }, 1053 { "lzxr", 0x76, INSTR_RRE_F0 }, 1054 { "fier", 0x77, INSTR_RRE_FF }, 1055 { "fidr", 0x7f, INSTR_RRE_FF }, 1056 { "sfpc", 0x84, INSTR_RRE_RR_OPT }, 1057 { "efpc", 0x8c, INSTR_RRE_RR_OPT }, 1058 { "cefbr", 0x94, INSTR_RRE_RF }, 1059 { "cdfbr", 0x95, INSTR_RRE_RF }, 1060 { "cxfbr", 0x96, INSTR_RRE_RF }, 1061 { "cfebr", 0x98, INSTR_RRF_U0RF }, 1062 { "cfdbr", 0x99, INSTR_RRF_U0RF }, 1063 { "cfxbr", 0x9a, INSTR_RRF_U0RF }, 1064 { "cefr", 0xb4, INSTR_RRE_FR }, 1065 { "cdfr", 0xb5, INSTR_RRE_FR }, 1066 { "cxfr", 0xb6, INSTR_RRE_FR }, 1067 { "cfer", 0xb8, INSTR_RRF_U0RF }, 1068 { "cfdr", 0xb9, INSTR_RRF_U0RF }, 1069 { "cfxr", 0xba, INSTR_RRF_U0RF }, 1070 { "", 0, INSTR_INVALID } 1071 }; 1072 1073 static struct s390_insn opcode_b9[] = { 1074 { "lpgr", 0x00, INSTR_RRE_RR }, 1075 { "lngr", 0x01, INSTR_RRE_RR }, 1076 { "ltgr", 0x02, INSTR_RRE_RR }, 1077 { "lcgr", 0x03, INSTR_RRE_RR }, 1078 { "lgr", 0x04, INSTR_RRE_RR }, 1079 { "lurag", 0x05, INSTR_RRE_RR }, 1080 { "lgbr", 0x06, INSTR_RRE_RR }, 1081 { "lghr", 0x07, INSTR_RRE_RR }, 1082 { "agr", 0x08, INSTR_RRE_RR }, 1083 { "sgr", 0x09, INSTR_RRE_RR }, 1084 { "algr", 0x0a, INSTR_RRE_RR }, 1085 { "slgr", 0x0b, INSTR_RRE_RR }, 1086 { "msgr", 0x0c, INSTR_RRE_RR }, 1087 { "dsgr", 0x0d, INSTR_RRE_RR }, 1088 { "eregg", 0x0e, INSTR_RRE_RR }, 1089 { "lrvgr", 0x0f, INSTR_RRE_RR }, 1090 { "lpgfr", 0x10, INSTR_RRE_RR }, 1091 { "lngfr", 0x11, INSTR_RRE_RR }, 1092 { "ltgfr", 0x12, INSTR_RRE_RR }, 1093 { "lcgfr", 0x13, INSTR_RRE_RR }, 1094 { "lgfr", 0x14, INSTR_RRE_RR }, 1095 { "llgfr", 0x16, INSTR_RRE_RR }, 1096 { "llgtr", 0x17, INSTR_RRE_RR }, 1097 { "agfr", 0x18, INSTR_RRE_RR }, 1098 { "sgfr", 0x19, INSTR_RRE_RR }, 1099 { "algfr", 0x1a, INSTR_RRE_RR }, 1100 { "slgfr", 0x1b, INSTR_RRE_RR }, 1101 { "msgfr", 0x1c, INSTR_RRE_RR }, 1102 { "dsgfr", 0x1d, INSTR_RRE_RR }, 1103 { "cgr", 0x20, INSTR_RRE_RR }, 1104 { "clgr", 0x21, INSTR_RRE_RR }, 1105 { "sturg", 0x25, INSTR_RRE_RR }, 1106 { "lbr", 0x26, INSTR_RRE_RR }, 1107 { "lhr", 0x27, INSTR_RRE_RR }, 1108 { "cgfr", 0x30, INSTR_RRE_RR }, 1109 { "clgfr", 0x31, INSTR_RRE_RR }, 1110 { "cfdtr", 0x41, INSTR_RRF_UURF }, 1111 { { 0, LONG_INSN_CLGDTR }, 0x42, INSTR_RRF_UURF }, 1112 { { 0, LONG_INSN_CLFDTR }, 0x43, INSTR_RRF_UURF }, 1113 { "bctgr", 0x46, INSTR_RRE_RR }, 1114 { "cfxtr", 0x49, INSTR_RRF_UURF }, 1115 { { 0, LONG_INSN_CLGXTR }, 0x4a, INSTR_RRF_UUFR }, 1116 { { 0, LONG_INSN_CLFXTR }, 0x4b, INSTR_RRF_UUFR }, 1117 { "cdftr", 0x51, INSTR_RRF_UUFR }, 1118 { { 0, LONG_INSN_CDLGTR }, 0x52, INSTR_RRF_UUFR }, 1119 { { 0, LONG_INSN_CDLFTR }, 0x53, INSTR_RRF_UUFR }, 1120 { "cxftr", 0x59, INSTR_RRF_UURF }, 1121 { { 0, LONG_INSN_CXLGTR }, 0x5a, INSTR_RRF_UURF }, 1122 { { 0, LONG_INSN_CXLFTR }, 0x5b, INSTR_RRF_UUFR }, 1123 { "cgrt", 0x60, INSTR_RRF_U0RR }, 1124 { "clgrt", 0x61, INSTR_RRF_U0RR }, 1125 { "crt", 0x72, INSTR_RRF_U0RR }, 1126 { "clrt", 0x73, INSTR_RRF_U0RR }, 1127 { "ngr", 0x80, INSTR_RRE_RR }, 1128 { "ogr", 0x81, INSTR_RRE_RR }, 1129 { "xgr", 0x82, INSTR_RRE_RR }, 1130 { "flogr", 0x83, INSTR_RRE_RR }, 1131 { "llgcr", 0x84, INSTR_RRE_RR }, 1132 { "llghr", 0x85, INSTR_RRE_RR }, 1133 { "mlgr", 0x86, INSTR_RRE_RR }, 1134 { "dlgr", 0x87, INSTR_RRE_RR }, 1135 { "alcgr", 0x88, INSTR_RRE_RR }, 1136 { "slbgr", 0x89, INSTR_RRE_RR }, 1137 { "cspg", 0x8a, INSTR_RRE_RR }, 1138 { "idte", 0x8e, INSTR_RRF_R0RR }, 1139 { "crdte", 0x8f, INSTR_RRF_RMRR }, 1140 { "llcr", 0x94, INSTR_RRE_RR }, 1141 { "llhr", 0x95, INSTR_RRE_RR }, 1142 { "esea", 0x9d, INSTR_RRE_R0 }, 1143 { "ptf", 0xa2, INSTR_RRE_R0 }, 1144 { "lptea", 0xaa, INSTR_RRF_RURR }, 1145 { "rrbm", 0xae, INSTR_RRE_RR }, 1146 { "pfmf", 0xaf, INSTR_RRE_RR }, 1147 { "cu14", 0xb0, INSTR_RRF_M0RR }, 1148 { "cu24", 0xb1, INSTR_RRF_M0RR }, 1149 { "cu41", 0xb2, INSTR_RRE_RR }, 1150 { "cu42", 0xb3, INSTR_RRE_RR }, 1151 { "trtre", 0xbd, INSTR_RRF_M0RR }, 1152 { "srstu", 0xbe, INSTR_RRE_RR }, 1153 { "trte", 0xbf, INSTR_RRF_M0RR }, 1154 { "ahhhr", 0xc8, INSTR_RRF_R0RR2 }, 1155 { "shhhr", 0xc9, INSTR_RRF_R0RR2 }, 1156 { { 0, LONG_INSN_ALHHHR }, 0xca, INSTR_RRF_R0RR2 }, 1157 { { 0, LONG_INSN_SLHHHR }, 0xcb, INSTR_RRF_R0RR2 }, 1158 { "chhr", 0xcd, INSTR_RRE_RR }, 1159 { "clhhr", 0xcf, INSTR_RRE_RR }, 1160 { { 0, LONG_INSN_PCISTG }, 0xd0, INSTR_RRE_RR }, 1161 { "pcilg", 0xd2, INSTR_RRE_RR }, 1162 { "rpcit", 0xd3, INSTR_RRE_RR }, 1163 { "ahhlr", 0xd8, INSTR_RRF_R0RR2 }, 1164 { "shhlr", 0xd9, INSTR_RRF_R0RR2 }, 1165 { { 0, LONG_INSN_ALHHLR }, 0xda, INSTR_RRF_R0RR2 }, 1166 { { 0, LONG_INSN_SLHHLR }, 0xdb, INSTR_RRF_R0RR2 }, 1167 { "chlr", 0xdd, INSTR_RRE_RR }, 1168 { "clhlr", 0xdf, INSTR_RRE_RR }, 1169 { { 0, LONG_INSN_POPCNT }, 0xe1, INSTR_RRE_RR }, 1170 { "locgr", 0xe2, INSTR_RRF_M0RR }, 1171 { "ngrk", 0xe4, INSTR_RRF_R0RR2 }, 1172 { "ogrk", 0xe6, INSTR_RRF_R0RR2 }, 1173 { "xgrk", 0xe7, INSTR_RRF_R0RR2 }, 1174 { "agrk", 0xe8, INSTR_RRF_R0RR2 }, 1175 { "sgrk", 0xe9, INSTR_RRF_R0RR2 }, 1176 { "algrk", 0xea, INSTR_RRF_R0RR2 }, 1177 { "slgrk", 0xeb, INSTR_RRF_R0RR2 }, 1178 { "locr", 0xf2, INSTR_RRF_M0RR }, 1179 { "nrk", 0xf4, INSTR_RRF_R0RR2 }, 1180 { "ork", 0xf6, INSTR_RRF_R0RR2 }, 1181 { "xrk", 0xf7, INSTR_RRF_R0RR2 }, 1182 { "ark", 0xf8, INSTR_RRF_R0RR2 }, 1183 { "srk", 0xf9, INSTR_RRF_R0RR2 }, 1184 { "alrk", 0xfa, INSTR_RRF_R0RR2 }, 1185 { "slrk", 0xfb, INSTR_RRF_R0RR2 }, 1186 { "kmac", 0x1e, INSTR_RRE_RR }, 1187 { "lrvr", 0x1f, INSTR_RRE_RR }, 1188 { "km", 0x2e, INSTR_RRE_RR }, 1189 { "kmc", 0x2f, INSTR_RRE_RR }, 1190 { "kimd", 0x3e, INSTR_RRE_RR }, 1191 { "klmd", 0x3f, INSTR_RRE_RR }, 1192 { "epsw", 0x8d, INSTR_RRE_RR }, 1193 { "trtt", 0x90, INSTR_RRF_M0RR }, 1194 { "trto", 0x91, INSTR_RRF_M0RR }, 1195 { "trot", 0x92, INSTR_RRF_M0RR }, 1196 { "troo", 0x93, INSTR_RRF_M0RR }, 1197 { "mlr", 0x96, INSTR_RRE_RR }, 1198 { "dlr", 0x97, INSTR_RRE_RR }, 1199 { "alcr", 0x98, INSTR_RRE_RR }, 1200 { "slbr", 0x99, INSTR_RRE_RR }, 1201 { "", 0, INSTR_INVALID } 1202 }; 1203 1204 static struct s390_insn opcode_c0[] = { 1205 { "lgfi", 0x01, INSTR_RIL_RI }, 1206 { "xihf", 0x06, INSTR_RIL_RU }, 1207 { "xilf", 0x07, INSTR_RIL_RU }, 1208 { "iihf", 0x08, INSTR_RIL_RU }, 1209 { "iilf", 0x09, INSTR_RIL_RU }, 1210 { "nihf", 0x0a, INSTR_RIL_RU }, 1211 { "nilf", 0x0b, INSTR_RIL_RU }, 1212 { "oihf", 0x0c, INSTR_RIL_RU }, 1213 { "oilf", 0x0d, INSTR_RIL_RU }, 1214 { "llihf", 0x0e, INSTR_RIL_RU }, 1215 { "llilf", 0x0f, INSTR_RIL_RU }, 1216 { "larl", 0x00, INSTR_RIL_RP }, 1217 { "brcl", 0x04, INSTR_RIL_UP }, 1218 { "brasl", 0x05, INSTR_RIL_RP }, 1219 { "", 0, INSTR_INVALID } 1220 }; 1221 1222 static struct s390_insn opcode_c2[] = { 1223 { "msgfi", 0x00, INSTR_RIL_RI }, 1224 { "msfi", 0x01, INSTR_RIL_RI }, 1225 { "slgfi", 0x04, INSTR_RIL_RU }, 1226 { "slfi", 0x05, INSTR_RIL_RU }, 1227 { "agfi", 0x08, INSTR_RIL_RI }, 1228 { "afi", 0x09, INSTR_RIL_RI }, 1229 { "algfi", 0x0a, INSTR_RIL_RU }, 1230 { "alfi", 0x0b, INSTR_RIL_RU }, 1231 { "cgfi", 0x0c, INSTR_RIL_RI }, 1232 { "cfi", 0x0d, INSTR_RIL_RI }, 1233 { "clgfi", 0x0e, INSTR_RIL_RU }, 1234 { "clfi", 0x0f, INSTR_RIL_RU }, 1235 { "", 0, INSTR_INVALID } 1236 }; 1237 1238 static struct s390_insn opcode_c4[] = { 1239 { "llhrl", 0x02, INSTR_RIL_RP }, 1240 { "lghrl", 0x04, INSTR_RIL_RP }, 1241 { "lhrl", 0x05, INSTR_RIL_RP }, 1242 { { 0, LONG_INSN_LLGHRL }, 0x06, INSTR_RIL_RP }, 1243 { "sthrl", 0x07, INSTR_RIL_RP }, 1244 { "lgrl", 0x08, INSTR_RIL_RP }, 1245 { "stgrl", 0x0b, INSTR_RIL_RP }, 1246 { "lgfrl", 0x0c, INSTR_RIL_RP }, 1247 { "lrl", 0x0d, INSTR_RIL_RP }, 1248 { { 0, LONG_INSN_LLGFRL }, 0x0e, INSTR_RIL_RP }, 1249 { "strl", 0x0f, INSTR_RIL_RP }, 1250 { "", 0, INSTR_INVALID } 1251 }; 1252 1253 static struct s390_insn opcode_c6[] = { 1254 { "exrl", 0x00, INSTR_RIL_RP }, 1255 { "pfdrl", 0x02, INSTR_RIL_UP }, 1256 { "cghrl", 0x04, INSTR_RIL_RP }, 1257 { "chrl", 0x05, INSTR_RIL_RP }, 1258 { { 0, LONG_INSN_CLGHRL }, 0x06, INSTR_RIL_RP }, 1259 { "clhrl", 0x07, INSTR_RIL_RP }, 1260 { "cgrl", 0x08, INSTR_RIL_RP }, 1261 { "clgrl", 0x0a, INSTR_RIL_RP }, 1262 { "cgfrl", 0x0c, INSTR_RIL_RP }, 1263 { "crl", 0x0d, INSTR_RIL_RP }, 1264 { { 0, LONG_INSN_CLGFRL }, 0x0e, INSTR_RIL_RP }, 1265 { "clrl", 0x0f, INSTR_RIL_RP }, 1266 { "", 0, INSTR_INVALID } 1267 }; 1268 1269 static struct s390_insn opcode_c8[] = { 1270 { "mvcos", 0x00, INSTR_SSF_RRDRD }, 1271 { "ectg", 0x01, INSTR_SSF_RRDRD }, 1272 { "csst", 0x02, INSTR_SSF_RRDRD }, 1273 { "lpd", 0x04, INSTR_SSF_RRDRD2 }, 1274 { "lpdg", 0x05, INSTR_SSF_RRDRD2 }, 1275 { "", 0, INSTR_INVALID } 1276 }; 1277 1278 static struct s390_insn opcode_cc[] = { 1279 { "brcth", 0x06, INSTR_RIL_RP }, 1280 { "aih", 0x08, INSTR_RIL_RI }, 1281 { "alsih", 0x0a, INSTR_RIL_RI }, 1282 { { 0, LONG_INSN_ALSIHN }, 0x0b, INSTR_RIL_RI }, 1283 { "cih", 0x0d, INSTR_RIL_RI }, 1284 { "clih", 0x0f, INSTR_RIL_RI }, 1285 { "", 0, INSTR_INVALID } 1286 }; 1287 1288 static struct s390_insn opcode_e3[] = { 1289 { "ltg", 0x02, INSTR_RXY_RRRD }, 1290 { "lrag", 0x03, INSTR_RXY_RRRD }, 1291 { "lg", 0x04, INSTR_RXY_RRRD }, 1292 { "cvby", 0x06, INSTR_RXY_RRRD }, 1293 { "ag", 0x08, INSTR_RXY_RRRD }, 1294 { "sg", 0x09, INSTR_RXY_RRRD }, 1295 { "alg", 0x0a, INSTR_RXY_RRRD }, 1296 { "slg", 0x0b, INSTR_RXY_RRRD }, 1297 { "msg", 0x0c, INSTR_RXY_RRRD }, 1298 { "dsg", 0x0d, INSTR_RXY_RRRD }, 1299 { "cvbg", 0x0e, INSTR_RXY_RRRD }, 1300 { "lrvg", 0x0f, INSTR_RXY_RRRD }, 1301 { "lt", 0x12, INSTR_RXY_RRRD }, 1302 { "lray", 0x13, INSTR_RXY_RRRD }, 1303 { "lgf", 0x14, INSTR_RXY_RRRD }, 1304 { "lgh", 0x15, INSTR_RXY_RRRD }, 1305 { "llgf", 0x16, INSTR_RXY_RRRD }, 1306 { "llgt", 0x17, INSTR_RXY_RRRD }, 1307 { "agf", 0x18, INSTR_RXY_RRRD }, 1308 { "sgf", 0x19, INSTR_RXY_RRRD }, 1309 { "algf", 0x1a, INSTR_RXY_RRRD }, 1310 { "slgf", 0x1b, INSTR_RXY_RRRD }, 1311 { "msgf", 0x1c, INSTR_RXY_RRRD }, 1312 { "dsgf", 0x1d, INSTR_RXY_RRRD }, 1313 { "cg", 0x20, INSTR_RXY_RRRD }, 1314 { "clg", 0x21, INSTR_RXY_RRRD }, 1315 { "stg", 0x24, INSTR_RXY_RRRD }, 1316 { "ntstg", 0x25, INSTR_RXY_RRRD }, 1317 { "cvdy", 0x26, INSTR_RXY_RRRD }, 1318 { "cvdg", 0x2e, INSTR_RXY_RRRD }, 1319 { "strvg", 0x2f, INSTR_RXY_RRRD }, 1320 { "cgf", 0x30, INSTR_RXY_RRRD }, 1321 { "clgf", 0x31, INSTR_RXY_RRRD }, 1322 { "ltgf", 0x32, INSTR_RXY_RRRD }, 1323 { "cgh", 0x34, INSTR_RXY_RRRD }, 1324 { "pfd", 0x36, INSTR_RXY_URRD }, 1325 { "strvh", 0x3f, INSTR_RXY_RRRD }, 1326 { "bctg", 0x46, INSTR_RXY_RRRD }, 1327 { "sty", 0x50, INSTR_RXY_RRRD }, 1328 { "msy", 0x51, INSTR_RXY_RRRD }, 1329 { "ny", 0x54, INSTR_RXY_RRRD }, 1330 { "cly", 0x55, INSTR_RXY_RRRD }, 1331 { "oy", 0x56, INSTR_RXY_RRRD }, 1332 { "xy", 0x57, INSTR_RXY_RRRD }, 1333 { "ly", 0x58, INSTR_RXY_RRRD }, 1334 { "cy", 0x59, INSTR_RXY_RRRD }, 1335 { "ay", 0x5a, INSTR_RXY_RRRD }, 1336 { "sy", 0x5b, INSTR_RXY_RRRD }, 1337 { "mfy", 0x5c, INSTR_RXY_RRRD }, 1338 { "aly", 0x5e, INSTR_RXY_RRRD }, 1339 { "sly", 0x5f, INSTR_RXY_RRRD }, 1340 { "sthy", 0x70, INSTR_RXY_RRRD }, 1341 { "lay", 0x71, INSTR_RXY_RRRD }, 1342 { "stcy", 0x72, INSTR_RXY_RRRD }, 1343 { "icy", 0x73, INSTR_RXY_RRRD }, 1344 { "laey", 0x75, INSTR_RXY_RRRD }, 1345 { "lb", 0x76, INSTR_RXY_RRRD }, 1346 { "lgb", 0x77, INSTR_RXY_RRRD }, 1347 { "lhy", 0x78, INSTR_RXY_RRRD }, 1348 { "chy", 0x79, INSTR_RXY_RRRD }, 1349 { "ahy", 0x7a, INSTR_RXY_RRRD }, 1350 { "shy", 0x7b, INSTR_RXY_RRRD }, 1351 { "mhy", 0x7c, INSTR_RXY_RRRD }, 1352 { "ng", 0x80, INSTR_RXY_RRRD }, 1353 { "og", 0x81, INSTR_RXY_RRRD }, 1354 { "xg", 0x82, INSTR_RXY_RRRD }, 1355 { "lgat", 0x85, INSTR_RXY_RRRD }, 1356 { "mlg", 0x86, INSTR_RXY_RRRD }, 1357 { "dlg", 0x87, INSTR_RXY_RRRD }, 1358 { "alcg", 0x88, INSTR_RXY_RRRD }, 1359 { "slbg", 0x89, INSTR_RXY_RRRD }, 1360 { "stpq", 0x8e, INSTR_RXY_RRRD }, 1361 { "lpq", 0x8f, INSTR_RXY_RRRD }, 1362 { "llgc", 0x90, INSTR_RXY_RRRD }, 1363 { "llgh", 0x91, INSTR_RXY_RRRD }, 1364 { "llc", 0x94, INSTR_RXY_RRRD }, 1365 { "llh", 0x95, INSTR_RXY_RRRD }, 1366 { { 0, LONG_INSN_LLGTAT }, 0x9c, INSTR_RXY_RRRD }, 1367 { { 0, LONG_INSN_LLGFAT }, 0x9d, INSTR_RXY_RRRD }, 1368 { "lat", 0x9f, INSTR_RXY_RRRD }, 1369 { "lbh", 0xc0, INSTR_RXY_RRRD }, 1370 { "llch", 0xc2, INSTR_RXY_RRRD }, 1371 { "stch", 0xc3, INSTR_RXY_RRRD }, 1372 { "lhh", 0xc4, INSTR_RXY_RRRD }, 1373 { "llhh", 0xc6, INSTR_RXY_RRRD }, 1374 { "sthh", 0xc7, INSTR_RXY_RRRD }, 1375 { "lfhat", 0xc8, INSTR_RXY_RRRD }, 1376 { "lfh", 0xca, INSTR_RXY_RRRD }, 1377 { "stfh", 0xcb, INSTR_RXY_RRRD }, 1378 { "chf", 0xcd, INSTR_RXY_RRRD }, 1379 { "clhf", 0xcf, INSTR_RXY_RRRD }, 1380 { { 0, LONG_INSN_MPCIFC }, 0xd0, INSTR_RXY_RRRD }, 1381 { { 0, LONG_INSN_STPCIFC }, 0xd4, INSTR_RXY_RRRD }, 1382 { "lrv", 0x1e, INSTR_RXY_RRRD }, 1383 { "lrvh", 0x1f, INSTR_RXY_RRRD }, 1384 { "strv", 0x3e, INSTR_RXY_RRRD }, 1385 { "ml", 0x96, INSTR_RXY_RRRD }, 1386 { "dl", 0x97, INSTR_RXY_RRRD }, 1387 { "alc", 0x98, INSTR_RXY_RRRD }, 1388 { "slb", 0x99, INSTR_RXY_RRRD }, 1389 { "", 0, INSTR_INVALID } 1390 }; 1391 1392 static struct s390_insn opcode_e5[] = { 1393 { "strag", 0x02, INSTR_SSE_RDRD }, 1394 { "mvhhi", 0x44, INSTR_SIL_RDI }, 1395 { "mvghi", 0x48, INSTR_SIL_RDI }, 1396 { "mvhi", 0x4c, INSTR_SIL_RDI }, 1397 { "chhsi", 0x54, INSTR_SIL_RDI }, 1398 { { 0, LONG_INSN_CLHHSI }, 0x55, INSTR_SIL_RDU }, 1399 { "cghsi", 0x58, INSTR_SIL_RDI }, 1400 { { 0, LONG_INSN_CLGHSI }, 0x59, INSTR_SIL_RDU }, 1401 { "chsi", 0x5c, INSTR_SIL_RDI }, 1402 { { 0, LONG_INSN_CLFHSI }, 0x5d, INSTR_SIL_RDU }, 1403 { { 0, LONG_INSN_TBEGIN }, 0x60, INSTR_SIL_RDU }, 1404 { { 0, LONG_INSN_TBEGINC }, 0x61, INSTR_SIL_RDU }, 1405 { "lasp", 0x00, INSTR_SSE_RDRD }, 1406 { "tprot", 0x01, INSTR_SSE_RDRD }, 1407 { "mvcsk", 0x0e, INSTR_SSE_RDRD }, 1408 { "mvcdk", 0x0f, INSTR_SSE_RDRD }, 1409 { "", 0, INSTR_INVALID } 1410 }; 1411 1412 static struct s390_insn opcode_e7[] = { 1413 { "lcbb", 0x27, INSTR_RXE_RRRDM }, 1414 { "vgef", 0x13, INSTR_VRV_VVRDM }, 1415 { "vgeg", 0x12, INSTR_VRV_VVRDM }, 1416 { "vgbm", 0x44, INSTR_VRI_V0I0 }, 1417 { "vgm", 0x46, INSTR_VRI_V0IIM }, 1418 { "vl", 0x06, INSTR_VRX_VRRD0 }, 1419 { "vlr", 0x56, INSTR_VRR_VV00000 }, 1420 { "vlrp", 0x05, INSTR_VRX_VRRDM }, 1421 { "vleb", 0x00, INSTR_VRX_VRRDM }, 1422 { "vleh", 0x01, INSTR_VRX_VRRDM }, 1423 { "vlef", 0x03, INSTR_VRX_VRRDM }, 1424 { "vleg", 0x02, INSTR_VRX_VRRDM }, 1425 { "vleib", 0x40, INSTR_VRI_V0IM }, 1426 { "vleih", 0x41, INSTR_VRI_V0IM }, 1427 { "vleif", 0x43, INSTR_VRI_V0IM }, 1428 { "vleig", 0x42, INSTR_VRI_V0IM }, 1429 { "vlgv", 0x21, INSTR_VRS_RVRDM }, 1430 { "vllez", 0x04, INSTR_VRX_VRRDM }, 1431 { "vlm", 0x36, INSTR_VRS_VVRD0 }, 1432 { "vlbb", 0x07, INSTR_VRX_VRRDM }, 1433 { "vlvg", 0x22, INSTR_VRS_VRRDM }, 1434 { "vlvgp", 0x62, INSTR_VRR_VRR0000 }, 1435 { "vll", 0x37, INSTR_VRS_VRRD0 }, 1436 { "vmrh", 0x61, INSTR_VRR_VVV000M }, 1437 { "vmrl", 0x60, INSTR_VRR_VVV000M }, 1438 { "vpk", 0x94, INSTR_VRR_VVV000M }, 1439 { "vpks", 0x97, INSTR_VRR_VVV0M0M }, 1440 { "vpkls", 0x95, INSTR_VRR_VVV0M0M }, 1441 { "vperm", 0x8c, INSTR_VRR_VVV000V }, 1442 { "vpdi", 0x84, INSTR_VRR_VVV000M }, 1443 { "vrep", 0x4d, INSTR_VRI_VVIM }, 1444 { "vrepi", 0x45, INSTR_VRI_V0IM }, 1445 { "vscef", 0x1b, INSTR_VRV_VWRDM }, 1446 { "vsceg", 0x1a, INSTR_VRV_VWRDM }, 1447 { "vsel", 0x8d, INSTR_VRR_VVV000V }, 1448 { "vseg", 0x5f, INSTR_VRR_VV0000M }, 1449 { "vst", 0x0e, INSTR_VRX_VRRD0 }, 1450 { "vsteb", 0x08, INSTR_VRX_VRRDM }, 1451 { "vsteh", 0x09, INSTR_VRX_VRRDM }, 1452 { "vstef", 0x0b, INSTR_VRX_VRRDM }, 1453 { "vsteg", 0x0a, INSTR_VRX_VRRDM }, 1454 { "vstm", 0x3e, INSTR_VRS_VVRD0 }, 1455 { "vstl", 0x3f, INSTR_VRS_VRRD0 }, 1456 { "vuph", 0xd7, INSTR_VRR_VV0000M }, 1457 { "vuplh", 0xd5, INSTR_VRR_VV0000M }, 1458 { "vupl", 0xd6, INSTR_VRR_VV0000M }, 1459 { "vupll", 0xd4, INSTR_VRR_VV0000M }, 1460 { "va", 0xf3, INSTR_VRR_VVV000M }, 1461 { "vacc", 0xf1, INSTR_VRR_VVV000M }, 1462 { "vac", 0xbb, INSTR_VRR_VVVM00V }, 1463 { "vaccc", 0xb9, INSTR_VRR_VVVM00V }, 1464 { "vn", 0x68, INSTR_VRR_VVV0000 }, 1465 { "vnc", 0x69, INSTR_VRR_VVV0000 }, 1466 { "vavg", 0xf2, INSTR_VRR_VVV000M }, 1467 { "vavgl", 0xf0, INSTR_VRR_VVV000M }, 1468 { "vcksm", 0x66, INSTR_VRR_VVV0000 }, 1469 { "vec", 0xdb, INSTR_VRR_VV0000M }, 1470 { "vecl", 0xd9, INSTR_VRR_VV0000M }, 1471 { "vceq", 0xf8, INSTR_VRR_VVV0M0M }, 1472 { "vch", 0xfb, INSTR_VRR_VVV0M0M }, 1473 { "vchl", 0xf9, INSTR_VRR_VVV0M0M }, 1474 { "vclz", 0x53, INSTR_VRR_VV0000M }, 1475 { "vctz", 0x52, INSTR_VRR_VV0000M }, 1476 { "vx", 0x6d, INSTR_VRR_VVV0000 }, 1477 { "vgfm", 0xb4, INSTR_VRR_VVV000M }, 1478 { "vgfma", 0xbc, INSTR_VRR_VVVM00V }, 1479 { "vlc", 0xde, INSTR_VRR_VV0000M }, 1480 { "vlp", 0xdf, INSTR_VRR_VV0000M }, 1481 { "vmx", 0xff, INSTR_VRR_VVV000M }, 1482 { "vmxl", 0xfd, INSTR_VRR_VVV000M }, 1483 { "vmn", 0xfe, INSTR_VRR_VVV000M }, 1484 { "vmnl", 0xfc, INSTR_VRR_VVV000M }, 1485 { "vmal", 0xaa, INSTR_VRR_VVVM00V }, 1486 { "vmae", 0xae, INSTR_VRR_VVVM00V }, 1487 { "vmale", 0xac, INSTR_VRR_VVVM00V }, 1488 { "vmah", 0xab, INSTR_VRR_VVVM00V }, 1489 { "vmalh", 0xa9, INSTR_VRR_VVVM00V }, 1490 { "vmao", 0xaf, INSTR_VRR_VVVM00V }, 1491 { "vmalo", 0xad, INSTR_VRR_VVVM00V }, 1492 { "vmh", 0xa3, INSTR_VRR_VVV000M }, 1493 { "vmlh", 0xa1, INSTR_VRR_VVV000M }, 1494 { "vml", 0xa2, INSTR_VRR_VVV000M }, 1495 { "vme", 0xa6, INSTR_VRR_VVV000M }, 1496 { "vmle", 0xa4, INSTR_VRR_VVV000M }, 1497 { "vmo", 0xa7, INSTR_VRR_VVV000M }, 1498 { "vmlo", 0xa5, INSTR_VRR_VVV000M }, 1499 { "vno", 0x6b, INSTR_VRR_VVV0000 }, 1500 { "vo", 0x6a, INSTR_VRR_VVV0000 }, 1501 { { 0, LONG_INSN_VPOPCT }, 0x50, INSTR_VRR_VV0000M }, 1502 { { 0, LONG_INSN_VERLLV }, 0x73, INSTR_VRR_VVV000M }, 1503 { "verll", 0x33, INSTR_VRS_VVRDM }, 1504 { "verim", 0x72, INSTR_VRI_VVV0IM }, 1505 { "veslv", 0x70, INSTR_VRR_VVV000M }, 1506 { "vesl", 0x30, INSTR_VRS_VVRDM }, 1507 { { 0, LONG_INSN_VESRAV }, 0x7a, INSTR_VRR_VVV000M }, 1508 { "vesra", 0x3a, INSTR_VRS_VVRDM }, 1509 { { 0, LONG_INSN_VESRLV }, 0x78, INSTR_VRR_VVV000M }, 1510 { "vesrl", 0x38, INSTR_VRS_VVRDM }, 1511 { "vsl", 0x74, INSTR_VRR_VVV0000 }, 1512 { "vslb", 0x75, INSTR_VRR_VVV0000 }, 1513 { "vsldb", 0x77, INSTR_VRI_VVV0I0 }, 1514 { "vsra", 0x7e, INSTR_VRR_VVV0000 }, 1515 { "vsrab", 0x7f, INSTR_VRR_VVV0000 }, 1516 { "vsrl", 0x7c, INSTR_VRR_VVV0000 }, 1517 { "vsrlb", 0x7d, INSTR_VRR_VVV0000 }, 1518 { "vs", 0xf7, INSTR_VRR_VVV000M }, 1519 { "vscb", 0xf5, INSTR_VRR_VVV000M }, 1520 { "vsb", 0xbf, INSTR_VRR_VVVM00V }, 1521 { { 0, LONG_INSN_VSBCBI }, 0xbd, INSTR_VRR_VVVM00V }, 1522 { "vsumg", 0x65, INSTR_VRR_VVV000M }, 1523 { "vsumq", 0x67, INSTR_VRR_VVV000M }, 1524 { "vsum", 0x64, INSTR_VRR_VVV000M }, 1525 { "vtm", 0xd8, INSTR_VRR_VV00000 }, 1526 { "vfae", 0x82, INSTR_VRR_VVV0M0M }, 1527 { "vfee", 0x80, INSTR_VRR_VVV0M0M }, 1528 { "vfene", 0x81, INSTR_VRR_VVV0M0M }, 1529 { "vistr", 0x5c, INSTR_VRR_VV00M0M }, 1530 { "vstrc", 0x8a, INSTR_VRR_VVVMM0V }, 1531 { "vfa", 0xe3, INSTR_VRR_VVV00MM }, 1532 { "wfc", 0xcb, INSTR_VRR_VV000MM }, 1533 { "wfk", 0xca, INSTR_VRR_VV000MM }, 1534 { "vfce", 0xe8, INSTR_VRR_VVV0MMM }, 1535 { "vfch", 0xeb, INSTR_VRR_VVV0MMM }, 1536 { "vfche", 0xea, INSTR_VRR_VVV0MMM }, 1537 { "vcdg", 0xc3, INSTR_VRR_VV00MMM }, 1538 { "vcdlg", 0xc1, INSTR_VRR_VV00MMM }, 1539 { "vcgd", 0xc2, INSTR_VRR_VV00MMM }, 1540 { "vclgd", 0xc0, INSTR_VRR_VV00MMM }, 1541 { "vfd", 0xe5, INSTR_VRR_VVV00MM }, 1542 { "vfi", 0xc7, INSTR_VRR_VV00MMM }, 1543 { "vlde", 0xc4, INSTR_VRR_VV000MM }, 1544 { "vled", 0xc5, INSTR_VRR_VV00MMM }, 1545 { "vfm", 0xe7, INSTR_VRR_VVV00MM }, 1546 { "vfma", 0x8f, INSTR_VRR_VVVM0MV }, 1547 { "vfms", 0x8e, INSTR_VRR_VVVM0MV }, 1548 { "vfpso", 0xcc, INSTR_VRR_VV00MMM }, 1549 { "vfsq", 0xce, INSTR_VRR_VV000MM }, 1550 { "vfs", 0xe2, INSTR_VRR_VVV00MM }, 1551 { "vftci", 0x4a, INSTR_VRI_VVIMM }, 1552 }; 1553 1554 static struct s390_insn opcode_eb[] = { 1555 { "lmg", 0x04, INSTR_RSY_RRRD }, 1556 { "srag", 0x0a, INSTR_RSY_RRRD }, 1557 { "slag", 0x0b, INSTR_RSY_RRRD }, 1558 { "srlg", 0x0c, INSTR_RSY_RRRD }, 1559 { "sllg", 0x0d, INSTR_RSY_RRRD }, 1560 { "tracg", 0x0f, INSTR_RSY_RRRD }, 1561 { "csy", 0x14, INSTR_RSY_RRRD }, 1562 { "rllg", 0x1c, INSTR_RSY_RRRD }, 1563 { "clmh", 0x20, INSTR_RSY_RURD }, 1564 { "clmy", 0x21, INSTR_RSY_RURD }, 1565 { "clt", 0x23, INSTR_RSY_RURD }, 1566 { "stmg", 0x24, INSTR_RSY_RRRD }, 1567 { "stctg", 0x25, INSTR_RSY_CCRD }, 1568 { "stmh", 0x26, INSTR_RSY_RRRD }, 1569 { "clgt", 0x2b, INSTR_RSY_RURD }, 1570 { "stcmh", 0x2c, INSTR_RSY_RURD }, 1571 { "stcmy", 0x2d, INSTR_RSY_RURD }, 1572 { "lctlg", 0x2f, INSTR_RSY_CCRD }, 1573 { "csg", 0x30, INSTR_RSY_RRRD }, 1574 { "cdsy", 0x31, INSTR_RSY_RRRD }, 1575 { "cdsg", 0x3e, INSTR_RSY_RRRD }, 1576 { "bxhg", 0x44, INSTR_RSY_RRRD }, 1577 { "bxleg", 0x45, INSTR_RSY_RRRD }, 1578 { "ecag", 0x4c, INSTR_RSY_RRRD }, 1579 { "tmy", 0x51, INSTR_SIY_URD }, 1580 { "mviy", 0x52, INSTR_SIY_URD }, 1581 { "niy", 0x54, INSTR_SIY_URD }, 1582 { "cliy", 0x55, INSTR_SIY_URD }, 1583 { "oiy", 0x56, INSTR_SIY_URD }, 1584 { "xiy", 0x57, INSTR_SIY_URD }, 1585 { "asi", 0x6a, INSTR_SIY_IRD }, 1586 { "alsi", 0x6e, INSTR_SIY_IRD }, 1587 { "agsi", 0x7a, INSTR_SIY_IRD }, 1588 { "algsi", 0x7e, INSTR_SIY_IRD }, 1589 { "icmh", 0x80, INSTR_RSY_RURD }, 1590 { "icmy", 0x81, INSTR_RSY_RURD }, 1591 { "clclu", 0x8f, INSTR_RSY_RRRD }, 1592 { "stmy", 0x90, INSTR_RSY_RRRD }, 1593 { "lmh", 0x96, INSTR_RSY_RRRD }, 1594 { "lmy", 0x98, INSTR_RSY_RRRD }, 1595 { "lamy", 0x9a, INSTR_RSY_AARD }, 1596 { "stamy", 0x9b, INSTR_RSY_AARD }, 1597 { { 0, LONG_INSN_PCISTB }, 0xd0, INSTR_RSY_RRRD }, 1598 { "sic", 0xd1, INSTR_RSY_RRRD }, 1599 { "srak", 0xdc, INSTR_RSY_RRRD }, 1600 { "slak", 0xdd, INSTR_RSY_RRRD }, 1601 { "srlk", 0xde, INSTR_RSY_RRRD }, 1602 { "sllk", 0xdf, INSTR_RSY_RRRD }, 1603 { "locg", 0xe2, INSTR_RSY_RDRM }, 1604 { "stocg", 0xe3, INSTR_RSY_RDRM }, 1605 { "lang", 0xe4, INSTR_RSY_RRRD }, 1606 { "laog", 0xe6, INSTR_RSY_RRRD }, 1607 { "laxg", 0xe7, INSTR_RSY_RRRD }, 1608 { "laag", 0xe8, INSTR_RSY_RRRD }, 1609 { "laalg", 0xea, INSTR_RSY_RRRD }, 1610 { "loc", 0xf2, INSTR_RSY_RDRM }, 1611 { "stoc", 0xf3, INSTR_RSY_RDRM }, 1612 { "lan", 0xf4, INSTR_RSY_RRRD }, 1613 { "lao", 0xf6, INSTR_RSY_RRRD }, 1614 { "lax", 0xf7, INSTR_RSY_RRRD }, 1615 { "laa", 0xf8, INSTR_RSY_RRRD }, 1616 { "laal", 0xfa, INSTR_RSY_RRRD }, 1617 { "lric", 0x60, INSTR_RSY_RDRM }, 1618 { "stric", 0x61, INSTR_RSY_RDRM }, 1619 { "mric", 0x62, INSTR_RSY_RDRM }, 1620 { { 0, LONG_INSN_STCCTM }, 0x17, INSTR_RSY_RMRD }, 1621 { "rll", 0x1d, INSTR_RSY_RRRD }, 1622 { "mvclu", 0x8e, INSTR_RSY_RRRD }, 1623 { "tp", 0xc0, INSTR_RSL_R0RD }, 1624 { "", 0, INSTR_INVALID } 1625 }; 1626 1627 static struct s390_insn opcode_ec[] = { 1628 { "brxhg", 0x44, INSTR_RIE_RRP }, 1629 { "brxlg", 0x45, INSTR_RIE_RRP }, 1630 { { 0, LONG_INSN_RISBLG }, 0x51, INSTR_RIE_RRUUU }, 1631 { "rnsbg", 0x54, INSTR_RIE_RRUUU }, 1632 { "risbg", 0x55, INSTR_RIE_RRUUU }, 1633 { "rosbg", 0x56, INSTR_RIE_RRUUU }, 1634 { "rxsbg", 0x57, INSTR_RIE_RRUUU }, 1635 { { 0, LONG_INSN_RISBGN }, 0x59, INSTR_RIE_RRUUU }, 1636 { { 0, LONG_INSN_RISBHG }, 0x5D, INSTR_RIE_RRUUU }, 1637 { "cgrj", 0x64, INSTR_RIE_RRPU }, 1638 { "clgrj", 0x65, INSTR_RIE_RRPU }, 1639 { "cgit", 0x70, INSTR_RIE_R0IU }, 1640 { "clgit", 0x71, INSTR_RIE_R0UU }, 1641 { "cit", 0x72, INSTR_RIE_R0IU }, 1642 { "clfit", 0x73, INSTR_RIE_R0UU }, 1643 { "crj", 0x76, INSTR_RIE_RRPU }, 1644 { "clrj", 0x77, INSTR_RIE_RRPU }, 1645 { "cgij", 0x7c, INSTR_RIE_RUPI }, 1646 { "clgij", 0x7d, INSTR_RIE_RUPU }, 1647 { "cij", 0x7e, INSTR_RIE_RUPI }, 1648 { "clij", 0x7f, INSTR_RIE_RUPU }, 1649 { "ahik", 0xd8, INSTR_RIE_RRI0 }, 1650 { "aghik", 0xd9, INSTR_RIE_RRI0 }, 1651 { { 0, LONG_INSN_ALHSIK }, 0xda, INSTR_RIE_RRI0 }, 1652 { { 0, LONG_INSN_ALGHSIK }, 0xdb, INSTR_RIE_RRI0 }, 1653 { "cgrb", 0xe4, INSTR_RRS_RRRDU }, 1654 { "clgrb", 0xe5, INSTR_RRS_RRRDU }, 1655 { "crb", 0xf6, INSTR_RRS_RRRDU }, 1656 { "clrb", 0xf7, INSTR_RRS_RRRDU }, 1657 { "cgib", 0xfc, INSTR_RIS_RURDI }, 1658 { "clgib", 0xfd, INSTR_RIS_RURDU }, 1659 { "cib", 0xfe, INSTR_RIS_RURDI }, 1660 { "clib", 0xff, INSTR_RIS_RURDU }, 1661 { "", 0, INSTR_INVALID } 1662 }; 1663 1664 static struct s390_insn opcode_ed[] = { 1665 { "mayl", 0x38, INSTR_RXF_FRRDF }, 1666 { "myl", 0x39, INSTR_RXF_FRRDF }, 1667 { "may", 0x3a, INSTR_RXF_FRRDF }, 1668 { "my", 0x3b, INSTR_RXF_FRRDF }, 1669 { "mayh", 0x3c, INSTR_RXF_FRRDF }, 1670 { "myh", 0x3d, INSTR_RXF_FRRDF }, 1671 { "sldt", 0x40, INSTR_RXF_FRRDF }, 1672 { "srdt", 0x41, INSTR_RXF_FRRDF }, 1673 { "slxt", 0x48, INSTR_RXF_FRRDF }, 1674 { "srxt", 0x49, INSTR_RXF_FRRDF }, 1675 { "tdcet", 0x50, INSTR_RXE_FRRD }, 1676 { "tdget", 0x51, INSTR_RXE_FRRD }, 1677 { "tdcdt", 0x54, INSTR_RXE_FRRD }, 1678 { "tdgdt", 0x55, INSTR_RXE_FRRD }, 1679 { "tdcxt", 0x58, INSTR_RXE_FRRD }, 1680 { "tdgxt", 0x59, INSTR_RXE_FRRD }, 1681 { "ley", 0x64, INSTR_RXY_FRRD }, 1682 { "ldy", 0x65, INSTR_RXY_FRRD }, 1683 { "stey", 0x66, INSTR_RXY_FRRD }, 1684 { "stdy", 0x67, INSTR_RXY_FRRD }, 1685 { "czdt", 0xa8, INSTR_RSL_LRDFU }, 1686 { "czxt", 0xa9, INSTR_RSL_LRDFU }, 1687 { "cdzt", 0xaa, INSTR_RSL_LRDFU }, 1688 { "cxzt", 0xab, INSTR_RSL_LRDFU }, 1689 { "ldeb", 0x04, INSTR_RXE_FRRD }, 1690 { "lxdb", 0x05, INSTR_RXE_FRRD }, 1691 { "lxeb", 0x06, INSTR_RXE_FRRD }, 1692 { "mxdb", 0x07, INSTR_RXE_FRRD }, 1693 { "keb", 0x08, INSTR_RXE_FRRD }, 1694 { "ceb", 0x09, INSTR_RXE_FRRD }, 1695 { "aeb", 0x0a, INSTR_RXE_FRRD }, 1696 { "seb", 0x0b, INSTR_RXE_FRRD }, 1697 { "mdeb", 0x0c, INSTR_RXE_FRRD }, 1698 { "deb", 0x0d, INSTR_RXE_FRRD }, 1699 { "maeb", 0x0e, INSTR_RXF_FRRDF }, 1700 { "mseb", 0x0f, INSTR_RXF_FRRDF }, 1701 { "tceb", 0x10, INSTR_RXE_FRRD }, 1702 { "tcdb", 0x11, INSTR_RXE_FRRD }, 1703 { "tcxb", 0x12, INSTR_RXE_FRRD }, 1704 { "sqeb", 0x14, INSTR_RXE_FRRD }, 1705 { "sqdb", 0x15, INSTR_RXE_FRRD }, 1706 { "meeb", 0x17, INSTR_RXE_FRRD }, 1707 { "kdb", 0x18, INSTR_RXE_FRRD }, 1708 { "cdb", 0x19, INSTR_RXE_FRRD }, 1709 { "adb", 0x1a, INSTR_RXE_FRRD }, 1710 { "sdb", 0x1b, INSTR_RXE_FRRD }, 1711 { "mdb", 0x1c, INSTR_RXE_FRRD }, 1712 { "ddb", 0x1d, INSTR_RXE_FRRD }, 1713 { "madb", 0x1e, INSTR_RXF_FRRDF }, 1714 { "msdb", 0x1f, INSTR_RXF_FRRDF }, 1715 { "lde", 0x24, INSTR_RXE_FRRD }, 1716 { "lxd", 0x25, INSTR_RXE_FRRD }, 1717 { "lxe", 0x26, INSTR_RXE_FRRD }, 1718 { "mae", 0x2e, INSTR_RXF_FRRDF }, 1719 { "mse", 0x2f, INSTR_RXF_FRRDF }, 1720 { "sqe", 0x34, INSTR_RXE_FRRD }, 1721 { "sqd", 0x35, INSTR_RXE_FRRD }, 1722 { "mee", 0x37, INSTR_RXE_FRRD }, 1723 { "mad", 0x3e, INSTR_RXF_FRRDF }, 1724 { "msd", 0x3f, INSTR_RXF_FRRDF }, 1725 { "", 0, INSTR_INVALID } 1726 }; 1727 1728 /* Extracts an operand value from an instruction. */ 1729 static unsigned int extract_operand(unsigned char *code, 1730 const struct s390_operand *operand) 1731 { 1732 unsigned char *cp; 1733 unsigned int val; 1734 int bits; 1735 1736 /* Extract fragments of the operand byte for byte. */ 1737 cp = code + operand->shift / 8; 1738 bits = (operand->shift & 7) + operand->bits; 1739 val = 0; 1740 do { 1741 val <<= 8; 1742 val |= (unsigned int) *cp++; 1743 bits -= 8; 1744 } while (bits > 0); 1745 val >>= -bits; 1746 val &= ((1U << (operand->bits - 1)) << 1) - 1; 1747 1748 /* Check for special long displacement case. */ 1749 if (operand->bits == 20 && operand->shift == 20) 1750 val = (val & 0xff) << 12 | (val & 0xfff00) >> 8; 1751 1752 /* Check for register extensions bits for vector registers. */ 1753 if (operand->flags & OPERAND_VR) { 1754 if (operand->shift == 8) 1755 val |= (code[4] & 8) << 1; 1756 else if (operand->shift == 12) 1757 val |= (code[4] & 4) << 2; 1758 else if (operand->shift == 16) 1759 val |= (code[4] & 2) << 3; 1760 else if (operand->shift == 32) 1761 val |= (code[4] & 1) << 4; 1762 } 1763 1764 /* Sign extend value if the operand is signed or pc relative. */ 1765 if ((operand->flags & (OPERAND_SIGNED | OPERAND_PCREL)) && 1766 (val & (1U << (operand->bits - 1)))) 1767 val |= (-1U << (operand->bits - 1)) << 1; 1768 1769 /* Double value if the operand is pc relative. */ 1770 if (operand->flags & OPERAND_PCREL) 1771 val <<= 1; 1772 1773 /* Length x in an instructions has real length x + 1. */ 1774 if (operand->flags & OPERAND_LENGTH) 1775 val++; 1776 return val; 1777 } 1778 1779 struct s390_insn *find_insn(unsigned char *code) 1780 { 1781 unsigned char opfrag = code[1]; 1782 unsigned char opmask; 1783 struct s390_insn *table; 1784 1785 switch (code[0]) { 1786 case 0x01: 1787 table = opcode_01; 1788 break; 1789 case 0xa5: 1790 table = opcode_a5; 1791 break; 1792 case 0xa7: 1793 table = opcode_a7; 1794 break; 1795 case 0xaa: 1796 table = opcode_aa; 1797 break; 1798 case 0xb2: 1799 table = opcode_b2; 1800 break; 1801 case 0xb3: 1802 table = opcode_b3; 1803 break; 1804 case 0xb9: 1805 table = opcode_b9; 1806 break; 1807 case 0xc0: 1808 table = opcode_c0; 1809 break; 1810 case 0xc2: 1811 table = opcode_c2; 1812 break; 1813 case 0xc4: 1814 table = opcode_c4; 1815 break; 1816 case 0xc6: 1817 table = opcode_c6; 1818 break; 1819 case 0xc8: 1820 table = opcode_c8; 1821 break; 1822 case 0xcc: 1823 table = opcode_cc; 1824 break; 1825 case 0xe3: 1826 table = opcode_e3; 1827 opfrag = code[5]; 1828 break; 1829 case 0xe5: 1830 table = opcode_e5; 1831 break; 1832 case 0xe7: 1833 table = opcode_e7; 1834 opfrag = code[5]; 1835 break; 1836 case 0xeb: 1837 table = opcode_eb; 1838 opfrag = code[5]; 1839 break; 1840 case 0xec: 1841 table = opcode_ec; 1842 opfrag = code[5]; 1843 break; 1844 case 0xed: 1845 table = opcode_ed; 1846 opfrag = code[5]; 1847 break; 1848 default: 1849 table = opcode; 1850 opfrag = code[0]; 1851 break; 1852 } 1853 while (table->format != INSTR_INVALID) { 1854 opmask = formats[table->format][0]; 1855 if (table->opfrag == (opfrag & opmask)) 1856 return table; 1857 table++; 1858 } 1859 return NULL; 1860 } 1861 1862 /** 1863 * insn_to_mnemonic - decode an s390 instruction 1864 * @instruction: instruction to decode 1865 * @buf: buffer to fill with mnemonic 1866 * @len: length of buffer 1867 * 1868 * Decode the instruction at @instruction and store the corresponding 1869 * mnemonic into @buf of length @len. 1870 * @buf is left unchanged if the instruction could not be decoded. 1871 * Returns: 1872 * %0 on success, %-ENOENT if the instruction was not found. 1873 */ 1874 int insn_to_mnemonic(unsigned char *instruction, char *buf, unsigned int len) 1875 { 1876 struct s390_insn *insn; 1877 1878 insn = find_insn(instruction); 1879 if (!insn) 1880 return -ENOENT; 1881 if (insn->name[0] == '\0') 1882 snprintf(buf, len, "%s", 1883 long_insn_name[(int) insn->name[1]]); 1884 else 1885 snprintf(buf, len, "%.5s", insn->name); 1886 return 0; 1887 } 1888 EXPORT_SYMBOL_GPL(insn_to_mnemonic); 1889 1890 static int print_insn(char *buffer, unsigned char *code, unsigned long addr) 1891 { 1892 struct s390_insn *insn; 1893 const unsigned char *ops; 1894 const struct s390_operand *operand; 1895 unsigned int value; 1896 char separator; 1897 char *ptr; 1898 int i; 1899 1900 ptr = buffer; 1901 insn = find_insn(code); 1902 if (insn) { 1903 if (insn->name[0] == '\0') 1904 ptr += sprintf(ptr, "%s\t", 1905 long_insn_name[(int) insn->name[1]]); 1906 else 1907 ptr += sprintf(ptr, "%.5s\t", insn->name); 1908 /* Extract the operands. */ 1909 separator = 0; 1910 for (ops = formats[insn->format] + 1, i = 0; 1911 *ops != 0 && i < 6; ops++, i++) { 1912 operand = operands + *ops; 1913 value = extract_operand(code, operand); 1914 if ((operand->flags & OPERAND_INDEX) && value == 0) 1915 continue; 1916 if ((operand->flags & OPERAND_BASE) && 1917 value == 0 && separator == '(') { 1918 separator = ','; 1919 continue; 1920 } 1921 if (separator) 1922 ptr += sprintf(ptr, "%c", separator); 1923 if (operand->flags & OPERAND_GPR) 1924 ptr += sprintf(ptr, "%%r%i", value); 1925 else if (operand->flags & OPERAND_FPR) 1926 ptr += sprintf(ptr, "%%f%i", value); 1927 else if (operand->flags & OPERAND_AR) 1928 ptr += sprintf(ptr, "%%a%i", value); 1929 else if (operand->flags & OPERAND_CR) 1930 ptr += sprintf(ptr, "%%c%i", value); 1931 else if (operand->flags & OPERAND_VR) 1932 ptr += sprintf(ptr, "%%v%i", value); 1933 else if (operand->flags & OPERAND_PCREL) 1934 ptr += sprintf(ptr, "%lx", (signed int) value 1935 + addr); 1936 else if (operand->flags & OPERAND_SIGNED) 1937 ptr += sprintf(ptr, "%i", value); 1938 else 1939 ptr += sprintf(ptr, "%u", value); 1940 if (operand->flags & OPERAND_DISP) 1941 separator = '('; 1942 else if (operand->flags & OPERAND_BASE) { 1943 ptr += sprintf(ptr, ")"); 1944 separator = ','; 1945 } else 1946 separator = ','; 1947 } 1948 } else 1949 ptr += sprintf(ptr, "unknown"); 1950 return (int) (ptr - buffer); 1951 } 1952 1953 void show_code(struct pt_regs *regs) 1954 { 1955 char *mode = user_mode(regs) ? "User" : "Krnl"; 1956 unsigned char code[64]; 1957 char buffer[64], *ptr; 1958 mm_segment_t old_fs; 1959 unsigned long addr; 1960 int start, end, opsize, hops, i; 1961 1962 /* Get a snapshot of the 64 bytes surrounding the fault address. */ 1963 old_fs = get_fs(); 1964 set_fs(user_mode(regs) ? USER_DS : KERNEL_DS); 1965 for (start = 32; start && regs->psw.addr >= 34 - start; start -= 2) { 1966 addr = regs->psw.addr - 34 + start; 1967 if (__copy_from_user(code + start - 2, 1968 (char __user *) addr, 2)) 1969 break; 1970 } 1971 for (end = 32; end < 64; end += 2) { 1972 addr = regs->psw.addr + end - 32; 1973 if (__copy_from_user(code + end, 1974 (char __user *) addr, 2)) 1975 break; 1976 } 1977 set_fs(old_fs); 1978 /* Code snapshot useable ? */ 1979 if ((regs->psw.addr & 1) || start >= end) { 1980 printk("%s Code: Bad PSW.\n", mode); 1981 return; 1982 } 1983 /* Find a starting point for the disassembly. */ 1984 while (start < 32) { 1985 for (i = 0, hops = 0; start + i < 32 && hops < 3; hops++) { 1986 if (!find_insn(code + start + i)) 1987 break; 1988 i += insn_length(code[start + i]); 1989 } 1990 if (start + i == 32) 1991 /* Looks good, sequence ends at PSW. */ 1992 break; 1993 start += 2; 1994 } 1995 /* Decode the instructions. */ 1996 ptr = buffer; 1997 ptr += sprintf(ptr, "%s Code:", mode); 1998 hops = 0; 1999 while (start < end && hops < 8) { 2000 opsize = insn_length(code[start]); 2001 if (start + opsize == 32) 2002 *ptr++ = '#'; 2003 else if (start == 32) 2004 *ptr++ = '>'; 2005 else 2006 *ptr++ = ' '; 2007 addr = regs->psw.addr + start - 32; 2008 ptr += sprintf(ptr, "%016lx: ", addr); 2009 if (start + opsize >= end) 2010 break; 2011 for (i = 0; i < opsize; i++) 2012 ptr += sprintf(ptr, "%02x", code[start + i]); 2013 *ptr++ = '\t'; 2014 if (i < 6) 2015 *ptr++ = '\t'; 2016 ptr += print_insn(ptr, code + start, addr); 2017 start += opsize; 2018 printk(buffer); 2019 ptr = buffer; 2020 ptr += sprintf(ptr, "\n "); 2021 hops++; 2022 } 2023 printk("\n"); 2024 } 2025 2026 void print_fn_code(unsigned char *code, unsigned long len) 2027 { 2028 char buffer[64], *ptr; 2029 int opsize, i; 2030 2031 while (len) { 2032 ptr = buffer; 2033 opsize = insn_length(*code); 2034 if (opsize > len) 2035 break; 2036 ptr += sprintf(ptr, "%p: ", code); 2037 for (i = 0; i < opsize; i++) 2038 ptr += sprintf(ptr, "%02x", code[i]); 2039 *ptr++ = '\t'; 2040 if (i < 4) 2041 *ptr++ = '\t'; 2042 ptr += print_insn(ptr, code, (unsigned long) code); 2043 *ptr++ = '\n'; 2044 *ptr++ = 0; 2045 printk(buffer); 2046 code += opsize; 2047 len -= opsize; 2048 } 2049 } 2050