1 /* 2 * arch/s390/kernel/dis.c 3 * 4 * Disassemble s390 instructions. 5 * 6 * Copyright IBM Corp. 2007 7 * Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com), 8 */ 9 10 #include <linux/sched.h> 11 #include <linux/kernel.h> 12 #include <linux/string.h> 13 #include <linux/errno.h> 14 #include <linux/ptrace.h> 15 #include <linux/timer.h> 16 #include <linux/mm.h> 17 #include <linux/smp.h> 18 #include <linux/init.h> 19 #include <linux/interrupt.h> 20 #include <linux/delay.h> 21 #include <linux/module.h> 22 #include <linux/kallsyms.h> 23 #include <linux/reboot.h> 24 #include <linux/kprobes.h> 25 #include <linux/kdebug.h> 26 27 #include <asm/system.h> 28 #include <asm/uaccess.h> 29 #include <asm/io.h> 30 #include <asm/atomic.h> 31 #include <asm/mathemu.h> 32 #include <asm/cpcmd.h> 33 #include <asm/s390_ext.h> 34 #include <asm/lowcore.h> 35 #include <asm/debug.h> 36 37 #ifndef CONFIG_64BIT 38 #define ONELONG "%08lx: " 39 #else /* CONFIG_64BIT */ 40 #define ONELONG "%016lx: " 41 #endif /* CONFIG_64BIT */ 42 43 #define OPERAND_GPR 0x1 /* Operand printed as %rx */ 44 #define OPERAND_FPR 0x2 /* Operand printed as %fx */ 45 #define OPERAND_AR 0x4 /* Operand printed as %ax */ 46 #define OPERAND_CR 0x8 /* Operand printed as %cx */ 47 #define OPERAND_DISP 0x10 /* Operand printed as displacement */ 48 #define OPERAND_BASE 0x20 /* Operand printed as base register */ 49 #define OPERAND_INDEX 0x40 /* Operand printed as index register */ 50 #define OPERAND_PCREL 0x80 /* Operand printed as pc-relative symbol */ 51 #define OPERAND_SIGNED 0x100 /* Operand printed as signed value */ 52 #define OPERAND_LENGTH 0x200 /* Operand printed as length (+1) */ 53 54 enum { 55 UNUSED, /* Indicates the end of the operand list */ 56 R_8, /* GPR starting at position 8 */ 57 R_12, /* GPR starting at position 12 */ 58 R_16, /* GPR starting at position 16 */ 59 R_20, /* GPR starting at position 20 */ 60 R_24, /* GPR starting at position 24 */ 61 R_28, /* GPR starting at position 28 */ 62 R_32, /* GPR starting at position 32 */ 63 F_8, /* FPR starting at position 8 */ 64 F_12, /* FPR starting at position 12 */ 65 F_16, /* FPR starting at position 16 */ 66 F_20, /* FPR starting at position 16 */ 67 F_24, /* FPR starting at position 24 */ 68 F_28, /* FPR starting at position 28 */ 69 F_32, /* FPR starting at position 32 */ 70 A_8, /* Access reg. starting at position 8 */ 71 A_12, /* Access reg. starting at position 12 */ 72 A_24, /* Access reg. starting at position 24 */ 73 A_28, /* Access reg. starting at position 28 */ 74 C_8, /* Control reg. starting at position 8 */ 75 C_12, /* Control reg. starting at position 12 */ 76 B_16, /* Base register starting at position 16 */ 77 B_32, /* Base register starting at position 32 */ 78 X_12, /* Index register starting at position 12 */ 79 D_20, /* Displacement starting at position 20 */ 80 D_36, /* Displacement starting at position 36 */ 81 D20_20, /* 20 bit displacement starting at 20 */ 82 L4_8, /* 4 bit length starting at position 8 */ 83 L4_12, /* 4 bit length starting at position 12 */ 84 L8_8, /* 8 bit length starting at position 8 */ 85 U4_8, /* 4 bit unsigned value starting at 8 */ 86 U4_12, /* 4 bit unsigned value starting at 12 */ 87 U4_16, /* 4 bit unsigned value starting at 16 */ 88 U4_20, /* 4 bit unsigned value starting at 20 */ 89 U4_32, /* 4 bit unsigned value starting at 32 */ 90 U8_8, /* 8 bit unsigned value starting at 8 */ 91 U8_16, /* 8 bit unsigned value starting at 16 */ 92 U8_24, /* 8 bit unsigned value starting at 24 */ 93 U8_32, /* 8 bit unsigned value starting at 32 */ 94 I8_8, /* 8 bit signed value starting at 8 */ 95 I8_32, /* 8 bit signed value starting at 32 */ 96 I16_16, /* 16 bit signed value starting at 16 */ 97 I16_32, /* 32 bit signed value starting at 16 */ 98 U16_16, /* 16 bit unsigned value starting at 16 */ 99 U16_32, /* 32 bit unsigned value starting at 16 */ 100 J16_16, /* PC relative jump offset at 16 */ 101 J32_16, /* PC relative long offset at 16 */ 102 I32_16, /* 32 bit signed value starting at 16 */ 103 U32_16, /* 32 bit unsigned value starting at 16 */ 104 M_16, /* 4 bit optional mask starting at 16 */ 105 RO_28, /* optional GPR starting at position 28 */ 106 }; 107 108 /* 109 * Enumeration of the different instruction formats. 110 * For details consult the principles of operation. 111 */ 112 enum { 113 INSTR_INVALID, 114 INSTR_E, 115 INSTR_RIE_R0IU, INSTR_RIE_R0UU, INSTR_RIE_RRP, INSTR_RIE_RRPU, 116 INSTR_RIE_RRUUU, INSTR_RIE_RUPI, INSTR_RIE_RUPU, 117 INSTR_RIL_RI, INSTR_RIL_RP, INSTR_RIL_RU, INSTR_RIL_UP, 118 INSTR_RIS_R0RDU, INSTR_RIS_R0UU, INSTR_RIS_RURDI, INSTR_RIS_RURDU, 119 INSTR_RI_RI, INSTR_RI_RP, INSTR_RI_RU, INSTR_RI_UP, 120 INSTR_RRE_00, INSTR_RRE_0R, INSTR_RRE_AA, INSTR_RRE_AR, INSTR_RRE_F0, 121 INSTR_RRE_FF, INSTR_RRE_FR, INSTR_RRE_R0, INSTR_RRE_RA, INSTR_RRE_RF, 122 INSTR_RRE_RR, INSTR_RRE_RR_OPT, 123 INSTR_RRF_0UFF, INSTR_RRF_F0FF, INSTR_RRF_F0FF2, INSTR_RRF_F0FR, 124 INSTR_RRF_FFRU, INSTR_RRF_FUFF, INSTR_RRF_M0RR, INSTR_RRF_R0RR, 125 INSTR_RRF_RURR, INSTR_RRF_U0FF, INSTR_RRF_U0RF, INSTR_RRF_U0RR, 126 INSTR_RRF_UUFF, INSTR_RRR_F0FF, INSTR_RRS_RRRDU, 127 INSTR_RR_FF, INSTR_RR_R0, INSTR_RR_RR, INSTR_RR_U0, INSTR_RR_UR, 128 INSTR_RSE_CCRD, INSTR_RSE_RRRD, INSTR_RSE_RURD, 129 INSTR_RSI_RRP, 130 INSTR_RSL_R0RD, 131 INSTR_RSY_AARD, INSTR_RSY_CCRD, INSTR_RSY_RRRD, INSTR_RSY_RURD, 132 INSTR_RS_AARD, INSTR_RS_CCRD, INSTR_RS_R0RD, INSTR_RS_RRRD, 133 INSTR_RS_RURD, 134 INSTR_RXE_FRRD, INSTR_RXE_RRRD, 135 INSTR_RXF_FRRDF, 136 INSTR_RXY_FRRD, INSTR_RXY_RRRD, INSTR_RXY_URRD, 137 INSTR_RX_FRRD, INSTR_RX_RRRD, INSTR_RX_URRD, 138 INSTR_SIL_RDI, INSTR_SIL_RDU, 139 INSTR_SIY_IRD, INSTR_SIY_URD, 140 INSTR_SI_URD, 141 INSTR_SSE_RDRD, 142 INSTR_SSF_RRDRD, 143 INSTR_SS_L0RDRD, INSTR_SS_LIRDRD, INSTR_SS_LLRDRD, INSTR_SS_RRRDRD, 144 INSTR_SS_RRRDRD2, INSTR_SS_RRRDRD3, 145 INSTR_S_00, INSTR_S_RD, 146 }; 147 148 struct operand { 149 int bits; /* The number of bits in the operand. */ 150 int shift; /* The number of bits to shift. */ 151 int flags; /* One bit syntax flags. */ 152 }; 153 154 struct insn { 155 const char name[6]; 156 unsigned char opfrag; 157 unsigned char format; 158 }; 159 160 static const struct operand operands[] = 161 { 162 [UNUSED] = { 0, 0, 0 }, 163 [R_8] = { 4, 8, OPERAND_GPR }, 164 [R_12] = { 4, 12, OPERAND_GPR }, 165 [R_16] = { 4, 16, OPERAND_GPR }, 166 [R_20] = { 4, 20, OPERAND_GPR }, 167 [R_24] = { 4, 24, OPERAND_GPR }, 168 [R_28] = { 4, 28, OPERAND_GPR }, 169 [R_32] = { 4, 32, OPERAND_GPR }, 170 [F_8] = { 4, 8, OPERAND_FPR }, 171 [F_12] = { 4, 12, OPERAND_FPR }, 172 [F_16] = { 4, 16, OPERAND_FPR }, 173 [F_20] = { 4, 16, OPERAND_FPR }, 174 [F_24] = { 4, 24, OPERAND_FPR }, 175 [F_28] = { 4, 28, OPERAND_FPR }, 176 [F_32] = { 4, 32, OPERAND_FPR }, 177 [A_8] = { 4, 8, OPERAND_AR }, 178 [A_12] = { 4, 12, OPERAND_AR }, 179 [A_24] = { 4, 24, OPERAND_AR }, 180 [A_28] = { 4, 28, OPERAND_AR }, 181 [C_8] = { 4, 8, OPERAND_CR }, 182 [C_12] = { 4, 12, OPERAND_CR }, 183 [B_16] = { 4, 16, OPERAND_BASE | OPERAND_GPR }, 184 [B_32] = { 4, 32, OPERAND_BASE | OPERAND_GPR }, 185 [X_12] = { 4, 12, OPERAND_INDEX | OPERAND_GPR }, 186 [D_20] = { 12, 20, OPERAND_DISP }, 187 [D_36] = { 12, 36, OPERAND_DISP }, 188 [D20_20] = { 20, 20, OPERAND_DISP | OPERAND_SIGNED }, 189 [L4_8] = { 4, 8, OPERAND_LENGTH }, 190 [L4_12] = { 4, 12, OPERAND_LENGTH }, 191 [L8_8] = { 8, 8, OPERAND_LENGTH }, 192 [U4_8] = { 4, 8, 0 }, 193 [U4_12] = { 4, 12, 0 }, 194 [U4_16] = { 4, 16, 0 }, 195 [U4_20] = { 4, 20, 0 }, 196 [U4_32] = { 4, 32, 0 }, 197 [U8_8] = { 8, 8, 0 }, 198 [U8_16] = { 8, 16, 0 }, 199 [U8_24] = { 8, 24, 0 }, 200 [U8_32] = { 8, 32, 0 }, 201 [I16_16] = { 16, 16, OPERAND_SIGNED }, 202 [U16_16] = { 16, 16, 0 }, 203 [U16_32] = { 16, 32, 0 }, 204 [J16_16] = { 16, 16, OPERAND_PCREL }, 205 [I16_32] = { 16, 32, OPERAND_SIGNED }, 206 [J32_16] = { 32, 16, OPERAND_PCREL }, 207 [I32_16] = { 32, 16, OPERAND_SIGNED }, 208 [U32_16] = { 32, 16, 0 }, 209 [M_16] = { 4, 16, 0 }, 210 [RO_28] = { 4, 28, OPERAND_GPR } 211 }; 212 213 static const unsigned char formats[][7] = { 214 [INSTR_E] = { 0xff, 0,0,0,0,0,0 }, 215 [INSTR_RIE_R0UU] = { 0xff, R_8,U16_16,U4_32,0,0,0 }, 216 [INSTR_RIE_RRPU] = { 0xff, R_8,R_12,U4_32,J16_16,0,0 }, 217 [INSTR_RIE_RRP] = { 0xff, R_8,R_12,J16_16,0,0,0 }, 218 [INSTR_RIE_RRUUU] = { 0xff, R_8,R_12,U8_16,U8_24,U8_32,0 }, 219 [INSTR_RIE_RUPI] = { 0xff, R_8,I8_32,U4_12,J16_16,0,0 }, 220 [INSTR_RIL_RI] = { 0x0f, R_8,I32_16,0,0,0,0 }, 221 [INSTR_RIL_RP] = { 0x0f, R_8,J32_16,0,0,0,0 }, 222 [INSTR_RIL_RU] = { 0x0f, R_8,U32_16,0,0,0,0 }, 223 [INSTR_RIL_UP] = { 0x0f, U4_8,J32_16,0,0,0,0 }, 224 [INSTR_RIS_R0RDU] = { 0xff, R_8,U8_32,D_20,B_16,0,0 }, 225 [INSTR_RIS_RURDI] = { 0xff, R_8,I8_32,U4_12,D_20,B_16,0 }, 226 [INSTR_RIS_RURDU] = { 0xff, R_8,U8_32,U4_12,D_20,B_16,0 }, 227 [INSTR_RI_RI] = { 0x0f, R_8,I16_16,0,0,0,0 }, 228 [INSTR_RI_RP] = { 0x0f, R_8,J16_16,0,0,0,0 }, 229 [INSTR_RI_RU] = { 0x0f, R_8,U16_16,0,0,0,0 }, 230 [INSTR_RI_UP] = { 0x0f, U4_8,J16_16,0,0,0,0 }, 231 [INSTR_RRE_00] = { 0xff, 0,0,0,0,0,0 }, 232 [INSTR_RRE_0R] = { 0xff, R_28,0,0,0,0,0 }, 233 [INSTR_RRE_AA] = { 0xff, A_24,A_28,0,0,0,0 }, 234 [INSTR_RRE_AR] = { 0xff, A_24,R_28,0,0,0,0 }, 235 [INSTR_RRE_F0] = { 0xff, F_24,0,0,0,0,0 }, 236 [INSTR_RRE_FF] = { 0xff, F_24,F_28,0,0,0,0 }, 237 [INSTR_RRE_FR] = { 0xff, F_24,R_28,0,0,0,0 }, 238 [INSTR_RRE_R0] = { 0xff, R_24,0,0,0,0,0 }, 239 [INSTR_RRE_RA] = { 0xff, R_24,A_28,0,0,0,0 }, 240 [INSTR_RRE_RF] = { 0xff, R_24,F_28,0,0,0,0 }, 241 [INSTR_RRE_RR] = { 0xff, R_24,R_28,0,0,0,0 }, 242 [INSTR_RRE_RR_OPT]= { 0xff, R_24,RO_28,0,0,0,0 }, 243 [INSTR_RRF_0UFF] = { 0xff, F_24,F_28,U4_20,0,0,0 }, 244 [INSTR_RRF_F0FF2] = { 0xff, F_24,F_16,F_28,0,0,0 }, 245 [INSTR_RRF_F0FF] = { 0xff, F_16,F_24,F_28,0,0,0 }, 246 [INSTR_RRF_F0FR] = { 0xff, F_24,F_16,R_28,0,0,0 }, 247 [INSTR_RRF_FFRU] = { 0xff, F_24,F_16,R_28,U4_20,0,0 }, 248 [INSTR_RRF_FUFF] = { 0xff, F_24,F_16,F_28,U4_20,0,0 }, 249 [INSTR_RRF_M0RR] = { 0xff, R_24,R_28,M_16,0,0,0 }, 250 [INSTR_RRF_R0RR] = { 0xff, R_24,R_16,R_28,0,0,0 }, 251 [INSTR_RRF_RURR] = { 0xff, R_24,R_28,R_16,U4_20,0,0 }, 252 [INSTR_RRF_U0FF] = { 0xff, F_24,U4_16,F_28,0,0,0 }, 253 [INSTR_RRF_U0RF] = { 0xff, R_24,U4_16,F_28,0,0,0 }, 254 [INSTR_RRF_U0RR] = { 0xff, R_24,R_28,U4_16,0,0,0 }, 255 [INSTR_RRF_UUFF] = { 0xff, F_24,U4_16,F_28,U4_20,0,0 }, 256 [INSTR_RRR_F0FF] = { 0xff, F_24,F_28,F_16,0,0,0 }, 257 [INSTR_RRS_RRRDU] = { 0xff, R_8,R_12,U4_32,D_20,B_16,0 }, 258 [INSTR_RR_FF] = { 0xff, F_8,F_12,0,0,0,0 }, 259 [INSTR_RR_R0] = { 0xff, R_8, 0,0,0,0,0 }, 260 [INSTR_RR_RR] = { 0xff, R_8,R_12,0,0,0,0 }, 261 [INSTR_RR_U0] = { 0xff, U8_8, 0,0,0,0,0 }, 262 [INSTR_RR_UR] = { 0xff, U4_8,R_12,0,0,0,0 }, 263 [INSTR_RSE_CCRD] = { 0xff, C_8,C_12,D_20,B_16,0,0 }, 264 [INSTR_RSE_RRRD] = { 0xff, R_8,R_12,D_20,B_16,0,0 }, 265 [INSTR_RSE_RURD] = { 0xff, R_8,U4_12,D_20,B_16,0,0 }, 266 [INSTR_RSI_RRP] = { 0xff, R_8,R_12,J16_16,0,0,0 }, 267 [INSTR_RSL_R0RD] = { 0xff, D_20,L4_8,B_16,0,0,0 }, 268 [INSTR_RSY_AARD] = { 0xff, A_8,A_12,D20_20,B_16,0,0 }, 269 [INSTR_RSY_CCRD] = { 0xff, C_8,C_12,D20_20,B_16,0,0 }, 270 [INSTR_RSY_RRRD] = { 0xff, R_8,R_12,D20_20,B_16,0,0 }, 271 [INSTR_RSY_RURD] = { 0xff, R_8,U4_12,D20_20,B_16,0,0 }, 272 [INSTR_RS_AARD] = { 0xff, A_8,A_12,D_20,B_16,0,0 }, 273 [INSTR_RS_CCRD] = { 0xff, C_8,C_12,D_20,B_16,0,0 }, 274 [INSTR_RS_R0RD] = { 0xff, R_8,D_20,B_16,0,0,0 }, 275 [INSTR_RS_RRRD] = { 0xff, R_8,R_12,D_20,B_16,0,0 }, 276 [INSTR_RS_RURD] = { 0xff, R_8,U4_12,D_20,B_16,0,0 }, 277 [INSTR_RXE_FRRD] = { 0xff, F_8,D_20,X_12,B_16,0,0 }, 278 [INSTR_RXE_RRRD] = { 0xff, R_8,D_20,X_12,B_16,0,0 }, 279 [INSTR_RXF_FRRDF] = { 0xff, F_32,F_8,D_20,X_12,B_16,0 }, 280 [INSTR_RXY_FRRD] = { 0xff, F_8,D20_20,X_12,B_16,0,0 }, 281 [INSTR_RXY_RRRD] = { 0xff, R_8,D20_20,X_12,B_16,0,0 }, 282 [INSTR_RXY_URRD] = { 0xff, U4_8,D20_20,X_12,B_16,0,0 }, 283 [INSTR_RX_FRRD] = { 0xff, F_8,D_20,X_12,B_16,0,0 }, 284 [INSTR_RX_RRRD] = { 0xff, R_8,D_20,X_12,B_16,0,0 }, 285 [INSTR_RX_URRD] = { 0xff, U4_8,D_20,X_12,B_16,0,0 }, 286 [INSTR_SIL_RDI] = { 0xff, D_20,B_16,I16_32,0,0,0 }, 287 [INSTR_SIL_RDU] = { 0xff, D_20,B_16,U16_32,0,0,0 }, 288 [INSTR_SIY_IRD] = { 0xff, D20_20,B_16,I8_8,0,0,0 }, 289 [INSTR_SIY_URD] = { 0xff, D20_20,B_16,U8_8,0,0,0 }, 290 [INSTR_SI_URD] = { 0xff, D_20,B_16,U8_8,0,0,0 }, 291 [INSTR_SSE_RDRD] = { 0xff, D_20,B_16,D_36,B_32,0,0 }, 292 [INSTR_SSF_RRDRD] = { 0x00, D_20,B_16,D_36,B_32,R_8,0 }, 293 [INSTR_SS_L0RDRD] = { 0xff, D_20,L8_8,B_16,D_36,B_32,0 }, 294 [INSTR_SS_LIRDRD] = { 0xff, D_20,L4_8,B_16,D_36,B_32,U4_12 }, 295 [INSTR_SS_LLRDRD] = { 0xff, D_20,L4_8,B_16,D_36,L4_12,B_32 }, 296 [INSTR_SS_RRRDRD2]= { 0xff, R_8,D_20,B_16,R_12,D_36,B_32 }, 297 [INSTR_SS_RRRDRD3]= { 0xff, R_8,R_12,D_20,B_16,D_36,B_32 }, 298 [INSTR_SS_RRRDRD] = { 0xff, D_20,R_8,B_16,D_36,B_32,R_12 }, 299 [INSTR_S_00] = { 0xff, 0,0,0,0,0,0 }, 300 [INSTR_S_RD] = { 0xff, D_20,B_16,0,0,0,0 }, 301 }; 302 303 static struct insn opcode[] = { 304 #ifdef CONFIG_64BIT 305 { "lmd", 0xef, INSTR_SS_RRRDRD3 }, 306 #endif 307 { "spm", 0x04, INSTR_RR_R0 }, 308 { "balr", 0x05, INSTR_RR_RR }, 309 { "bctr", 0x06, INSTR_RR_RR }, 310 { "bcr", 0x07, INSTR_RR_UR }, 311 { "svc", 0x0a, INSTR_RR_U0 }, 312 { "bsm", 0x0b, INSTR_RR_RR }, 313 { "bassm", 0x0c, INSTR_RR_RR }, 314 { "basr", 0x0d, INSTR_RR_RR }, 315 { "mvcl", 0x0e, INSTR_RR_RR }, 316 { "clcl", 0x0f, INSTR_RR_RR }, 317 { "lpr", 0x10, INSTR_RR_RR }, 318 { "lnr", 0x11, INSTR_RR_RR }, 319 { "ltr", 0x12, INSTR_RR_RR }, 320 { "lcr", 0x13, INSTR_RR_RR }, 321 { "nr", 0x14, INSTR_RR_RR }, 322 { "clr", 0x15, INSTR_RR_RR }, 323 { "or", 0x16, INSTR_RR_RR }, 324 { "xr", 0x17, INSTR_RR_RR }, 325 { "lr", 0x18, INSTR_RR_RR }, 326 { "cr", 0x19, INSTR_RR_RR }, 327 { "ar", 0x1a, INSTR_RR_RR }, 328 { "sr", 0x1b, INSTR_RR_RR }, 329 { "mr", 0x1c, INSTR_RR_RR }, 330 { "dr", 0x1d, INSTR_RR_RR }, 331 { "alr", 0x1e, INSTR_RR_RR }, 332 { "slr", 0x1f, INSTR_RR_RR }, 333 { "lpdr", 0x20, INSTR_RR_FF }, 334 { "lndr", 0x21, INSTR_RR_FF }, 335 { "ltdr", 0x22, INSTR_RR_FF }, 336 { "lcdr", 0x23, INSTR_RR_FF }, 337 { "hdr", 0x24, INSTR_RR_FF }, 338 { "ldxr", 0x25, INSTR_RR_FF }, 339 { "lrdr", 0x25, INSTR_RR_FF }, 340 { "mxr", 0x26, INSTR_RR_FF }, 341 { "mxdr", 0x27, INSTR_RR_FF }, 342 { "ldr", 0x28, INSTR_RR_FF }, 343 { "cdr", 0x29, INSTR_RR_FF }, 344 { "adr", 0x2a, INSTR_RR_FF }, 345 { "sdr", 0x2b, INSTR_RR_FF }, 346 { "mdr", 0x2c, INSTR_RR_FF }, 347 { "ddr", 0x2d, INSTR_RR_FF }, 348 { "awr", 0x2e, INSTR_RR_FF }, 349 { "swr", 0x2f, INSTR_RR_FF }, 350 { "lper", 0x30, INSTR_RR_FF }, 351 { "lner", 0x31, INSTR_RR_FF }, 352 { "lter", 0x32, INSTR_RR_FF }, 353 { "lcer", 0x33, INSTR_RR_FF }, 354 { "her", 0x34, INSTR_RR_FF }, 355 { "ledr", 0x35, INSTR_RR_FF }, 356 { "lrer", 0x35, INSTR_RR_FF }, 357 { "axr", 0x36, INSTR_RR_FF }, 358 { "sxr", 0x37, INSTR_RR_FF }, 359 { "ler", 0x38, INSTR_RR_FF }, 360 { "cer", 0x39, INSTR_RR_FF }, 361 { "aer", 0x3a, INSTR_RR_FF }, 362 { "ser", 0x3b, INSTR_RR_FF }, 363 { "mder", 0x3c, INSTR_RR_FF }, 364 { "mer", 0x3c, INSTR_RR_FF }, 365 { "der", 0x3d, INSTR_RR_FF }, 366 { "aur", 0x3e, INSTR_RR_FF }, 367 { "sur", 0x3f, INSTR_RR_FF }, 368 { "sth", 0x40, INSTR_RX_RRRD }, 369 { "la", 0x41, INSTR_RX_RRRD }, 370 { "stc", 0x42, INSTR_RX_RRRD }, 371 { "ic", 0x43, INSTR_RX_RRRD }, 372 { "ex", 0x44, INSTR_RX_RRRD }, 373 { "bal", 0x45, INSTR_RX_RRRD }, 374 { "bct", 0x46, INSTR_RX_RRRD }, 375 { "bc", 0x47, INSTR_RX_URRD }, 376 { "lh", 0x48, INSTR_RX_RRRD }, 377 { "ch", 0x49, INSTR_RX_RRRD }, 378 { "ah", 0x4a, INSTR_RX_RRRD }, 379 { "sh", 0x4b, INSTR_RX_RRRD }, 380 { "mh", 0x4c, INSTR_RX_RRRD }, 381 { "bas", 0x4d, INSTR_RX_RRRD }, 382 { "cvd", 0x4e, INSTR_RX_RRRD }, 383 { "cvb", 0x4f, INSTR_RX_RRRD }, 384 { "st", 0x50, INSTR_RX_RRRD }, 385 { "lae", 0x51, INSTR_RX_RRRD }, 386 { "n", 0x54, INSTR_RX_RRRD }, 387 { "cl", 0x55, INSTR_RX_RRRD }, 388 { "o", 0x56, INSTR_RX_RRRD }, 389 { "x", 0x57, INSTR_RX_RRRD }, 390 { "l", 0x58, INSTR_RX_RRRD }, 391 { "c", 0x59, INSTR_RX_RRRD }, 392 { "a", 0x5a, INSTR_RX_RRRD }, 393 { "s", 0x5b, INSTR_RX_RRRD }, 394 { "m", 0x5c, INSTR_RX_RRRD }, 395 { "d", 0x5d, INSTR_RX_RRRD }, 396 { "al", 0x5e, INSTR_RX_RRRD }, 397 { "sl", 0x5f, INSTR_RX_RRRD }, 398 { "std", 0x60, INSTR_RX_FRRD }, 399 { "mxd", 0x67, INSTR_RX_FRRD }, 400 { "ld", 0x68, INSTR_RX_FRRD }, 401 { "cd", 0x69, INSTR_RX_FRRD }, 402 { "ad", 0x6a, INSTR_RX_FRRD }, 403 { "sd", 0x6b, INSTR_RX_FRRD }, 404 { "md", 0x6c, INSTR_RX_FRRD }, 405 { "dd", 0x6d, INSTR_RX_FRRD }, 406 { "aw", 0x6e, INSTR_RX_FRRD }, 407 { "sw", 0x6f, INSTR_RX_FRRD }, 408 { "ste", 0x70, INSTR_RX_FRRD }, 409 { "ms", 0x71, INSTR_RX_RRRD }, 410 { "le", 0x78, INSTR_RX_FRRD }, 411 { "ce", 0x79, INSTR_RX_FRRD }, 412 { "ae", 0x7a, INSTR_RX_FRRD }, 413 { "se", 0x7b, INSTR_RX_FRRD }, 414 { "mde", 0x7c, INSTR_RX_FRRD }, 415 { "me", 0x7c, INSTR_RX_FRRD }, 416 { "de", 0x7d, INSTR_RX_FRRD }, 417 { "au", 0x7e, INSTR_RX_FRRD }, 418 { "su", 0x7f, INSTR_RX_FRRD }, 419 { "ssm", 0x80, INSTR_S_RD }, 420 { "lpsw", 0x82, INSTR_S_RD }, 421 { "diag", 0x83, INSTR_RS_RRRD }, 422 { "brxh", 0x84, INSTR_RSI_RRP }, 423 { "brxle", 0x85, INSTR_RSI_RRP }, 424 { "bxh", 0x86, INSTR_RS_RRRD }, 425 { "bxle", 0x87, INSTR_RS_RRRD }, 426 { "srl", 0x88, INSTR_RS_R0RD }, 427 { "sll", 0x89, INSTR_RS_R0RD }, 428 { "sra", 0x8a, INSTR_RS_R0RD }, 429 { "sla", 0x8b, INSTR_RS_R0RD }, 430 { "srdl", 0x8c, INSTR_RS_R0RD }, 431 { "sldl", 0x8d, INSTR_RS_R0RD }, 432 { "srda", 0x8e, INSTR_RS_R0RD }, 433 { "slda", 0x8f, INSTR_RS_R0RD }, 434 { "stm", 0x90, INSTR_RS_RRRD }, 435 { "tm", 0x91, INSTR_SI_URD }, 436 { "mvi", 0x92, INSTR_SI_URD }, 437 { "ts", 0x93, INSTR_S_RD }, 438 { "ni", 0x94, INSTR_SI_URD }, 439 { "cli", 0x95, INSTR_SI_URD }, 440 { "oi", 0x96, INSTR_SI_URD }, 441 { "xi", 0x97, INSTR_SI_URD }, 442 { "lm", 0x98, INSTR_RS_RRRD }, 443 { "trace", 0x99, INSTR_RS_RRRD }, 444 { "lam", 0x9a, INSTR_RS_AARD }, 445 { "stam", 0x9b, INSTR_RS_AARD }, 446 { "mvcle", 0xa8, INSTR_RS_RRRD }, 447 { "clcle", 0xa9, INSTR_RS_RRRD }, 448 { "stnsm", 0xac, INSTR_SI_URD }, 449 { "stosm", 0xad, INSTR_SI_URD }, 450 { "sigp", 0xae, INSTR_RS_RRRD }, 451 { "mc", 0xaf, INSTR_SI_URD }, 452 { "lra", 0xb1, INSTR_RX_RRRD }, 453 { "stctl", 0xb6, INSTR_RS_CCRD }, 454 { "lctl", 0xb7, INSTR_RS_CCRD }, 455 { "cs", 0xba, INSTR_RS_RRRD }, 456 { "cds", 0xbb, INSTR_RS_RRRD }, 457 { "clm", 0xbd, INSTR_RS_RURD }, 458 { "stcm", 0xbe, INSTR_RS_RURD }, 459 { "icm", 0xbf, INSTR_RS_RURD }, 460 { "mvn", 0xd1, INSTR_SS_L0RDRD }, 461 { "mvc", 0xd2, INSTR_SS_L0RDRD }, 462 { "mvz", 0xd3, INSTR_SS_L0RDRD }, 463 { "nc", 0xd4, INSTR_SS_L0RDRD }, 464 { "clc", 0xd5, INSTR_SS_L0RDRD }, 465 { "oc", 0xd6, INSTR_SS_L0RDRD }, 466 { "xc", 0xd7, INSTR_SS_L0RDRD }, 467 { "mvck", 0xd9, INSTR_SS_RRRDRD }, 468 { "mvcp", 0xda, INSTR_SS_RRRDRD }, 469 { "mvcs", 0xdb, INSTR_SS_RRRDRD }, 470 { "tr", 0xdc, INSTR_SS_L0RDRD }, 471 { "trt", 0xdd, INSTR_SS_L0RDRD }, 472 { "ed", 0xde, INSTR_SS_L0RDRD }, 473 { "edmk", 0xdf, INSTR_SS_L0RDRD }, 474 { "pku", 0xe1, INSTR_SS_L0RDRD }, 475 { "unpku", 0xe2, INSTR_SS_L0RDRD }, 476 { "mvcin", 0xe8, INSTR_SS_L0RDRD }, 477 { "pka", 0xe9, INSTR_SS_L0RDRD }, 478 { "unpka", 0xea, INSTR_SS_L0RDRD }, 479 { "plo", 0xee, INSTR_SS_RRRDRD2 }, 480 { "srp", 0xf0, INSTR_SS_LIRDRD }, 481 { "mvo", 0xf1, INSTR_SS_LLRDRD }, 482 { "pack", 0xf2, INSTR_SS_LLRDRD }, 483 { "unpk", 0xf3, INSTR_SS_LLRDRD }, 484 { "zap", 0xf8, INSTR_SS_LLRDRD }, 485 { "cp", 0xf9, INSTR_SS_LLRDRD }, 486 { "ap", 0xfa, INSTR_SS_LLRDRD }, 487 { "sp", 0xfb, INSTR_SS_LLRDRD }, 488 { "mp", 0xfc, INSTR_SS_LLRDRD }, 489 { "dp", 0xfd, INSTR_SS_LLRDRD }, 490 { "", 0, INSTR_INVALID } 491 }; 492 493 static struct insn opcode_01[] = { 494 #ifdef CONFIG_64BIT 495 { "sam64", 0x0e, INSTR_E }, 496 { "pfpo", 0x0a, INSTR_E }, 497 { "ptff", 0x04, INSTR_E }, 498 #endif 499 { "pr", 0x01, INSTR_E }, 500 { "upt", 0x02, INSTR_E }, 501 { "sckpf", 0x07, INSTR_E }, 502 { "tam", 0x0b, INSTR_E }, 503 { "sam24", 0x0c, INSTR_E }, 504 { "sam31", 0x0d, INSTR_E }, 505 { "trap2", 0xff, INSTR_E }, 506 { "", 0, INSTR_INVALID } 507 }; 508 509 static struct insn opcode_a5[] = { 510 #ifdef CONFIG_64BIT 511 { "iihh", 0x00, INSTR_RI_RU }, 512 { "iihl", 0x01, INSTR_RI_RU }, 513 { "iilh", 0x02, INSTR_RI_RU }, 514 { "iill", 0x03, INSTR_RI_RU }, 515 { "nihh", 0x04, INSTR_RI_RU }, 516 { "nihl", 0x05, INSTR_RI_RU }, 517 { "nilh", 0x06, INSTR_RI_RU }, 518 { "nill", 0x07, INSTR_RI_RU }, 519 { "oihh", 0x08, INSTR_RI_RU }, 520 { "oihl", 0x09, INSTR_RI_RU }, 521 { "oilh", 0x0a, INSTR_RI_RU }, 522 { "oill", 0x0b, INSTR_RI_RU }, 523 { "llihh", 0x0c, INSTR_RI_RU }, 524 { "llihl", 0x0d, INSTR_RI_RU }, 525 { "llilh", 0x0e, INSTR_RI_RU }, 526 { "llill", 0x0f, INSTR_RI_RU }, 527 #endif 528 { "", 0, INSTR_INVALID } 529 }; 530 531 static struct insn opcode_a7[] = { 532 #ifdef CONFIG_64BIT 533 { "tmhh", 0x02, INSTR_RI_RU }, 534 { "tmhl", 0x03, INSTR_RI_RU }, 535 { "brctg", 0x07, INSTR_RI_RP }, 536 { "lghi", 0x09, INSTR_RI_RI }, 537 { "aghi", 0x0b, INSTR_RI_RI }, 538 { "mghi", 0x0d, INSTR_RI_RI }, 539 { "cghi", 0x0f, INSTR_RI_RI }, 540 #endif 541 { "tmlh", 0x00, INSTR_RI_RU }, 542 { "tmll", 0x01, INSTR_RI_RU }, 543 { "brc", 0x04, INSTR_RI_UP }, 544 { "bras", 0x05, INSTR_RI_RP }, 545 { "brct", 0x06, INSTR_RI_RP }, 546 { "lhi", 0x08, INSTR_RI_RI }, 547 { "ahi", 0x0a, INSTR_RI_RI }, 548 { "mhi", 0x0c, INSTR_RI_RI }, 549 { "chi", 0x0e, INSTR_RI_RI }, 550 { "", 0, INSTR_INVALID } 551 }; 552 553 static struct insn opcode_b2[] = { 554 #ifdef CONFIG_64BIT 555 { "sske", 0x2b, INSTR_RRF_M0RR }, 556 { "stckf", 0x7c, INSTR_S_RD }, 557 { "cu21", 0xa6, INSTR_RRF_M0RR }, 558 { "cuutf", 0xa6, INSTR_RRF_M0RR }, 559 { "cu12", 0xa7, INSTR_RRF_M0RR }, 560 { "cutfu", 0xa7, INSTR_RRF_M0RR }, 561 { "stfle", 0xb0, INSTR_S_RD }, 562 { "lpswe", 0xb2, INSTR_S_RD }, 563 { "srnmt", 0xb9, INSTR_S_RD }, 564 { "lfas", 0xbd, INSTR_S_RD }, 565 #endif 566 { "stidp", 0x02, INSTR_S_RD }, 567 { "sck", 0x04, INSTR_S_RD }, 568 { "stck", 0x05, INSTR_S_RD }, 569 { "sckc", 0x06, INSTR_S_RD }, 570 { "stckc", 0x07, INSTR_S_RD }, 571 { "spt", 0x08, INSTR_S_RD }, 572 { "stpt", 0x09, INSTR_S_RD }, 573 { "spka", 0x0a, INSTR_S_RD }, 574 { "ipk", 0x0b, INSTR_S_00 }, 575 { "ptlb", 0x0d, INSTR_S_00 }, 576 { "spx", 0x10, INSTR_S_RD }, 577 { "stpx", 0x11, INSTR_S_RD }, 578 { "stap", 0x12, INSTR_S_RD }, 579 { "sie", 0x14, INSTR_S_RD }, 580 { "pc", 0x18, INSTR_S_RD }, 581 { "sac", 0x19, INSTR_S_RD }, 582 { "cfc", 0x1a, INSTR_S_RD }, 583 { "ipte", 0x21, INSTR_RRE_RR }, 584 { "ipm", 0x22, INSTR_RRE_R0 }, 585 { "ivsk", 0x23, INSTR_RRE_RR }, 586 { "iac", 0x24, INSTR_RRE_R0 }, 587 { "ssar", 0x25, INSTR_RRE_R0 }, 588 { "epar", 0x26, INSTR_RRE_R0 }, 589 { "esar", 0x27, INSTR_RRE_R0 }, 590 { "pt", 0x28, INSTR_RRE_RR }, 591 { "iske", 0x29, INSTR_RRE_RR }, 592 { "rrbe", 0x2a, INSTR_RRE_RR }, 593 { "sske", 0x2b, INSTR_RRE_RR }, 594 { "tb", 0x2c, INSTR_RRE_0R }, 595 { "dxr", 0x2d, INSTR_RRE_F0 }, 596 { "pgin", 0x2e, INSTR_RRE_RR }, 597 { "pgout", 0x2f, INSTR_RRE_RR }, 598 { "csch", 0x30, INSTR_S_00 }, 599 { "hsch", 0x31, INSTR_S_00 }, 600 { "msch", 0x32, INSTR_S_RD }, 601 { "ssch", 0x33, INSTR_S_RD }, 602 { "stsch", 0x34, INSTR_S_RD }, 603 { "tsch", 0x35, INSTR_S_RD }, 604 { "tpi", 0x36, INSTR_S_RD }, 605 { "sal", 0x37, INSTR_S_00 }, 606 { "rsch", 0x38, INSTR_S_00 }, 607 { "stcrw", 0x39, INSTR_S_RD }, 608 { "stcps", 0x3a, INSTR_S_RD }, 609 { "rchp", 0x3b, INSTR_S_00 }, 610 { "schm", 0x3c, INSTR_S_00 }, 611 { "bakr", 0x40, INSTR_RRE_RR }, 612 { "cksm", 0x41, INSTR_RRE_RR }, 613 { "sqdr", 0x44, INSTR_RRE_F0 }, 614 { "sqer", 0x45, INSTR_RRE_F0 }, 615 { "stura", 0x46, INSTR_RRE_RR }, 616 { "msta", 0x47, INSTR_RRE_R0 }, 617 { "palb", 0x48, INSTR_RRE_00 }, 618 { "ereg", 0x49, INSTR_RRE_RR }, 619 { "esta", 0x4a, INSTR_RRE_RR }, 620 { "lura", 0x4b, INSTR_RRE_RR }, 621 { "tar", 0x4c, INSTR_RRE_AR }, 622 { "cpya", 0x4d, INSTR_RRE_AA }, 623 { "sar", 0x4e, INSTR_RRE_AR }, 624 { "ear", 0x4f, INSTR_RRE_RA }, 625 { "csp", 0x50, INSTR_RRE_RR }, 626 { "msr", 0x52, INSTR_RRE_RR }, 627 { "mvpg", 0x54, INSTR_RRE_RR }, 628 { "mvst", 0x55, INSTR_RRE_RR }, 629 { "cuse", 0x57, INSTR_RRE_RR }, 630 { "bsg", 0x58, INSTR_RRE_RR }, 631 { "bsa", 0x5a, INSTR_RRE_RR }, 632 { "clst", 0x5d, INSTR_RRE_RR }, 633 { "srst", 0x5e, INSTR_RRE_RR }, 634 { "cmpsc", 0x63, INSTR_RRE_RR }, 635 { "siga", 0x74, INSTR_S_RD }, 636 { "xsch", 0x76, INSTR_S_00 }, 637 { "rp", 0x77, INSTR_S_RD }, 638 { "stcke", 0x78, INSTR_S_RD }, 639 { "sacf", 0x79, INSTR_S_RD }, 640 { "stsi", 0x7d, INSTR_S_RD }, 641 { "srnm", 0x99, INSTR_S_RD }, 642 { "stfpc", 0x9c, INSTR_S_RD }, 643 { "lfpc", 0x9d, INSTR_S_RD }, 644 { "tre", 0xa5, INSTR_RRE_RR }, 645 { "cuutf", 0xa6, INSTR_RRE_RR }, 646 { "cutfu", 0xa7, INSTR_RRE_RR }, 647 { "stfl", 0xb1, INSTR_S_RD }, 648 { "trap4", 0xff, INSTR_S_RD }, 649 { "", 0, INSTR_INVALID } 650 }; 651 652 static struct insn opcode_b3[] = { 653 #ifdef CONFIG_64BIT 654 { "maylr", 0x38, INSTR_RRF_F0FF }, 655 { "mylr", 0x39, INSTR_RRF_F0FF }, 656 { "mayr", 0x3a, INSTR_RRF_F0FF }, 657 { "myr", 0x3b, INSTR_RRF_F0FF }, 658 { "mayhr", 0x3c, INSTR_RRF_F0FF }, 659 { "myhr", 0x3d, INSTR_RRF_F0FF }, 660 { "cegbr", 0xa4, INSTR_RRE_RR }, 661 { "cdgbr", 0xa5, INSTR_RRE_RR }, 662 { "cxgbr", 0xa6, INSTR_RRE_RR }, 663 { "cgebr", 0xa8, INSTR_RRF_U0RF }, 664 { "cgdbr", 0xa9, INSTR_RRF_U0RF }, 665 { "cgxbr", 0xaa, INSTR_RRF_U0RF }, 666 { "cfer", 0xb8, INSTR_RRF_U0RF }, 667 { "cfdr", 0xb9, INSTR_RRF_U0RF }, 668 { "cfxr", 0xba, INSTR_RRF_U0RF }, 669 { "cegr", 0xc4, INSTR_RRE_RR }, 670 { "cdgr", 0xc5, INSTR_RRE_RR }, 671 { "cxgr", 0xc6, INSTR_RRE_RR }, 672 { "cger", 0xc8, INSTR_RRF_U0RF }, 673 { "cgdr", 0xc9, INSTR_RRF_U0RF }, 674 { "cgxr", 0xca, INSTR_RRF_U0RF }, 675 { "lpdfr", 0x70, INSTR_RRE_FF }, 676 { "lndfr", 0x71, INSTR_RRE_FF }, 677 { "cpsdr", 0x72, INSTR_RRF_F0FF2 }, 678 { "lcdfr", 0x73, INSTR_RRE_FF }, 679 { "ldgr", 0xc1, INSTR_RRE_FR }, 680 { "lgdr", 0xcd, INSTR_RRE_RF }, 681 { "adtr", 0xd2, INSTR_RRR_F0FF }, 682 { "axtr", 0xda, INSTR_RRR_F0FF }, 683 { "cdtr", 0xe4, INSTR_RRE_FF }, 684 { "cxtr", 0xec, INSTR_RRE_FF }, 685 { "kdtr", 0xe0, INSTR_RRE_FF }, 686 { "kxtr", 0xe8, INSTR_RRE_FF }, 687 { "cedtr", 0xf4, INSTR_RRE_FF }, 688 { "cextr", 0xfc, INSTR_RRE_FF }, 689 { "cdgtr", 0xf1, INSTR_RRE_FR }, 690 { "cxgtr", 0xf9, INSTR_RRE_FR }, 691 { "cdstr", 0xf3, INSTR_RRE_FR }, 692 { "cxstr", 0xfb, INSTR_RRE_FR }, 693 { "cdutr", 0xf2, INSTR_RRE_FR }, 694 { "cxutr", 0xfa, INSTR_RRE_FR }, 695 { "cgdtr", 0xe1, INSTR_RRF_U0RF }, 696 { "cgxtr", 0xe9, INSTR_RRF_U0RF }, 697 { "csdtr", 0xe3, INSTR_RRE_RF }, 698 { "csxtr", 0xeb, INSTR_RRE_RF }, 699 { "cudtr", 0xe2, INSTR_RRE_RF }, 700 { "cuxtr", 0xea, INSTR_RRE_RF }, 701 { "ddtr", 0xd1, INSTR_RRR_F0FF }, 702 { "dxtr", 0xd9, INSTR_RRR_F0FF }, 703 { "eedtr", 0xe5, INSTR_RRE_RF }, 704 { "eextr", 0xed, INSTR_RRE_RF }, 705 { "esdtr", 0xe7, INSTR_RRE_RF }, 706 { "esxtr", 0xef, INSTR_RRE_RF }, 707 { "iedtr", 0xf6, INSTR_RRF_F0FR }, 708 { "iextr", 0xfe, INSTR_RRF_F0FR }, 709 { "ltdtr", 0xd6, INSTR_RRE_FF }, 710 { "ltxtr", 0xde, INSTR_RRE_FF }, 711 { "fidtr", 0xd7, INSTR_RRF_UUFF }, 712 { "fixtr", 0xdf, INSTR_RRF_UUFF }, 713 { "ldetr", 0xd4, INSTR_RRF_0UFF }, 714 { "lxdtr", 0xdc, INSTR_RRF_0UFF }, 715 { "ledtr", 0xd5, INSTR_RRF_UUFF }, 716 { "ldxtr", 0xdd, INSTR_RRF_UUFF }, 717 { "mdtr", 0xd0, INSTR_RRR_F0FF }, 718 { "mxtr", 0xd8, INSTR_RRR_F0FF }, 719 { "qadtr", 0xf5, INSTR_RRF_FUFF }, 720 { "qaxtr", 0xfd, INSTR_RRF_FUFF }, 721 { "rrdtr", 0xf7, INSTR_RRF_FFRU }, 722 { "rrxtr", 0xff, INSTR_RRF_FFRU }, 723 { "sfasr", 0x85, INSTR_RRE_R0 }, 724 { "sdtr", 0xd3, INSTR_RRR_F0FF }, 725 { "sxtr", 0xdb, INSTR_RRR_F0FF }, 726 #endif 727 { "lpebr", 0x00, INSTR_RRE_FF }, 728 { "lnebr", 0x01, INSTR_RRE_FF }, 729 { "ltebr", 0x02, INSTR_RRE_FF }, 730 { "lcebr", 0x03, INSTR_RRE_FF }, 731 { "ldebr", 0x04, INSTR_RRE_FF }, 732 { "lxdbr", 0x05, INSTR_RRE_FF }, 733 { "lxebr", 0x06, INSTR_RRE_FF }, 734 { "mxdbr", 0x07, INSTR_RRE_FF }, 735 { "kebr", 0x08, INSTR_RRE_FF }, 736 { "cebr", 0x09, INSTR_RRE_FF }, 737 { "aebr", 0x0a, INSTR_RRE_FF }, 738 { "sebr", 0x0b, INSTR_RRE_FF }, 739 { "mdebr", 0x0c, INSTR_RRE_FF }, 740 { "debr", 0x0d, INSTR_RRE_FF }, 741 { "maebr", 0x0e, INSTR_RRF_F0FF }, 742 { "msebr", 0x0f, INSTR_RRF_F0FF }, 743 { "lpdbr", 0x10, INSTR_RRE_FF }, 744 { "lndbr", 0x11, INSTR_RRE_FF }, 745 { "ltdbr", 0x12, INSTR_RRE_FF }, 746 { "lcdbr", 0x13, INSTR_RRE_FF }, 747 { "sqebr", 0x14, INSTR_RRE_FF }, 748 { "sqdbr", 0x15, INSTR_RRE_FF }, 749 { "sqxbr", 0x16, INSTR_RRE_FF }, 750 { "meebr", 0x17, INSTR_RRE_FF }, 751 { "kdbr", 0x18, INSTR_RRE_FF }, 752 { "cdbr", 0x19, INSTR_RRE_FF }, 753 { "adbr", 0x1a, INSTR_RRE_FF }, 754 { "sdbr", 0x1b, INSTR_RRE_FF }, 755 { "mdbr", 0x1c, INSTR_RRE_FF }, 756 { "ddbr", 0x1d, INSTR_RRE_FF }, 757 { "madbr", 0x1e, INSTR_RRF_F0FF }, 758 { "msdbr", 0x1f, INSTR_RRF_F0FF }, 759 { "lder", 0x24, INSTR_RRE_FF }, 760 { "lxdr", 0x25, INSTR_RRE_FF }, 761 { "lxer", 0x26, INSTR_RRE_FF }, 762 { "maer", 0x2e, INSTR_RRF_F0FF }, 763 { "mser", 0x2f, INSTR_RRF_F0FF }, 764 { "sqxr", 0x36, INSTR_RRE_FF }, 765 { "meer", 0x37, INSTR_RRE_FF }, 766 { "madr", 0x3e, INSTR_RRF_F0FF }, 767 { "msdr", 0x3f, INSTR_RRF_F0FF }, 768 { "lpxbr", 0x40, INSTR_RRE_FF }, 769 { "lnxbr", 0x41, INSTR_RRE_FF }, 770 { "ltxbr", 0x42, INSTR_RRE_FF }, 771 { "lcxbr", 0x43, INSTR_RRE_FF }, 772 { "ledbr", 0x44, INSTR_RRE_FF }, 773 { "ldxbr", 0x45, INSTR_RRE_FF }, 774 { "lexbr", 0x46, INSTR_RRE_FF }, 775 { "fixbr", 0x47, INSTR_RRF_U0FF }, 776 { "kxbr", 0x48, INSTR_RRE_FF }, 777 { "cxbr", 0x49, INSTR_RRE_FF }, 778 { "axbr", 0x4a, INSTR_RRE_FF }, 779 { "sxbr", 0x4b, INSTR_RRE_FF }, 780 { "mxbr", 0x4c, INSTR_RRE_FF }, 781 { "dxbr", 0x4d, INSTR_RRE_FF }, 782 { "tbedr", 0x50, INSTR_RRF_U0FF }, 783 { "tbdr", 0x51, INSTR_RRF_U0FF }, 784 { "diebr", 0x53, INSTR_RRF_FUFF }, 785 { "fiebr", 0x57, INSTR_RRF_U0FF }, 786 { "thder", 0x58, INSTR_RRE_RR }, 787 { "thdr", 0x59, INSTR_RRE_RR }, 788 { "didbr", 0x5b, INSTR_RRF_FUFF }, 789 { "fidbr", 0x5f, INSTR_RRF_U0FF }, 790 { "lpxr", 0x60, INSTR_RRE_FF }, 791 { "lnxr", 0x61, INSTR_RRE_FF }, 792 { "ltxr", 0x62, INSTR_RRE_FF }, 793 { "lcxr", 0x63, INSTR_RRE_FF }, 794 { "lxr", 0x65, INSTR_RRE_RR }, 795 { "lexr", 0x66, INSTR_RRE_FF }, 796 { "fixr", 0x67, INSTR_RRF_U0FF }, 797 { "cxr", 0x69, INSTR_RRE_FF }, 798 { "lzer", 0x74, INSTR_RRE_R0 }, 799 { "lzdr", 0x75, INSTR_RRE_R0 }, 800 { "lzxr", 0x76, INSTR_RRE_R0 }, 801 { "fier", 0x77, INSTR_RRF_U0FF }, 802 { "fidr", 0x7f, INSTR_RRF_U0FF }, 803 { "sfpc", 0x84, INSTR_RRE_RR_OPT }, 804 { "efpc", 0x8c, INSTR_RRE_RR_OPT }, 805 { "cefbr", 0x94, INSTR_RRE_RF }, 806 { "cdfbr", 0x95, INSTR_RRE_RF }, 807 { "cxfbr", 0x96, INSTR_RRE_RF }, 808 { "cfebr", 0x98, INSTR_RRF_U0RF }, 809 { "cfdbr", 0x99, INSTR_RRF_U0RF }, 810 { "cfxbr", 0x9a, INSTR_RRF_U0RF }, 811 { "cefr", 0xb4, INSTR_RRE_RF }, 812 { "cdfr", 0xb5, INSTR_RRE_RF }, 813 { "cxfr", 0xb6, INSTR_RRE_RF }, 814 { "", 0, INSTR_INVALID } 815 }; 816 817 static struct insn opcode_b9[] = { 818 #ifdef CONFIG_64BIT 819 { "lpgr", 0x00, INSTR_RRE_RR }, 820 { "lngr", 0x01, INSTR_RRE_RR }, 821 { "ltgr", 0x02, INSTR_RRE_RR }, 822 { "lcgr", 0x03, INSTR_RRE_RR }, 823 { "lgr", 0x04, INSTR_RRE_RR }, 824 { "lurag", 0x05, INSTR_RRE_RR }, 825 { "lgbr", 0x06, INSTR_RRE_RR }, 826 { "lghr", 0x07, INSTR_RRE_RR }, 827 { "agr", 0x08, INSTR_RRE_RR }, 828 { "sgr", 0x09, INSTR_RRE_RR }, 829 { "algr", 0x0a, INSTR_RRE_RR }, 830 { "slgr", 0x0b, INSTR_RRE_RR }, 831 { "msgr", 0x0c, INSTR_RRE_RR }, 832 { "dsgr", 0x0d, INSTR_RRE_RR }, 833 { "eregg", 0x0e, INSTR_RRE_RR }, 834 { "lrvgr", 0x0f, INSTR_RRE_RR }, 835 { "lpgfr", 0x10, INSTR_RRE_RR }, 836 { "lngfr", 0x11, INSTR_RRE_RR }, 837 { "ltgfr", 0x12, INSTR_RRE_RR }, 838 { "lcgfr", 0x13, INSTR_RRE_RR }, 839 { "lgfr", 0x14, INSTR_RRE_RR }, 840 { "llgfr", 0x16, INSTR_RRE_RR }, 841 { "llgtr", 0x17, INSTR_RRE_RR }, 842 { "agfr", 0x18, INSTR_RRE_RR }, 843 { "sgfr", 0x19, INSTR_RRE_RR }, 844 { "algfr", 0x1a, INSTR_RRE_RR }, 845 { "slgfr", 0x1b, INSTR_RRE_RR }, 846 { "msgfr", 0x1c, INSTR_RRE_RR }, 847 { "dsgfr", 0x1d, INSTR_RRE_RR }, 848 { "cgr", 0x20, INSTR_RRE_RR }, 849 { "clgr", 0x21, INSTR_RRE_RR }, 850 { "sturg", 0x25, INSTR_RRE_RR }, 851 { "lbr", 0x26, INSTR_RRE_RR }, 852 { "lhr", 0x27, INSTR_RRE_RR }, 853 { "cgfr", 0x30, INSTR_RRE_RR }, 854 { "clgfr", 0x31, INSTR_RRE_RR }, 855 { "bctgr", 0x46, INSTR_RRE_RR }, 856 { "ngr", 0x80, INSTR_RRE_RR }, 857 { "ogr", 0x81, INSTR_RRE_RR }, 858 { "xgr", 0x82, INSTR_RRE_RR }, 859 { "flogr", 0x83, INSTR_RRE_RR }, 860 { "llgcr", 0x84, INSTR_RRE_RR }, 861 { "llghr", 0x85, INSTR_RRE_RR }, 862 { "mlgr", 0x86, INSTR_RRE_RR }, 863 { "dlgr", 0x87, INSTR_RRE_RR }, 864 { "alcgr", 0x88, INSTR_RRE_RR }, 865 { "slbgr", 0x89, INSTR_RRE_RR }, 866 { "cspg", 0x8a, INSTR_RRE_RR }, 867 { "idte", 0x8e, INSTR_RRF_R0RR }, 868 { "llcr", 0x94, INSTR_RRE_RR }, 869 { "llhr", 0x95, INSTR_RRE_RR }, 870 { "esea", 0x9d, INSTR_RRE_R0 }, 871 { "lptea", 0xaa, INSTR_RRF_RURR }, 872 { "cu14", 0xb0, INSTR_RRF_M0RR }, 873 { "cu24", 0xb1, INSTR_RRF_M0RR }, 874 { "cu41", 0xb2, INSTR_RRF_M0RR }, 875 { "cu42", 0xb3, INSTR_RRF_M0RR }, 876 { "crt", 0x72, INSTR_RRF_U0RR }, 877 { "cgrt", 0x60, INSTR_RRF_U0RR }, 878 { "clrt", 0x73, INSTR_RRF_U0RR }, 879 { "clgrt", 0x61, INSTR_RRF_U0RR }, 880 { "ptf", 0xa2, INSTR_RRE_R0 }, 881 { "pfmf", 0xaf, INSTR_RRE_RR }, 882 { "trte", 0xbf, INSTR_RRF_M0RR }, 883 { "trtre", 0xbd, INSTR_RRF_M0RR }, 884 #endif 885 { "kmac", 0x1e, INSTR_RRE_RR }, 886 { "lrvr", 0x1f, INSTR_RRE_RR }, 887 { "km", 0x2e, INSTR_RRE_RR }, 888 { "kmc", 0x2f, INSTR_RRE_RR }, 889 { "kimd", 0x3e, INSTR_RRE_RR }, 890 { "klmd", 0x3f, INSTR_RRE_RR }, 891 { "epsw", 0x8d, INSTR_RRE_RR }, 892 { "trtt", 0x90, INSTR_RRE_RR }, 893 { "trtt", 0x90, INSTR_RRF_M0RR }, 894 { "trto", 0x91, INSTR_RRE_RR }, 895 { "trto", 0x91, INSTR_RRF_M0RR }, 896 { "trot", 0x92, INSTR_RRE_RR }, 897 { "trot", 0x92, INSTR_RRF_M0RR }, 898 { "troo", 0x93, INSTR_RRE_RR }, 899 { "troo", 0x93, INSTR_RRF_M0RR }, 900 { "mlr", 0x96, INSTR_RRE_RR }, 901 { "dlr", 0x97, INSTR_RRE_RR }, 902 { "alcr", 0x98, INSTR_RRE_RR }, 903 { "slbr", 0x99, INSTR_RRE_RR }, 904 { "", 0, INSTR_INVALID } 905 }; 906 907 static struct insn opcode_c0[] = { 908 #ifdef CONFIG_64BIT 909 { "lgfi", 0x01, INSTR_RIL_RI }, 910 { "xihf", 0x06, INSTR_RIL_RU }, 911 { "xilf", 0x07, INSTR_RIL_RU }, 912 { "iihf", 0x08, INSTR_RIL_RU }, 913 { "iilf", 0x09, INSTR_RIL_RU }, 914 { "nihf", 0x0a, INSTR_RIL_RU }, 915 { "nilf", 0x0b, INSTR_RIL_RU }, 916 { "oihf", 0x0c, INSTR_RIL_RU }, 917 { "oilf", 0x0d, INSTR_RIL_RU }, 918 { "llihf", 0x0e, INSTR_RIL_RU }, 919 { "llilf", 0x0f, INSTR_RIL_RU }, 920 #endif 921 { "larl", 0x00, INSTR_RIL_RP }, 922 { "brcl", 0x04, INSTR_RIL_UP }, 923 { "brasl", 0x05, INSTR_RIL_RP }, 924 { "", 0, INSTR_INVALID } 925 }; 926 927 static struct insn opcode_c2[] = { 928 #ifdef CONFIG_64BIT 929 { "slgfi", 0x04, INSTR_RIL_RU }, 930 { "slfi", 0x05, INSTR_RIL_RU }, 931 { "agfi", 0x08, INSTR_RIL_RI }, 932 { "afi", 0x09, INSTR_RIL_RI }, 933 { "algfi", 0x0a, INSTR_RIL_RU }, 934 { "alfi", 0x0b, INSTR_RIL_RU }, 935 { "cgfi", 0x0c, INSTR_RIL_RI }, 936 { "cfi", 0x0d, INSTR_RIL_RI }, 937 { "clgfi", 0x0e, INSTR_RIL_RU }, 938 { "clfi", 0x0f, INSTR_RIL_RU }, 939 { "msfi", 0x01, INSTR_RIL_RI }, 940 { "msgfi", 0x00, INSTR_RIL_RI }, 941 #endif 942 { "", 0, INSTR_INVALID } 943 }; 944 945 static struct insn opcode_c4[] = { 946 #ifdef CONFIG_64BIT 947 { "lrl", 0x0d, INSTR_RIL_RP }, 948 { "lgrl", 0x08, INSTR_RIL_RP }, 949 { "lgfrl", 0x0c, INSTR_RIL_RP }, 950 { "lhrl", 0x05, INSTR_RIL_RP }, 951 { "lghrl", 0x04, INSTR_RIL_RP }, 952 { "llgfrl", 0x0e, INSTR_RIL_RP }, 953 { "llhrl", 0x02, INSTR_RIL_RP }, 954 { "llghrl", 0x06, INSTR_RIL_RP }, 955 { "strl", 0x0f, INSTR_RIL_RP }, 956 { "stgrl", 0x0b, INSTR_RIL_RP }, 957 { "sthrl", 0x07, INSTR_RIL_RP }, 958 #endif 959 { "", 0, INSTR_INVALID } 960 }; 961 962 static struct insn opcode_c6[] = { 963 #ifdef CONFIG_64BIT 964 { "crl", 0x0d, INSTR_RIL_RP }, 965 { "cgrl", 0x08, INSTR_RIL_RP }, 966 { "cgfrl", 0x0c, INSTR_RIL_RP }, 967 { "chrl", 0x05, INSTR_RIL_RP }, 968 { "cghrl", 0x04, INSTR_RIL_RP }, 969 { "clrl", 0x0f, INSTR_RIL_RP }, 970 { "clgrl", 0x0a, INSTR_RIL_RP }, 971 { "clgfrl", 0x0e, INSTR_RIL_RP }, 972 { "clhrl", 0x07, INSTR_RIL_RP }, 973 { "clghrl", 0x06, INSTR_RIL_RP }, 974 { "pfdrl", 0x02, INSTR_RIL_UP }, 975 { "exrl", 0x00, INSTR_RIL_RP }, 976 #endif 977 { "", 0, INSTR_INVALID } 978 }; 979 980 static struct insn opcode_c8[] = { 981 #ifdef CONFIG_64BIT 982 { "mvcos", 0x00, INSTR_SSF_RRDRD }, 983 { "ectg", 0x01, INSTR_SSF_RRDRD }, 984 { "csst", 0x02, INSTR_SSF_RRDRD }, 985 #endif 986 { "", 0, INSTR_INVALID } 987 }; 988 989 static struct insn opcode_e3[] = { 990 #ifdef CONFIG_64BIT 991 { "ltg", 0x02, INSTR_RXY_RRRD }, 992 { "lrag", 0x03, INSTR_RXY_RRRD }, 993 { "lg", 0x04, INSTR_RXY_RRRD }, 994 { "cvby", 0x06, INSTR_RXY_RRRD }, 995 { "ag", 0x08, INSTR_RXY_RRRD }, 996 { "sg", 0x09, INSTR_RXY_RRRD }, 997 { "alg", 0x0a, INSTR_RXY_RRRD }, 998 { "slg", 0x0b, INSTR_RXY_RRRD }, 999 { "msg", 0x0c, INSTR_RXY_RRRD }, 1000 { "dsg", 0x0d, INSTR_RXY_RRRD }, 1001 { "cvbg", 0x0e, INSTR_RXY_RRRD }, 1002 { "lrvg", 0x0f, INSTR_RXY_RRRD }, 1003 { "lt", 0x12, INSTR_RXY_RRRD }, 1004 { "lray", 0x13, INSTR_RXY_RRRD }, 1005 { "lgf", 0x14, INSTR_RXY_RRRD }, 1006 { "lgh", 0x15, INSTR_RXY_RRRD }, 1007 { "llgf", 0x16, INSTR_RXY_RRRD }, 1008 { "llgt", 0x17, INSTR_RXY_RRRD }, 1009 { "agf", 0x18, INSTR_RXY_RRRD }, 1010 { "sgf", 0x19, INSTR_RXY_RRRD }, 1011 { "algf", 0x1a, INSTR_RXY_RRRD }, 1012 { "slgf", 0x1b, INSTR_RXY_RRRD }, 1013 { "msgf", 0x1c, INSTR_RXY_RRRD }, 1014 { "dsgf", 0x1d, INSTR_RXY_RRRD }, 1015 { "cg", 0x20, INSTR_RXY_RRRD }, 1016 { "clg", 0x21, INSTR_RXY_RRRD }, 1017 { "stg", 0x24, INSTR_RXY_RRRD }, 1018 { "cvdy", 0x26, INSTR_RXY_RRRD }, 1019 { "cvdg", 0x2e, INSTR_RXY_RRRD }, 1020 { "strvg", 0x2f, INSTR_RXY_RRRD }, 1021 { "cgf", 0x30, INSTR_RXY_RRRD }, 1022 { "clgf", 0x31, INSTR_RXY_RRRD }, 1023 { "strvh", 0x3f, INSTR_RXY_RRRD }, 1024 { "bctg", 0x46, INSTR_RXY_RRRD }, 1025 { "sty", 0x50, INSTR_RXY_RRRD }, 1026 { "msy", 0x51, INSTR_RXY_RRRD }, 1027 { "ny", 0x54, INSTR_RXY_RRRD }, 1028 { "cly", 0x55, INSTR_RXY_RRRD }, 1029 { "oy", 0x56, INSTR_RXY_RRRD }, 1030 { "xy", 0x57, INSTR_RXY_RRRD }, 1031 { "ly", 0x58, INSTR_RXY_RRRD }, 1032 { "cy", 0x59, INSTR_RXY_RRRD }, 1033 { "ay", 0x5a, INSTR_RXY_RRRD }, 1034 { "sy", 0x5b, INSTR_RXY_RRRD }, 1035 { "aly", 0x5e, INSTR_RXY_RRRD }, 1036 { "sly", 0x5f, INSTR_RXY_RRRD }, 1037 { "sthy", 0x70, INSTR_RXY_RRRD }, 1038 { "lay", 0x71, INSTR_RXY_RRRD }, 1039 { "stcy", 0x72, INSTR_RXY_RRRD }, 1040 { "icy", 0x73, INSTR_RXY_RRRD }, 1041 { "lb", 0x76, INSTR_RXY_RRRD }, 1042 { "lgb", 0x77, INSTR_RXY_RRRD }, 1043 { "lhy", 0x78, INSTR_RXY_RRRD }, 1044 { "chy", 0x79, INSTR_RXY_RRRD }, 1045 { "ahy", 0x7a, INSTR_RXY_RRRD }, 1046 { "shy", 0x7b, INSTR_RXY_RRRD }, 1047 { "ng", 0x80, INSTR_RXY_RRRD }, 1048 { "og", 0x81, INSTR_RXY_RRRD }, 1049 { "xg", 0x82, INSTR_RXY_RRRD }, 1050 { "mlg", 0x86, INSTR_RXY_RRRD }, 1051 { "dlg", 0x87, INSTR_RXY_RRRD }, 1052 { "alcg", 0x88, INSTR_RXY_RRRD }, 1053 { "slbg", 0x89, INSTR_RXY_RRRD }, 1054 { "stpq", 0x8e, INSTR_RXY_RRRD }, 1055 { "lpq", 0x8f, INSTR_RXY_RRRD }, 1056 { "llgc", 0x90, INSTR_RXY_RRRD }, 1057 { "llgh", 0x91, INSTR_RXY_RRRD }, 1058 { "llc", 0x94, INSTR_RXY_RRRD }, 1059 { "llh", 0x95, INSTR_RXY_RRRD }, 1060 { "cgh", 0x34, INSTR_RXY_RRRD }, 1061 { "laey", 0x75, INSTR_RXY_RRRD }, 1062 { "ltgf", 0x32, INSTR_RXY_RRRD }, 1063 { "mfy", 0x5c, INSTR_RXY_RRRD }, 1064 { "mhy", 0x7c, INSTR_RXY_RRRD }, 1065 { "pfd", 0x36, INSTR_RXY_URRD }, 1066 #endif 1067 { "lrv", 0x1e, INSTR_RXY_RRRD }, 1068 { "lrvh", 0x1f, INSTR_RXY_RRRD }, 1069 { "strv", 0x3e, INSTR_RXY_RRRD }, 1070 { "ml", 0x96, INSTR_RXY_RRRD }, 1071 { "dl", 0x97, INSTR_RXY_RRRD }, 1072 { "alc", 0x98, INSTR_RXY_RRRD }, 1073 { "slb", 0x99, INSTR_RXY_RRRD }, 1074 { "", 0, INSTR_INVALID } 1075 }; 1076 1077 static struct insn opcode_e5[] = { 1078 #ifdef CONFIG_64BIT 1079 { "strag", 0x02, INSTR_SSE_RDRD }, 1080 { "chhsi", 0x54, INSTR_SIL_RDI }, 1081 { "chsi", 0x5c, INSTR_SIL_RDI }, 1082 { "cghsi", 0x58, INSTR_SIL_RDI }, 1083 { "clhhsi", 0x55, INSTR_SIL_RDU }, 1084 { "clfhsi", 0x5d, INSTR_SIL_RDU }, 1085 { "clghsi", 0x59, INSTR_SIL_RDU }, 1086 { "mvhhi", 0x44, INSTR_SIL_RDI }, 1087 { "mvhi", 0x4c, INSTR_SIL_RDI }, 1088 { "mvghi", 0x48, INSTR_SIL_RDI }, 1089 #endif 1090 { "lasp", 0x00, INSTR_SSE_RDRD }, 1091 { "tprot", 0x01, INSTR_SSE_RDRD }, 1092 { "mvcsk", 0x0e, INSTR_SSE_RDRD }, 1093 { "mvcdk", 0x0f, INSTR_SSE_RDRD }, 1094 { "", 0, INSTR_INVALID } 1095 }; 1096 1097 static struct insn opcode_eb[] = { 1098 #ifdef CONFIG_64BIT 1099 { "lmg", 0x04, INSTR_RSY_RRRD }, 1100 { "srag", 0x0a, INSTR_RSY_RRRD }, 1101 { "slag", 0x0b, INSTR_RSY_RRRD }, 1102 { "srlg", 0x0c, INSTR_RSY_RRRD }, 1103 { "sllg", 0x0d, INSTR_RSY_RRRD }, 1104 { "tracg", 0x0f, INSTR_RSY_RRRD }, 1105 { "csy", 0x14, INSTR_RSY_RRRD }, 1106 { "rllg", 0x1c, INSTR_RSY_RRRD }, 1107 { "clmh", 0x20, INSTR_RSY_RURD }, 1108 { "clmy", 0x21, INSTR_RSY_RURD }, 1109 { "stmg", 0x24, INSTR_RSY_RRRD }, 1110 { "stctg", 0x25, INSTR_RSY_CCRD }, 1111 { "stmh", 0x26, INSTR_RSY_RRRD }, 1112 { "stcmh", 0x2c, INSTR_RSY_RURD }, 1113 { "stcmy", 0x2d, INSTR_RSY_RURD }, 1114 { "lctlg", 0x2f, INSTR_RSY_CCRD }, 1115 { "csg", 0x30, INSTR_RSY_RRRD }, 1116 { "cdsy", 0x31, INSTR_RSY_RRRD }, 1117 { "cdsg", 0x3e, INSTR_RSY_RRRD }, 1118 { "bxhg", 0x44, INSTR_RSY_RRRD }, 1119 { "bxleg", 0x45, INSTR_RSY_RRRD }, 1120 { "tmy", 0x51, INSTR_SIY_URD }, 1121 { "mviy", 0x52, INSTR_SIY_URD }, 1122 { "niy", 0x54, INSTR_SIY_URD }, 1123 { "cliy", 0x55, INSTR_SIY_URD }, 1124 { "oiy", 0x56, INSTR_SIY_URD }, 1125 { "xiy", 0x57, INSTR_SIY_URD }, 1126 { "icmh", 0x80, INSTR_RSE_RURD }, 1127 { "icmh", 0x80, INSTR_RSY_RURD }, 1128 { "icmy", 0x81, INSTR_RSY_RURD }, 1129 { "clclu", 0x8f, INSTR_RSY_RRRD }, 1130 { "stmy", 0x90, INSTR_RSY_RRRD }, 1131 { "lmh", 0x96, INSTR_RSY_RRRD }, 1132 { "lmy", 0x98, INSTR_RSY_RRRD }, 1133 { "lamy", 0x9a, INSTR_RSY_AARD }, 1134 { "stamy", 0x9b, INSTR_RSY_AARD }, 1135 { "asi", 0x6a, INSTR_SIY_IRD }, 1136 { "agsi", 0x7a, INSTR_SIY_IRD }, 1137 { "alsi", 0x6e, INSTR_SIY_IRD }, 1138 { "algsi", 0x7e, INSTR_SIY_IRD }, 1139 { "ecag", 0x4c, INSTR_RSY_RRRD }, 1140 #endif 1141 { "rll", 0x1d, INSTR_RSY_RRRD }, 1142 { "mvclu", 0x8e, INSTR_RSY_RRRD }, 1143 { "tp", 0xc0, INSTR_RSL_R0RD }, 1144 { "", 0, INSTR_INVALID } 1145 }; 1146 1147 static struct insn opcode_ec[] = { 1148 #ifdef CONFIG_64BIT 1149 { "brxhg", 0x44, INSTR_RIE_RRP }, 1150 { "brxlg", 0x45, INSTR_RIE_RRP }, 1151 { "crb", 0xf6, INSTR_RRS_RRRDU }, 1152 { "cgrb", 0xe4, INSTR_RRS_RRRDU }, 1153 { "crj", 0x76, INSTR_RIE_RRPU }, 1154 { "cgrj", 0x64, INSTR_RIE_RRPU }, 1155 { "cib", 0xfe, INSTR_RIS_RURDI }, 1156 { "cgib", 0xfc, INSTR_RIS_RURDI }, 1157 { "cij", 0x7e, INSTR_RIE_RUPI }, 1158 { "cgij", 0x7c, INSTR_RIE_RUPI }, 1159 { "cit", 0x72, INSTR_RIE_R0IU }, 1160 { "cgit", 0x70, INSTR_RIE_R0IU }, 1161 { "clrb", 0xf7, INSTR_RRS_RRRDU }, 1162 { "clgrb", 0xe5, INSTR_RRS_RRRDU }, 1163 { "clrj", 0x77, INSTR_RIE_RRPU }, 1164 { "clgrj", 0x65, INSTR_RIE_RRPU }, 1165 { "clib", 0xff, INSTR_RIS_RURDU }, 1166 { "clgib", 0xfd, INSTR_RIS_RURDU }, 1167 { "clij", 0x7f, INSTR_RIE_RUPU }, 1168 { "clgij", 0x7d, INSTR_RIE_RUPU }, 1169 { "clfit", 0x73, INSTR_RIE_R0UU }, 1170 { "clgit", 0x71, INSTR_RIE_R0UU }, 1171 { "rnsbg", 0x54, INSTR_RIE_RRUUU }, 1172 { "rxsbg", 0x57, INSTR_RIE_RRUUU }, 1173 { "rosbg", 0x56, INSTR_RIE_RRUUU }, 1174 { "risbg", 0x55, INSTR_RIE_RRUUU }, 1175 #endif 1176 { "", 0, INSTR_INVALID } 1177 }; 1178 1179 static struct insn opcode_ed[] = { 1180 #ifdef CONFIG_64BIT 1181 { "mayl", 0x38, INSTR_RXF_FRRDF }, 1182 { "myl", 0x39, INSTR_RXF_FRRDF }, 1183 { "may", 0x3a, INSTR_RXF_FRRDF }, 1184 { "my", 0x3b, INSTR_RXF_FRRDF }, 1185 { "mayh", 0x3c, INSTR_RXF_FRRDF }, 1186 { "myh", 0x3d, INSTR_RXF_FRRDF }, 1187 { "ley", 0x64, INSTR_RXY_FRRD }, 1188 { "ldy", 0x65, INSTR_RXY_FRRD }, 1189 { "stey", 0x66, INSTR_RXY_FRRD }, 1190 { "stdy", 0x67, INSTR_RXY_FRRD }, 1191 { "sldt", 0x40, INSTR_RXF_FRRDF }, 1192 { "slxt", 0x48, INSTR_RXF_FRRDF }, 1193 { "srdt", 0x41, INSTR_RXF_FRRDF }, 1194 { "srxt", 0x49, INSTR_RXF_FRRDF }, 1195 { "tdcet", 0x50, INSTR_RXE_FRRD }, 1196 { "tdcdt", 0x54, INSTR_RXE_FRRD }, 1197 { "tdcxt", 0x58, INSTR_RXE_FRRD }, 1198 { "tdget", 0x51, INSTR_RXE_FRRD }, 1199 { "tdgdt", 0x55, INSTR_RXE_FRRD }, 1200 { "tdgxt", 0x59, INSTR_RXE_FRRD }, 1201 #endif 1202 { "ldeb", 0x04, INSTR_RXE_FRRD }, 1203 { "lxdb", 0x05, INSTR_RXE_FRRD }, 1204 { "lxeb", 0x06, INSTR_RXE_FRRD }, 1205 { "mxdb", 0x07, INSTR_RXE_FRRD }, 1206 { "keb", 0x08, INSTR_RXE_FRRD }, 1207 { "ceb", 0x09, INSTR_RXE_FRRD }, 1208 { "aeb", 0x0a, INSTR_RXE_FRRD }, 1209 { "seb", 0x0b, INSTR_RXE_FRRD }, 1210 { "mdeb", 0x0c, INSTR_RXE_FRRD }, 1211 { "deb", 0x0d, INSTR_RXE_FRRD }, 1212 { "maeb", 0x0e, INSTR_RXF_FRRDF }, 1213 { "mseb", 0x0f, INSTR_RXF_FRRDF }, 1214 { "tceb", 0x10, INSTR_RXE_FRRD }, 1215 { "tcdb", 0x11, INSTR_RXE_FRRD }, 1216 { "tcxb", 0x12, INSTR_RXE_FRRD }, 1217 { "sqeb", 0x14, INSTR_RXE_FRRD }, 1218 { "sqdb", 0x15, INSTR_RXE_FRRD }, 1219 { "meeb", 0x17, INSTR_RXE_FRRD }, 1220 { "kdb", 0x18, INSTR_RXE_FRRD }, 1221 { "cdb", 0x19, INSTR_RXE_FRRD }, 1222 { "adb", 0x1a, INSTR_RXE_FRRD }, 1223 { "sdb", 0x1b, INSTR_RXE_FRRD }, 1224 { "mdb", 0x1c, INSTR_RXE_FRRD }, 1225 { "ddb", 0x1d, INSTR_RXE_FRRD }, 1226 { "madb", 0x1e, INSTR_RXF_FRRDF }, 1227 { "msdb", 0x1f, INSTR_RXF_FRRDF }, 1228 { "lde", 0x24, INSTR_RXE_FRRD }, 1229 { "lxd", 0x25, INSTR_RXE_FRRD }, 1230 { "lxe", 0x26, INSTR_RXE_FRRD }, 1231 { "mae", 0x2e, INSTR_RXF_FRRDF }, 1232 { "mse", 0x2f, INSTR_RXF_FRRDF }, 1233 { "sqe", 0x34, INSTR_RXE_FRRD }, 1234 { "sqd", 0x35, INSTR_RXE_FRRD }, 1235 { "mee", 0x37, INSTR_RXE_FRRD }, 1236 { "mad", 0x3e, INSTR_RXF_FRRDF }, 1237 { "msd", 0x3f, INSTR_RXF_FRRDF }, 1238 { "", 0, INSTR_INVALID } 1239 }; 1240 1241 /* Extracts an operand value from an instruction. */ 1242 static unsigned int extract_operand(unsigned char *code, 1243 const struct operand *operand) 1244 { 1245 unsigned int val; 1246 int bits; 1247 1248 /* Extract fragments of the operand byte for byte. */ 1249 code += operand->shift / 8; 1250 bits = (operand->shift & 7) + operand->bits; 1251 val = 0; 1252 do { 1253 val <<= 8; 1254 val |= (unsigned int) *code++; 1255 bits -= 8; 1256 } while (bits > 0); 1257 val >>= -bits; 1258 val &= ((1U << (operand->bits - 1)) << 1) - 1; 1259 1260 /* Check for special long displacement case. */ 1261 if (operand->bits == 20 && operand->shift == 20) 1262 val = (val & 0xff) << 12 | (val & 0xfff00) >> 8; 1263 1264 /* Sign extend value if the operand is signed or pc relative. */ 1265 if ((operand->flags & (OPERAND_SIGNED | OPERAND_PCREL)) && 1266 (val & (1U << (operand->bits - 1)))) 1267 val |= (-1U << (operand->bits - 1)) << 1; 1268 1269 /* Double value if the operand is pc relative. */ 1270 if (operand->flags & OPERAND_PCREL) 1271 val <<= 1; 1272 1273 /* Length x in an instructions has real length x + 1. */ 1274 if (operand->flags & OPERAND_LENGTH) 1275 val++; 1276 return val; 1277 } 1278 1279 static inline int insn_length(unsigned char code) 1280 { 1281 return ((((int) code + 64) >> 7) + 1) << 1; 1282 } 1283 1284 static struct insn *find_insn(unsigned char *code) 1285 { 1286 unsigned char opfrag = code[1]; 1287 unsigned char opmask; 1288 struct insn *table; 1289 1290 switch (code[0]) { 1291 case 0x01: 1292 table = opcode_01; 1293 break; 1294 case 0xa5: 1295 table = opcode_a5; 1296 break; 1297 case 0xa7: 1298 table = opcode_a7; 1299 break; 1300 case 0xb2: 1301 table = opcode_b2; 1302 break; 1303 case 0xb3: 1304 table = opcode_b3; 1305 break; 1306 case 0xb9: 1307 table = opcode_b9; 1308 break; 1309 case 0xc0: 1310 table = opcode_c0; 1311 break; 1312 case 0xc2: 1313 table = opcode_c2; 1314 break; 1315 case 0xc4: 1316 table = opcode_c4; 1317 break; 1318 case 0xc6: 1319 table = opcode_c6; 1320 break; 1321 case 0xc8: 1322 table = opcode_c8; 1323 break; 1324 case 0xe3: 1325 table = opcode_e3; 1326 opfrag = code[5]; 1327 break; 1328 case 0xe5: 1329 table = opcode_e5; 1330 break; 1331 case 0xeb: 1332 table = opcode_eb; 1333 opfrag = code[5]; 1334 break; 1335 case 0xec: 1336 table = opcode_ec; 1337 opfrag = code[5]; 1338 break; 1339 case 0xed: 1340 table = opcode_ed; 1341 opfrag = code[5]; 1342 break; 1343 default: 1344 table = opcode; 1345 opfrag = code[0]; 1346 break; 1347 } 1348 while (table->format != INSTR_INVALID) { 1349 opmask = formats[table->format][0]; 1350 if (table->opfrag == (opfrag & opmask)) 1351 return table; 1352 table++; 1353 } 1354 return NULL; 1355 } 1356 1357 static int print_insn(char *buffer, unsigned char *code, unsigned long addr) 1358 { 1359 struct insn *insn; 1360 const unsigned char *ops; 1361 const struct operand *operand; 1362 unsigned int value; 1363 char separator; 1364 char *ptr; 1365 int i; 1366 1367 ptr = buffer; 1368 insn = find_insn(code); 1369 if (insn) { 1370 ptr += sprintf(ptr, "%.5s\t", insn->name); 1371 /* Extract the operands. */ 1372 separator = 0; 1373 for (ops = formats[insn->format] + 1, i = 0; 1374 *ops != 0 && i < 6; ops++, i++) { 1375 operand = operands + *ops; 1376 value = extract_operand(code, operand); 1377 if ((operand->flags & OPERAND_INDEX) && value == 0) 1378 continue; 1379 if ((operand->flags & OPERAND_BASE) && 1380 value == 0 && separator == '(') { 1381 separator = ','; 1382 continue; 1383 } 1384 if (separator) 1385 ptr += sprintf(ptr, "%c", separator); 1386 if (operand->flags & OPERAND_GPR) 1387 ptr += sprintf(ptr, "%%r%i", value); 1388 else if (operand->flags & OPERAND_FPR) 1389 ptr += sprintf(ptr, "%%f%i", value); 1390 else if (operand->flags & OPERAND_AR) 1391 ptr += sprintf(ptr, "%%a%i", value); 1392 else if (operand->flags & OPERAND_CR) 1393 ptr += sprintf(ptr, "%%c%i", value); 1394 else if (operand->flags & OPERAND_PCREL) 1395 ptr += sprintf(ptr, "%lx", (signed int) value 1396 + addr); 1397 else if (operand->flags & OPERAND_SIGNED) 1398 ptr += sprintf(ptr, "%i", value); 1399 else 1400 ptr += sprintf(ptr, "%u", value); 1401 if (operand->flags & OPERAND_DISP) 1402 separator = '('; 1403 else if (operand->flags & OPERAND_BASE) { 1404 ptr += sprintf(ptr, ")"); 1405 separator = ','; 1406 } else 1407 separator = ','; 1408 } 1409 } else 1410 ptr += sprintf(ptr, "unknown"); 1411 return (int) (ptr - buffer); 1412 } 1413 1414 void show_code(struct pt_regs *regs) 1415 { 1416 char *mode = (regs->psw.mask & PSW_MASK_PSTATE) ? "User" : "Krnl"; 1417 unsigned char code[64]; 1418 char buffer[64], *ptr; 1419 mm_segment_t old_fs; 1420 unsigned long addr; 1421 int start, end, opsize, hops, i; 1422 1423 /* Get a snapshot of the 64 bytes surrounding the fault address. */ 1424 old_fs = get_fs(); 1425 set_fs((regs->psw.mask & PSW_MASK_PSTATE) ? USER_DS : KERNEL_DS); 1426 for (start = 32; start && regs->psw.addr >= 34 - start; start -= 2) { 1427 addr = regs->psw.addr - 34 + start; 1428 if (__copy_from_user(code + start - 2, 1429 (char __user *) addr, 2)) 1430 break; 1431 } 1432 for (end = 32; end < 64; end += 2) { 1433 addr = regs->psw.addr + end - 32; 1434 if (__copy_from_user(code + end, 1435 (char __user *) addr, 2)) 1436 break; 1437 } 1438 set_fs(old_fs); 1439 /* Code snapshot useable ? */ 1440 if ((regs->psw.addr & 1) || start >= end) { 1441 printk("%s Code: Bad PSW.\n", mode); 1442 return; 1443 } 1444 /* Find a starting point for the disassembly. */ 1445 while (start < 32) { 1446 for (i = 0, hops = 0; start + i < 32 && hops < 3; hops++) { 1447 if (!find_insn(code + start + i)) 1448 break; 1449 i += insn_length(code[start + i]); 1450 } 1451 if (start + i == 32) 1452 /* Looks good, sequence ends at PSW. */ 1453 break; 1454 start += 2; 1455 } 1456 /* Decode the instructions. */ 1457 ptr = buffer; 1458 ptr += sprintf(ptr, "%s Code:", mode); 1459 hops = 0; 1460 while (start < end && hops < 8) { 1461 *ptr++ = (start == 32) ? '>' : ' '; 1462 addr = regs->psw.addr + start - 32; 1463 ptr += sprintf(ptr, ONELONG, addr); 1464 opsize = insn_length(code[start]); 1465 if (start + opsize >= end) 1466 break; 1467 for (i = 0; i < opsize; i++) 1468 ptr += sprintf(ptr, "%02x", code[start + i]); 1469 *ptr++ = '\t'; 1470 if (i < 6) 1471 *ptr++ = '\t'; 1472 ptr += print_insn(ptr, code + start, addr); 1473 start += opsize; 1474 printk(buffer); 1475 ptr = buffer; 1476 ptr += sprintf(ptr, "\n "); 1477 hops++; 1478 } 1479 printk("\n"); 1480 } 1481