1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _S390_TLB_H 3 #define _S390_TLB_H 4 5 /* 6 * TLB flushing on s390 is complicated. The following requirement 7 * from the principles of operation is the most arduous: 8 * 9 * "A valid table entry must not be changed while it is attached 10 * to any CPU and may be used for translation by that CPU except to 11 * (1) invalidate the entry by using INVALIDATE PAGE TABLE ENTRY, 12 * or INVALIDATE DAT TABLE ENTRY, (2) alter bits 56-63 of a page 13 * table entry, or (3) make a change by means of a COMPARE AND SWAP 14 * AND PURGE instruction that purges the TLB." 15 * 16 * The modification of a pte of an active mm struct therefore is 17 * a two step process: i) invalidate the pte, ii) store the new pte. 18 * This is true for the page protection bit as well. 19 * The only possible optimization is to flush at the beginning of 20 * a tlb_gather_mmu cycle if the mm_struct is currently not in use. 21 * 22 * Pages used for the page tables is a different story. FIXME: more 23 */ 24 25 #include <linux/mm.h> 26 #include <linux/pagemap.h> 27 #include <linux/swap.h> 28 #include <asm/processor.h> 29 #include <asm/pgalloc.h> 30 #include <asm/tlbflush.h> 31 32 struct mmu_gather { 33 struct mm_struct *mm; 34 struct mmu_table_batch *batch; 35 unsigned int fullmm; 36 unsigned long start, end; 37 }; 38 39 struct mmu_table_batch { 40 struct rcu_head rcu; 41 unsigned int nr; 42 void *tables[0]; 43 }; 44 45 #define MAX_TABLE_BATCH \ 46 ((PAGE_SIZE - sizeof(struct mmu_table_batch)) / sizeof(void *)) 47 48 extern void tlb_table_flush(struct mmu_gather *tlb); 49 extern void tlb_remove_table(struct mmu_gather *tlb, void *table); 50 51 static inline void 52 arch_tlb_gather_mmu(struct mmu_gather *tlb, struct mm_struct *mm, 53 unsigned long start, unsigned long end) 54 { 55 tlb->mm = mm; 56 tlb->start = start; 57 tlb->end = end; 58 tlb->fullmm = !(start | (end+1)); 59 tlb->batch = NULL; 60 } 61 62 static inline void tlb_flush_mmu_tlbonly(struct mmu_gather *tlb) 63 { 64 __tlb_flush_mm_lazy(tlb->mm); 65 } 66 67 static inline void tlb_flush_mmu_free(struct mmu_gather *tlb) 68 { 69 tlb_table_flush(tlb); 70 } 71 72 73 static inline void tlb_flush_mmu(struct mmu_gather *tlb) 74 { 75 tlb_flush_mmu_tlbonly(tlb); 76 tlb_flush_mmu_free(tlb); 77 } 78 79 static inline void 80 arch_tlb_finish_mmu(struct mmu_gather *tlb, 81 unsigned long start, unsigned long end, bool force) 82 { 83 if (force) { 84 tlb->start = start; 85 tlb->end = end; 86 } 87 88 tlb_flush_mmu(tlb); 89 } 90 91 /* 92 * Release the page cache reference for a pte removed by 93 * tlb_ptep_clear_flush. In both flush modes the tlb for a page cache page 94 * has already been freed, so just do free_page_and_swap_cache. 95 */ 96 static inline bool __tlb_remove_page(struct mmu_gather *tlb, struct page *page) 97 { 98 free_page_and_swap_cache(page); 99 return false; /* avoid calling tlb_flush_mmu */ 100 } 101 102 static inline void tlb_remove_page(struct mmu_gather *tlb, struct page *page) 103 { 104 free_page_and_swap_cache(page); 105 } 106 107 static inline bool __tlb_remove_page_size(struct mmu_gather *tlb, 108 struct page *page, int page_size) 109 { 110 return __tlb_remove_page(tlb, page); 111 } 112 113 static inline void tlb_remove_page_size(struct mmu_gather *tlb, 114 struct page *page, int page_size) 115 { 116 return tlb_remove_page(tlb, page); 117 } 118 119 /* 120 * pte_free_tlb frees a pte table and clears the CRSTE for the 121 * page table from the tlb. 122 */ 123 static inline void pte_free_tlb(struct mmu_gather *tlb, pgtable_t pte, 124 unsigned long address) 125 { 126 page_table_free_rcu(tlb, (unsigned long *) pte, address); 127 } 128 129 /* 130 * pmd_free_tlb frees a pmd table and clears the CRSTE for the 131 * segment table entry from the tlb. 132 * If the mm uses a two level page table the single pmd is freed 133 * as the pgd. pmd_free_tlb checks the asce_limit against 2GB 134 * to avoid the double free of the pmd in this case. 135 */ 136 static inline void pmd_free_tlb(struct mmu_gather *tlb, pmd_t *pmd, 137 unsigned long address) 138 { 139 if (tlb->mm->context.asce_limit <= _REGION3_SIZE) 140 return; 141 pgtable_pmd_page_dtor(virt_to_page(pmd)); 142 tlb_remove_table(tlb, pmd); 143 } 144 145 /* 146 * p4d_free_tlb frees a pud table and clears the CRSTE for the 147 * region second table entry from the tlb. 148 * If the mm uses a four level page table the single p4d is freed 149 * as the pgd. p4d_free_tlb checks the asce_limit against 8PB 150 * to avoid the double free of the p4d in this case. 151 */ 152 static inline void p4d_free_tlb(struct mmu_gather *tlb, p4d_t *p4d, 153 unsigned long address) 154 { 155 if (tlb->mm->context.asce_limit <= _REGION1_SIZE) 156 return; 157 tlb_remove_table(tlb, p4d); 158 } 159 160 /* 161 * pud_free_tlb frees a pud table and clears the CRSTE for the 162 * region third table entry from the tlb. 163 * If the mm uses a three level page table the single pud is freed 164 * as the pgd. pud_free_tlb checks the asce_limit against 4TB 165 * to avoid the double free of the pud in this case. 166 */ 167 static inline void pud_free_tlb(struct mmu_gather *tlb, pud_t *pud, 168 unsigned long address) 169 { 170 if (tlb->mm->context.asce_limit <= _REGION2_SIZE) 171 return; 172 tlb_remove_table(tlb, pud); 173 } 174 175 #define tlb_start_vma(tlb, vma) do { } while (0) 176 #define tlb_end_vma(tlb, vma) do { } while (0) 177 #define tlb_remove_tlb_entry(tlb, ptep, addr) do { } while (0) 178 #define tlb_remove_pmd_tlb_entry(tlb, pmdp, addr) do { } while (0) 179 #define tlb_migrate_finish(mm) do { } while (0) 180 #define tlb_remove_huge_tlb_entry(h, tlb, ptep, address) \ 181 tlb_remove_tlb_entry(tlb, ptep, address) 182 183 #define tlb_remove_check_page_size_change tlb_remove_check_page_size_change 184 static inline void tlb_remove_check_page_size_change(struct mmu_gather *tlb, 185 unsigned int page_size) 186 { 187 } 188 189 #endif /* _S390_TLB_H */ 190