xref: /openbmc/linux/arch/s390/include/asm/tlb.h (revision 89aba575)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _S390_TLB_H
3 #define _S390_TLB_H
4 
5 /*
6  * TLB flushing on s390 is complicated. The following requirement
7  * from the principles of operation is the most arduous:
8  *
9  * "A valid table entry must not be changed while it is attached
10  * to any CPU and may be used for translation by that CPU except to
11  * (1) invalidate the entry by using INVALIDATE PAGE TABLE ENTRY,
12  * or INVALIDATE DAT TABLE ENTRY, (2) alter bits 56-63 of a page
13  * table entry, or (3) make a change by means of a COMPARE AND SWAP
14  * AND PURGE instruction that purges the TLB."
15  *
16  * The modification of a pte of an active mm struct therefore is
17  * a two step process: i) invalidate the pte, ii) store the new pte.
18  * This is true for the page protection bit as well.
19  * The only possible optimization is to flush at the beginning of
20  * a tlb_gather_mmu cycle if the mm_struct is currently not in use.
21  *
22  * Pages used for the page tables is a different story. FIXME: more
23  */
24 
25 void __tlb_remove_table(void *_table);
26 static inline void tlb_flush(struct mmu_gather *tlb);
27 static inline bool __tlb_remove_page_size(struct mmu_gather *tlb,
28 					  struct page *page, int page_size);
29 
30 #define tlb_flush tlb_flush
31 #define pte_free_tlb pte_free_tlb
32 #define pmd_free_tlb pmd_free_tlb
33 #define p4d_free_tlb p4d_free_tlb
34 #define pud_free_tlb pud_free_tlb
35 
36 #include <asm/tlbflush.h>
37 #include <asm-generic/tlb.h>
38 
39 /*
40  * Release the page cache reference for a pte removed by
41  * tlb_ptep_clear_flush. In both flush modes the tlb for a page cache page
42  * has already been freed, so just do free_page_and_swap_cache.
43  */
44 static inline bool __tlb_remove_page_size(struct mmu_gather *tlb,
45 					  struct page *page, int page_size)
46 {
47 	free_page_and_swap_cache(page);
48 	return false;
49 }
50 
51 static inline void tlb_flush(struct mmu_gather *tlb)
52 {
53 	__tlb_flush_mm_lazy(tlb->mm);
54 }
55 
56 /*
57  * pte_free_tlb frees a pte table and clears the CRSTE for the
58  * page table from the tlb.
59  */
60 static inline void pte_free_tlb(struct mmu_gather *tlb, pgtable_t pte,
61                                 unsigned long address)
62 {
63 	__tlb_adjust_range(tlb, address, PAGE_SIZE);
64 	tlb->mm->context.flush_mm = 1;
65 	tlb->freed_tables = 1;
66 	tlb->cleared_pmds = 1;
67 	/*
68 	 * page_table_free_rcu takes care of the allocation bit masks
69 	 * of the 2K table fragments in the 4K page table page,
70 	 * then calls tlb_remove_table.
71 	 */
72 	page_table_free_rcu(tlb, (unsigned long *) pte, address);
73 }
74 
75 /*
76  * pmd_free_tlb frees a pmd table and clears the CRSTE for the
77  * segment table entry from the tlb.
78  * If the mm uses a two level page table the single pmd is freed
79  * as the pgd. pmd_free_tlb checks the asce_limit against 2GB
80  * to avoid the double free of the pmd in this case.
81  */
82 static inline void pmd_free_tlb(struct mmu_gather *tlb, pmd_t *pmd,
83 				unsigned long address)
84 {
85 	if (mm_pmd_folded(tlb->mm))
86 		return;
87 	pgtable_pmd_page_dtor(virt_to_page(pmd));
88 	__tlb_adjust_range(tlb, address, PAGE_SIZE);
89 	tlb->mm->context.flush_mm = 1;
90 	tlb->freed_tables = 1;
91 	tlb->cleared_puds = 1;
92 	tlb_remove_table(tlb, pmd);
93 }
94 
95 /*
96  * p4d_free_tlb frees a pud table and clears the CRSTE for the
97  * region second table entry from the tlb.
98  * If the mm uses a four level page table the single p4d is freed
99  * as the pgd. p4d_free_tlb checks the asce_limit against 8PB
100  * to avoid the double free of the p4d in this case.
101  */
102 static inline void p4d_free_tlb(struct mmu_gather *tlb, p4d_t *p4d,
103 				unsigned long address)
104 {
105 	if (mm_p4d_folded(tlb->mm))
106 		return;
107 	__tlb_adjust_range(tlb, address, PAGE_SIZE);
108 	tlb->mm->context.flush_mm = 1;
109 	tlb->freed_tables = 1;
110 	tlb_remove_table(tlb, p4d);
111 }
112 
113 /*
114  * pud_free_tlb frees a pud table and clears the CRSTE for the
115  * region third table entry from the tlb.
116  * If the mm uses a three level page table the single pud is freed
117  * as the pgd. pud_free_tlb checks the asce_limit against 4TB
118  * to avoid the double free of the pud in this case.
119  */
120 static inline void pud_free_tlb(struct mmu_gather *tlb, pud_t *pud,
121 				unsigned long address)
122 {
123 	if (mm_pud_folded(tlb->mm))
124 		return;
125 	tlb->mm->context.flush_mm = 1;
126 	tlb->freed_tables = 1;
127 	tlb->cleared_p4ds = 1;
128 	tlb_remove_table(tlb, pud);
129 }
130 
131 
132 #endif /* _S390_TLB_H */
133