xref: /openbmc/linux/arch/s390/include/asm/qdio.h (revision 2cf1c348)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Copyright IBM Corp. 2000, 2008
4  * Author(s): Utz Bacher <utz.bacher@de.ibm.com>
5  *	      Jan Glauber <jang@linux.vnet.ibm.com>
6  *
7  */
8 #ifndef __QDIO_H__
9 #define __QDIO_H__
10 
11 #include <linux/interrupt.h>
12 #include <asm/cio.h>
13 #include <asm/ccwdev.h>
14 
15 /* only use 4 queues to save some cachelines */
16 #define QDIO_MAX_QUEUES_PER_IRQ		4
17 #define QDIO_MAX_BUFFERS_PER_Q		128
18 #define QDIO_MAX_BUFFERS_MASK		(QDIO_MAX_BUFFERS_PER_Q - 1)
19 #define QDIO_BUFNR(num)			((num) & QDIO_MAX_BUFFERS_MASK)
20 #define QDIO_MAX_ELEMENTS_PER_BUFFER	16
21 
22 #define QDIO_QETH_QFMT			0
23 #define QDIO_ZFCP_QFMT			1
24 #define QDIO_IQDIO_QFMT			2
25 
26 /**
27  * struct qdesfmt0 - queue descriptor, format 0
28  * @sliba: absolute address of storage list information block
29  * @sla: absolute address of storage list
30  * @slsba: absolute address of storage list state block
31  * @akey: access key for SLIB
32  * @bkey: access key for SL
33  * @ckey: access key for SBALs
34  * @dkey: access key for SLSB
35  */
36 struct qdesfmt0 {
37 	u64 sliba;
38 	u64 sla;
39 	u64 slsba;
40 	u32	 : 32;
41 	u32 akey : 4;
42 	u32 bkey : 4;
43 	u32 ckey : 4;
44 	u32 dkey : 4;
45 	u32	 : 16;
46 } __attribute__ ((packed));
47 
48 #define QDR_AC_MULTI_BUFFER_ENABLE 0x01
49 
50 /**
51  * struct qdr - queue description record (QDR)
52  * @qfmt: queue format
53  * @ac: adapter characteristics
54  * @iqdcnt: input queue descriptor count
55  * @oqdcnt: output queue descriptor count
56  * @iqdsz: input queue descriptor size
57  * @oqdsz: output queue descriptor size
58  * @qiba: absolute address of queue information block
59  * @qkey: queue information block key
60  * @qdf0: queue descriptions
61  */
62 struct qdr {
63 	u32 qfmt   : 8;
64 	u32	   : 16;
65 	u32 ac	   : 8;
66 	u32	   : 8;
67 	u32 iqdcnt : 8;
68 	u32	   : 8;
69 	u32 oqdcnt : 8;
70 	u32	   : 8;
71 	u32 iqdsz  : 8;
72 	u32	   : 8;
73 	u32 oqdsz  : 8;
74 	/* private: */
75 	u32 res[9];
76 	/* public: */
77 	u64 qiba;
78 	u32	   : 32;
79 	u32 qkey   : 4;
80 	u32	   : 28;
81 	struct qdesfmt0 qdf0[126];
82 } __packed __aligned(PAGE_SIZE);
83 
84 #define QIB_AC_OUTBOUND_PCI_SUPPORTED	0x40
85 #define QIB_RFLAGS_ENABLE_QEBSM		0x80
86 #define QIB_RFLAGS_ENABLE_DATA_DIV	0x02
87 
88 /**
89  * struct qib - queue information block (QIB)
90  * @qfmt: queue format
91  * @pfmt: implementation dependent parameter format
92  * @rflags: QEBSM
93  * @ac: adapter characteristics
94  * @isliba: logical address of first input SLIB
95  * @osliba: logical address of first output SLIB
96  * @ebcnam: adapter identifier in EBCDIC
97  * @parm: implementation dependent parameters
98  */
99 struct qib {
100 	u32 qfmt   : 8;
101 	u32 pfmt   : 8;
102 	u32 rflags : 8;
103 	u32 ac	   : 8;
104 	u32	   : 32;
105 	u64 isliba;
106 	u64 osliba;
107 	u32	   : 32;
108 	u32	   : 32;
109 	u8 ebcnam[8];
110 	/* private: */
111 	u8 res[88];
112 	/* public: */
113 	u8 parm[128];
114 } __attribute__ ((packed, aligned(256)));
115 
116 /**
117  * struct slibe - storage list information block element (SLIBE)
118  * @parms: implementation dependent parameters
119  */
120 struct slibe {
121 	u64 parms;
122 };
123 
124 /**
125  * struct qaob - queue asynchronous operation block
126  * @res0: reserved parameters
127  * @res1: reserved parameter
128  * @res2: reserved parameter
129  * @res3: reserved parameter
130  * @aorc: asynchronous operation return code
131  * @flags: internal flags
132  * @cbtbs: control block type
133  * @sb_count: number of storage blocks
134  * @sba: storage block element addresses
135  * @dcount: size of storage block elements
136  * @user0: user defineable value
137  * @res4: reserved paramater
138  * @user1: user defineable value
139  */
140 struct qaob {
141 	u64 res0[6];
142 	u8 res1;
143 	u8 res2;
144 	u8 res3;
145 	u8 aorc;
146 	u8 flags;
147 	u16 cbtbs;
148 	u8 sb_count;
149 	u64 sba[QDIO_MAX_ELEMENTS_PER_BUFFER];
150 	u16 dcount[QDIO_MAX_ELEMENTS_PER_BUFFER];
151 	u64 user0;
152 	u64 res4[2];
153 	u8 user1[16];
154 } __attribute__ ((packed, aligned(256)));
155 
156 /**
157  * struct slib - storage list information block (SLIB)
158  * @nsliba: next SLIB address (if any)
159  * @sla: SL address
160  * @slsba: SLSB address
161  * @slibe: SLIB elements
162  */
163 struct slib {
164 	u64 nsliba;
165 	u64 sla;
166 	u64 slsba;
167 	/* private: */
168 	u8 res[1000];
169 	/* public: */
170 	struct slibe slibe[QDIO_MAX_BUFFERS_PER_Q];
171 } __attribute__ ((packed, aligned(2048)));
172 
173 #define SBAL_EFLAGS_LAST_ENTRY		0x40
174 #define SBAL_EFLAGS_CONTIGUOUS		0x20
175 #define SBAL_EFLAGS_FIRST_FRAG		0x04
176 #define SBAL_EFLAGS_MIDDLE_FRAG		0x08
177 #define SBAL_EFLAGS_LAST_FRAG		0x0c
178 #define SBAL_EFLAGS_MASK		0x6f
179 
180 #define SBAL_SFLAGS0_PCI_REQ		0x40
181 #define SBAL_SFLAGS0_DATA_CONTINUATION	0x20
182 
183 /* Awesome OpenFCP extensions */
184 #define SBAL_SFLAGS0_TYPE_STATUS	0x00
185 #define SBAL_SFLAGS0_TYPE_WRITE		0x08
186 #define SBAL_SFLAGS0_TYPE_READ		0x10
187 #define SBAL_SFLAGS0_TYPE_WRITE_READ	0x18
188 #define SBAL_SFLAGS0_MORE_SBALS		0x04
189 #define SBAL_SFLAGS0_COMMAND		0x02
190 #define SBAL_SFLAGS0_LAST_SBAL		0x00
191 #define SBAL_SFLAGS0_ONLY_SBAL		SBAL_SFLAGS0_COMMAND
192 #define SBAL_SFLAGS0_MIDDLE_SBAL	SBAL_SFLAGS0_MORE_SBALS
193 #define SBAL_SFLAGS0_FIRST_SBAL (SBAL_SFLAGS0_MORE_SBALS | SBAL_SFLAGS0_COMMAND)
194 
195 /**
196  * struct qdio_buffer_element - SBAL entry
197  * @eflags: SBAL entry flags
198  * @scount: SBAL count
199  * @sflags: whole SBAL flags
200  * @length: length
201  * @addr: absolute data address
202 */
203 struct qdio_buffer_element {
204 	u8 eflags;
205 	/* private: */
206 	u8 res1;
207 	/* public: */
208 	u8 scount;
209 	u8 sflags;
210 	u32 length;
211 	u64 addr;
212 } __attribute__ ((packed, aligned(16)));
213 
214 /**
215  * struct qdio_buffer - storage block address list (SBAL)
216  * @element: SBAL entries
217  */
218 struct qdio_buffer {
219 	struct qdio_buffer_element element[QDIO_MAX_ELEMENTS_PER_BUFFER];
220 } __attribute__ ((packed, aligned(256)));
221 
222 /**
223  * struct sl_element - storage list entry
224  * @sbal: absolute SBAL address
225  */
226 struct sl_element {
227 	u64 sbal;
228 } __attribute__ ((packed));
229 
230 /**
231  * struct sl - storage list (SL)
232  * @element: SL entries
233  */
234 struct sl {
235 	struct sl_element element[QDIO_MAX_BUFFERS_PER_Q];
236 } __attribute__ ((packed, aligned(1024)));
237 
238 /**
239  * struct slsb - storage list state block (SLSB)
240  * @val: state per buffer
241  */
242 struct slsb {
243 	u8 val[QDIO_MAX_BUFFERS_PER_Q];
244 } __attribute__ ((packed, aligned(256)));
245 
246 /* qdio adapter-characteristics-1 flag */
247 #define CHSC_AC1_INITIATE_INPUTQ	0x80
248 #define AC1_SIGA_INPUT_NEEDED		0x40	/* process input queues */
249 #define AC1_SIGA_OUTPUT_NEEDED		0x20	/* process output queues */
250 #define AC1_SIGA_SYNC_NEEDED		0x10	/* ask hypervisor to sync */
251 #define AC1_AUTOMATIC_SYNC_ON_THININT	0x08	/* set by hypervisor */
252 #define AC1_AUTOMATIC_SYNC_ON_OUT_PCI	0x04	/* set by hypervisor */
253 #define AC1_SC_QEBSM_AVAILABLE		0x02	/* available for subchannel */
254 #define AC1_SC_QEBSM_ENABLED		0x01	/* enabled for subchannel */
255 
256 #define CHSC_AC2_MULTI_BUFFER_AVAILABLE	0x0080
257 #define CHSC_AC2_MULTI_BUFFER_ENABLED	0x0040
258 #define CHSC_AC2_DATA_DIV_AVAILABLE	0x0010
259 #define CHSC_AC2_SNIFFER_AVAILABLE	0x0008
260 #define CHSC_AC2_DATA_DIV_ENABLED	0x0002
261 
262 #define CHSC_AC3_FORMAT2_CQ_AVAILABLE	0x8000
263 
264 struct qdio_ssqd_desc {
265 	u8 flags;
266 	u8:8;
267 	u16 sch;
268 	u8 qfmt;
269 	u8 parm;
270 	u8 qdioac1;
271 	u8 sch_class;
272 	u8 pcnt;
273 	u8 icnt;
274 	u8:8;
275 	u8 ocnt;
276 	u8:8;
277 	u8 mbccnt;
278 	u16 qdioac2;
279 	u64 sch_token;
280 	u8 mro;
281 	u8 mri;
282 	u16 qdioac3;
283 	u16:16;
284 	u8:8;
285 	u8 mmwc;
286 } __attribute__ ((packed));
287 
288 /* params are: ccw_device, qdio_error, queue_number,
289    first element processed, number of elements processed, int_parm */
290 typedef void qdio_handler_t(struct ccw_device *, unsigned int, int,
291 			    int, int, unsigned long);
292 
293 /* qdio errors reported through the queue handlers: */
294 #define QDIO_ERROR_ACTIVATE			0x0001
295 #define QDIO_ERROR_GET_BUF_STATE		0x0002
296 #define QDIO_ERROR_SET_BUF_STATE		0x0004
297 
298 /* extra info for completed SBALs: */
299 #define QDIO_ERROR_SLSB_STATE			0x0100
300 #define QDIO_ERROR_SLSB_PENDING			0x0200
301 
302 /* for qdio_cleanup */
303 #define QDIO_FLAG_CLEANUP_USING_CLEAR		0x01
304 #define QDIO_FLAG_CLEANUP_USING_HALT		0x02
305 
306 /**
307  * struct qdio_initialize - qdio initialization data
308  * @q_format: queue format
309  * @qdr_ac: feature flags to set
310  * @qib_param_field_format: format for qib_parm_field
311  * @qib_param_field: pointer to 128 bytes or NULL, if no param field
312  * @qib_rflags: rflags to set
313  * @no_input_qs: number of input queues
314  * @no_output_qs: number of output queues
315  * @input_handler: handler to be called for input queues, and device-wide errors
316  * @output_handler: handler to be called for output queues
317  * @irq_poll: Data IRQ polling handler
318  * @scan_threshold: # of in-use buffers that triggers scan on output queue
319  * @int_parm: interruption parameter
320  * @input_sbal_addr_array:  per-queue array, each element points to 128 SBALs
321  * @output_sbal_addr_array: per-queue array, each element points to 128 SBALs
322  */
323 struct qdio_initialize {
324 	unsigned char q_format;
325 	unsigned char qdr_ac;
326 	unsigned int qib_param_field_format;
327 	unsigned char *qib_param_field;
328 	unsigned char qib_rflags;
329 	unsigned int no_input_qs;
330 	unsigned int no_output_qs;
331 	qdio_handler_t *input_handler;
332 	qdio_handler_t *output_handler;
333 	void (*irq_poll)(struct ccw_device *cdev, unsigned long data);
334 	unsigned long int_parm;
335 	struct qdio_buffer ***input_sbal_addr_array;
336 	struct qdio_buffer ***output_sbal_addr_array;
337 };
338 
339 int qdio_alloc_buffers(struct qdio_buffer **buf, unsigned int count);
340 void qdio_free_buffers(struct qdio_buffer **buf, unsigned int count);
341 void qdio_reset_buffers(struct qdio_buffer **buf, unsigned int count);
342 
343 extern int qdio_allocate(struct ccw_device *cdev, unsigned int no_input_qs,
344 			 unsigned int no_output_qs);
345 extern int qdio_establish(struct ccw_device *cdev,
346 			  struct qdio_initialize *init_data);
347 extern int qdio_activate(struct ccw_device *);
348 extern int qdio_start_irq(struct ccw_device *cdev);
349 extern int qdio_stop_irq(struct ccw_device *cdev);
350 extern int qdio_inspect_input_queue(struct ccw_device *cdev, unsigned int nr,
351 				    unsigned int *bufnr, unsigned int *error);
352 extern int qdio_inspect_output_queue(struct ccw_device *cdev, unsigned int nr,
353 				     unsigned int *bufnr, unsigned int *error);
354 extern int qdio_add_bufs_to_input_queue(struct ccw_device *cdev,
355 					unsigned int q_nr, unsigned int bufnr,
356 					unsigned int count);
357 extern int qdio_add_bufs_to_output_queue(struct ccw_device *cdev,
358 					 unsigned int q_nr, unsigned int bufnr,
359 					 unsigned int count, struct qaob *aob);
360 extern int qdio_shutdown(struct ccw_device *, int);
361 extern int qdio_free(struct ccw_device *);
362 extern int qdio_get_ssqd_desc(struct ccw_device *, struct qdio_ssqd_desc *);
363 
364 #endif /* __QDIO_H__ */
365