xref: /openbmc/linux/arch/s390/include/asm/processor.h (revision d2999e1b)
1 /*
2  *  S390 version
3  *    Copyright IBM Corp. 1999
4  *    Author(s): Hartmut Penner (hp@de.ibm.com),
5  *               Martin Schwidefsky (schwidefsky@de.ibm.com)
6  *
7  *  Derived from "include/asm-i386/processor.h"
8  *    Copyright (C) 1994, Linus Torvalds
9  */
10 
11 #ifndef __ASM_S390_PROCESSOR_H
12 #define __ASM_S390_PROCESSOR_H
13 
14 #define CIF_MCCK_PENDING	0	/* machine check handling is pending */
15 #define CIF_ASCE		1	/* user asce needs fixup / uaccess */
16 
17 #define _CIF_MCCK_PENDING	(1<<CIF_MCCK_PENDING)
18 #define _CIF_ASCE		(1<<CIF_ASCE)
19 
20 
21 #ifndef __ASSEMBLY__
22 
23 #include <linux/linkage.h>
24 #include <linux/irqflags.h>
25 #include <asm/cpu.h>
26 #include <asm/page.h>
27 #include <asm/ptrace.h>
28 #include <asm/setup.h>
29 #include <asm/runtime_instr.h>
30 
31 static inline void set_cpu_flag(int flag)
32 {
33 	S390_lowcore.cpu_flags |= (1U << flag);
34 }
35 
36 static inline void clear_cpu_flag(int flag)
37 {
38 	S390_lowcore.cpu_flags &= ~(1U << flag);
39 }
40 
41 static inline int test_cpu_flag(int flag)
42 {
43 	return !!(S390_lowcore.cpu_flags & (1U << flag));
44 }
45 
46 /*
47  * Default implementation of macro that returns current
48  * instruction pointer ("program counter").
49  */
50 #define current_text_addr() ({ void *pc; asm("basr %0,0" : "=a" (pc)); pc; })
51 
52 static inline void get_cpu_id(struct cpuid *ptr)
53 {
54 	asm volatile("stidp %0" : "=Q" (*ptr));
55 }
56 
57 extern void s390_adjust_jiffies(void);
58 extern const struct seq_operations cpuinfo_op;
59 extern int sysctl_ieee_emulation_warnings;
60 extern void execve_tail(void);
61 
62 /*
63  * User space process size: 2GB for 31 bit, 4TB or 8PT for 64 bit.
64  */
65 #ifndef CONFIG_64BIT
66 
67 #define TASK_SIZE		(1UL << 31)
68 #define TASK_MAX_SIZE		(1UL << 31)
69 #define TASK_UNMAPPED_BASE	(1UL << 30)
70 
71 #else /* CONFIG_64BIT */
72 
73 #define TASK_SIZE_OF(tsk)	((tsk)->mm->context.asce_limit)
74 #define TASK_UNMAPPED_BASE	(test_thread_flag(TIF_31BIT) ? \
75 					(1UL << 30) : (1UL << 41))
76 #define TASK_SIZE		TASK_SIZE_OF(current)
77 #define TASK_MAX_SIZE		(1UL << 53)
78 
79 #endif /* CONFIG_64BIT */
80 
81 #ifndef CONFIG_64BIT
82 #define STACK_TOP		(1UL << 31)
83 #define STACK_TOP_MAX		(1UL << 31)
84 #else /* CONFIG_64BIT */
85 #define STACK_TOP		(1UL << (test_thread_flag(TIF_31BIT) ? 31:42))
86 #define STACK_TOP_MAX		(1UL << 42)
87 #endif /* CONFIG_64BIT */
88 
89 #define HAVE_ARCH_PICK_MMAP_LAYOUT
90 
91 typedef struct {
92         __u32 ar4;
93 } mm_segment_t;
94 
95 /*
96  * Thread structure
97  */
98 struct thread_struct {
99 	s390_fp_regs fp_regs;
100 	unsigned int  acrs[NUM_ACRS];
101         unsigned long ksp;              /* kernel stack pointer             */
102 	mm_segment_t mm_segment;
103 	unsigned long gmap_addr;	/* address of last gmap fault. */
104 	unsigned int gmap_pfault;	/* signal of a pending guest pfault */
105 	struct per_regs per_user;	/* User specified PER registers */
106 	struct per_event per_event;	/* Cause of the last PER trap */
107 	unsigned long per_flags;	/* Flags to control debug behavior */
108         /* pfault_wait is used to block the process on a pfault event */
109 	unsigned long pfault_wait;
110 	struct list_head list;
111 	/* cpu runtime instrumentation */
112 	struct runtime_instr_cb *ri_cb;
113 	int ri_signum;
114 #ifdef CONFIG_64BIT
115 	unsigned char trap_tdb[256];	/* Transaction abort diagnose block */
116 #endif
117 };
118 
119 /* Flag to disable transactions. */
120 #define PER_FLAG_NO_TE			1UL
121 /* Flag to enable random transaction aborts. */
122 #define PER_FLAG_TE_ABORT_RAND		2UL
123 /* Flag to specify random transaction abort mode:
124  * - abort each transaction at a random instruction before TEND if set.
125  * - abort random transactions at a random instruction if cleared.
126  */
127 #define PER_FLAG_TE_ABORT_RAND_TEND	4UL
128 
129 typedef struct thread_struct thread_struct;
130 
131 /*
132  * Stack layout of a C stack frame.
133  */
134 #ifndef __PACK_STACK
135 struct stack_frame {
136 	unsigned long back_chain;
137 	unsigned long empty1[5];
138 	unsigned long gprs[10];
139 	unsigned int  empty2[8];
140 };
141 #else
142 struct stack_frame {
143 	unsigned long empty1[5];
144 	unsigned int  empty2[8];
145 	unsigned long gprs[10];
146 	unsigned long back_chain;
147 };
148 #endif
149 
150 #define ARCH_MIN_TASKALIGN	8
151 
152 #define INIT_THREAD {							\
153 	.ksp = sizeof(init_stack) + (unsigned long) &init_stack,	\
154 }
155 
156 /*
157  * Do necessary setup to start up a new thread.
158  */
159 #define start_thread(regs, new_psw, new_stackp) do {			\
160 	regs->psw.mask	= PSW_USER_BITS | PSW_MASK_EA | PSW_MASK_BA;	\
161 	regs->psw.addr	= new_psw | PSW_ADDR_AMODE;			\
162 	regs->gprs[15]	= new_stackp;					\
163 	execve_tail();							\
164 } while (0)
165 
166 #define start_thread31(regs, new_psw, new_stackp) do {			\
167 	regs->psw.mask	= PSW_USER_BITS | PSW_MASK_BA;			\
168 	regs->psw.addr	= new_psw | PSW_ADDR_AMODE;			\
169 	regs->gprs[15]	= new_stackp;					\
170 	crst_table_downgrade(current->mm, 1UL << 31);			\
171 	execve_tail();							\
172 } while (0)
173 
174 /* Forward declaration, a strange C thing */
175 struct task_struct;
176 struct mm_struct;
177 struct seq_file;
178 
179 #ifdef CONFIG_64BIT
180 extern void show_cacheinfo(struct seq_file *m);
181 #else
182 static inline void show_cacheinfo(struct seq_file *m) { }
183 #endif
184 
185 /* Free all resources held by a thread. */
186 extern void release_thread(struct task_struct *);
187 
188 /*
189  * Return saved PC of a blocked thread.
190  */
191 extern unsigned long thread_saved_pc(struct task_struct *t);
192 
193 unsigned long get_wchan(struct task_struct *p);
194 #define task_pt_regs(tsk) ((struct pt_regs *) \
195         (task_stack_page(tsk) + THREAD_SIZE) - 1)
196 #define KSTK_EIP(tsk)	(task_pt_regs(tsk)->psw.addr)
197 #define KSTK_ESP(tsk)	(task_pt_regs(tsk)->gprs[15])
198 
199 /* Has task runtime instrumentation enabled ? */
200 #define is_ri_task(tsk) (!!(tsk)->thread.ri_cb)
201 
202 static inline unsigned short stap(void)
203 {
204 	unsigned short cpu_address;
205 
206 	asm volatile("stap %0" : "=m" (cpu_address));
207 	return cpu_address;
208 }
209 
210 /*
211  * Give up the time slice of the virtual PU.
212  */
213 static inline void cpu_relax(void)
214 {
215 	if (MACHINE_HAS_DIAG44)
216 		asm volatile("diag 0,0,68");
217 	barrier();
218 }
219 
220 #define arch_mutex_cpu_relax()  barrier()
221 
222 static inline void psw_set_key(unsigned int key)
223 {
224 	asm volatile("spka 0(%0)" : : "d" (key));
225 }
226 
227 /*
228  * Set PSW to specified value.
229  */
230 static inline void __load_psw(psw_t psw)
231 {
232 #ifndef CONFIG_64BIT
233 	asm volatile("lpsw  %0" : : "Q" (psw) : "cc");
234 #else
235 	asm volatile("lpswe %0" : : "Q" (psw) : "cc");
236 #endif
237 }
238 
239 /*
240  * Set PSW mask to specified value, while leaving the
241  * PSW addr pointing to the next instruction.
242  */
243 static inline void __load_psw_mask (unsigned long mask)
244 {
245 	unsigned long addr;
246 	psw_t psw;
247 
248 	psw.mask = mask;
249 
250 #ifndef CONFIG_64BIT
251 	asm volatile(
252 		"	basr	%0,0\n"
253 		"0:	ahi	%0,1f-0b\n"
254 		"	st	%0,%O1+4(%R1)\n"
255 		"	lpsw	%1\n"
256 		"1:"
257 		: "=&d" (addr), "=Q" (psw) : "Q" (psw) : "memory", "cc");
258 #else /* CONFIG_64BIT */
259 	asm volatile(
260 		"	larl	%0,1f\n"
261 		"	stg	%0,%O1+8(%R1)\n"
262 		"	lpswe	%1\n"
263 		"1:"
264 		: "=&d" (addr), "=Q" (psw) : "Q" (psw) : "memory", "cc");
265 #endif /* CONFIG_64BIT */
266 }
267 
268 /*
269  * Rewind PSW instruction address by specified number of bytes.
270  */
271 static inline unsigned long __rewind_psw(psw_t psw, unsigned long ilc)
272 {
273 #ifndef CONFIG_64BIT
274 	if (psw.addr & PSW_ADDR_AMODE)
275 		/* 31 bit mode */
276 		return (psw.addr - ilc) | PSW_ADDR_AMODE;
277 	/* 24 bit mode */
278 	return (psw.addr - ilc) & ((1UL << 24) - 1);
279 #else
280 	unsigned long mask;
281 
282 	mask = (psw.mask & PSW_MASK_EA) ? -1UL :
283 	       (psw.mask & PSW_MASK_BA) ? (1UL << 31) - 1 :
284 					  (1UL << 24) - 1;
285 	return (psw.addr - ilc) & mask;
286 #endif
287 }
288 
289 /*
290  * Function to drop a processor into disabled wait state
291  */
292 static inline void __noreturn disabled_wait(unsigned long code)
293 {
294         unsigned long ctl_buf;
295         psw_t dw_psw;
296 
297 	dw_psw.mask = PSW_MASK_BASE | PSW_MASK_WAIT | PSW_MASK_BA | PSW_MASK_EA;
298         dw_psw.addr = code;
299         /*
300          * Store status and then load disabled wait psw,
301          * the processor is dead afterwards
302          */
303 #ifndef CONFIG_64BIT
304 	asm volatile(
305 		"	stctl	0,0,0(%2)\n"
306 		"	ni	0(%2),0xef\n"	/* switch off protection */
307 		"	lctl	0,0,0(%2)\n"
308 		"	stpt	0xd8\n"		/* store timer */
309 		"	stckc	0xe0\n"		/* store clock comparator */
310 		"	stpx	0x108\n"	/* store prefix register */
311 		"	stam	0,15,0x120\n"	/* store access registers */
312 		"	std	0,0x160\n"	/* store f0 */
313 		"	std	2,0x168\n"	/* store f2 */
314 		"	std	4,0x170\n"	/* store f4 */
315 		"	std	6,0x178\n"	/* store f6 */
316 		"	stm	0,15,0x180\n"	/* store general registers */
317 		"	stctl	0,15,0x1c0\n"	/* store control registers */
318 		"	oi	0x1c0,0x10\n"	/* fake protection bit */
319 		"	lpsw	0(%1)"
320 		: "=m" (ctl_buf)
321 		: "a" (&dw_psw), "a" (&ctl_buf), "m" (dw_psw) : "cc");
322 #else /* CONFIG_64BIT */
323 	asm volatile(
324 		"	stctg	0,0,0(%2)\n"
325 		"	ni	4(%2),0xef\n"	/* switch off protection */
326 		"	lctlg	0,0,0(%2)\n"
327 		"	lghi	1,0x1000\n"
328 		"	stpt	0x328(1)\n"	/* store timer */
329 		"	stckc	0x330(1)\n"	/* store clock comparator */
330 		"	stpx	0x318(1)\n"	/* store prefix register */
331 		"	stam	0,15,0x340(1)\n"/* store access registers */
332 		"	stfpc	0x31c(1)\n"	/* store fpu control */
333 		"	std	0,0x200(1)\n"	/* store f0 */
334 		"	std	1,0x208(1)\n"	/* store f1 */
335 		"	std	2,0x210(1)\n"	/* store f2 */
336 		"	std	3,0x218(1)\n"	/* store f3 */
337 		"	std	4,0x220(1)\n"	/* store f4 */
338 		"	std	5,0x228(1)\n"	/* store f5 */
339 		"	std	6,0x230(1)\n"	/* store f6 */
340 		"	std	7,0x238(1)\n"	/* store f7 */
341 		"	std	8,0x240(1)\n"	/* store f8 */
342 		"	std	9,0x248(1)\n"	/* store f9 */
343 		"	std	10,0x250(1)\n"	/* store f10 */
344 		"	std	11,0x258(1)\n"	/* store f11 */
345 		"	std	12,0x260(1)\n"	/* store f12 */
346 		"	std	13,0x268(1)\n"	/* store f13 */
347 		"	std	14,0x270(1)\n"	/* store f14 */
348 		"	std	15,0x278(1)\n"	/* store f15 */
349 		"	stmg	0,15,0x280(1)\n"/* store general registers */
350 		"	stctg	0,15,0x380(1)\n"/* store control registers */
351 		"	oi	0x384(1),0x10\n"/* fake protection bit */
352 		"	lpswe	0(%1)"
353 		: "=m" (ctl_buf)
354 		: "a" (&dw_psw), "a" (&ctl_buf), "m" (dw_psw) : "cc", "0", "1");
355 #endif /* CONFIG_64BIT */
356 	while (1);
357 }
358 
359 /*
360  * Use to set psw mask except for the first byte which
361  * won't be changed by this function.
362  */
363 static inline void
364 __set_psw_mask(unsigned long mask)
365 {
366 	__load_psw_mask(mask | (arch_local_save_flags() & ~(-1UL >> 8)));
367 }
368 
369 #define local_mcck_enable() \
370 	__set_psw_mask(PSW_KERNEL_BITS | PSW_MASK_DAT | PSW_MASK_MCHECK)
371 #define local_mcck_disable() \
372 	__set_psw_mask(PSW_KERNEL_BITS | PSW_MASK_DAT)
373 
374 /*
375  * Basic Machine Check/Program Check Handler.
376  */
377 
378 extern void s390_base_mcck_handler(void);
379 extern void s390_base_pgm_handler(void);
380 extern void s390_base_ext_handler(void);
381 
382 extern void (*s390_base_mcck_handler_fn)(void);
383 extern void (*s390_base_pgm_handler_fn)(void);
384 extern void (*s390_base_ext_handler_fn)(void);
385 
386 #define ARCH_LOW_ADDRESS_LIMIT	0x7fffffffUL
387 
388 extern int memcpy_real(void *, void *, size_t);
389 extern void memcpy_absolute(void *, void *, size_t);
390 
391 #define mem_assign_absolute(dest, val) {			\
392 	__typeof__(dest) __tmp = (val);				\
393 								\
394 	BUILD_BUG_ON(sizeof(__tmp) != sizeof(val));		\
395 	memcpy_absolute(&(dest), &__tmp, sizeof(__tmp));	\
396 }
397 
398 /*
399  * Helper macro for exception table entries
400  */
401 #define EX_TABLE(_fault, _target)	\
402 	".section __ex_table,\"a\"\n"	\
403 	".align	4\n"			\
404 	".long	(" #_fault ") - .\n"	\
405 	".long	(" #_target ") - .\n"	\
406 	".previous\n"
407 
408 #else /* __ASSEMBLY__ */
409 
410 #define EX_TABLE(_fault, _target)	\
411 	.section __ex_table,"a"	;	\
412 	.align	4 ;			\
413 	.long	(_fault) - . ;		\
414 	.long	(_target) - . ;		\
415 	.previous
416 
417 #endif /* __ASSEMBLY__ */
418 
419 #endif /* __ASM_S390_PROCESSOR_H */
420