1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * S390 version 4 * Copyright IBM Corp. 1999 5 * Author(s): Hartmut Penner (hp@de.ibm.com), 6 * Martin Schwidefsky (schwidefsky@de.ibm.com) 7 * 8 * Derived from "include/asm-i386/processor.h" 9 * Copyright (C) 1994, Linus Torvalds 10 */ 11 12 #ifndef __ASM_S390_PROCESSOR_H 13 #define __ASM_S390_PROCESSOR_H 14 15 #include <linux/bits.h> 16 17 #define CIF_NOHZ_DELAY 2 /* delay HZ disable for a tick */ 18 #define CIF_FPU 3 /* restore FPU registers */ 19 #define CIF_ENABLED_WAIT 5 /* in enabled wait state */ 20 #define CIF_MCCK_GUEST 6 /* machine check happening in guest */ 21 #define CIF_DEDICATED_CPU 7 /* this CPU is dedicated */ 22 23 #define _CIF_NOHZ_DELAY BIT(CIF_NOHZ_DELAY) 24 #define _CIF_FPU BIT(CIF_FPU) 25 #define _CIF_ENABLED_WAIT BIT(CIF_ENABLED_WAIT) 26 #define _CIF_MCCK_GUEST BIT(CIF_MCCK_GUEST) 27 #define _CIF_DEDICATED_CPU BIT(CIF_DEDICATED_CPU) 28 29 #define RESTART_FLAG_CTLREGS _AC(1 << 0, U) 30 31 #ifndef __ASSEMBLY__ 32 33 #include <linux/cpumask.h> 34 #include <linux/linkage.h> 35 #include <linux/irqflags.h> 36 #include <asm/cpu.h> 37 #include <asm/page.h> 38 #include <asm/ptrace.h> 39 #include <asm/setup.h> 40 #include <asm/runtime_instr.h> 41 #include <asm/fpu/types.h> 42 #include <asm/fpu/internal.h> 43 #include <asm/irqflags.h> 44 45 typedef long (*sys_call_ptr_t)(struct pt_regs *regs); 46 47 static inline void set_cpu_flag(int flag) 48 { 49 S390_lowcore.cpu_flags |= (1UL << flag); 50 } 51 52 static inline void clear_cpu_flag(int flag) 53 { 54 S390_lowcore.cpu_flags &= ~(1UL << flag); 55 } 56 57 static inline int test_cpu_flag(int flag) 58 { 59 return !!(S390_lowcore.cpu_flags & (1UL << flag)); 60 } 61 62 /* 63 * Test CIF flag of another CPU. The caller needs to ensure that 64 * CPU hotplug can not happen, e.g. by disabling preemption. 65 */ 66 static inline int test_cpu_flag_of(int flag, int cpu) 67 { 68 struct lowcore *lc = lowcore_ptr[cpu]; 69 return !!(lc->cpu_flags & (1UL << flag)); 70 } 71 72 #define arch_needs_cpu() test_cpu_flag(CIF_NOHZ_DELAY) 73 74 static inline void get_cpu_id(struct cpuid *ptr) 75 { 76 asm volatile("stidp %0" : "=Q" (*ptr)); 77 } 78 79 void s390_adjust_jiffies(void); 80 void s390_update_cpu_mhz(void); 81 void cpu_detect_mhz_feature(void); 82 83 extern const struct seq_operations cpuinfo_op; 84 extern void execve_tail(void); 85 extern void __bpon(void); 86 87 /* 88 * User space process size: 2GB for 31 bit, 4TB or 8PT for 64 bit. 89 */ 90 91 #define TASK_SIZE (test_thread_flag(TIF_31BIT) ? \ 92 _REGION3_SIZE : TASK_SIZE_MAX) 93 #define TASK_UNMAPPED_BASE (test_thread_flag(TIF_31BIT) ? \ 94 (_REGION3_SIZE >> 1) : (_REGION2_SIZE >> 1)) 95 #define TASK_SIZE_MAX (-PAGE_SIZE) 96 97 #define STACK_TOP (test_thread_flag(TIF_31BIT) ? \ 98 _REGION3_SIZE : _REGION2_SIZE) 99 #define STACK_TOP_MAX _REGION2_SIZE 100 101 #define HAVE_ARCH_PICK_MMAP_LAYOUT 102 103 /* 104 * Thread structure 105 */ 106 struct thread_struct { 107 unsigned int acrs[NUM_ACRS]; 108 unsigned long ksp; /* kernel stack pointer */ 109 unsigned long user_timer; /* task cputime in user space */ 110 unsigned long guest_timer; /* task cputime in kvm guest */ 111 unsigned long system_timer; /* task cputime in kernel space */ 112 unsigned long hardirq_timer; /* task cputime in hardirq context */ 113 unsigned long softirq_timer; /* task cputime in softirq context */ 114 const sys_call_ptr_t *sys_call_table; /* system call table address */ 115 unsigned long gmap_addr; /* address of last gmap fault. */ 116 unsigned int gmap_write_flag; /* gmap fault write indication */ 117 unsigned int gmap_int_code; /* int code of last gmap fault */ 118 unsigned int gmap_pfault; /* signal of a pending guest pfault */ 119 120 /* Per-thread information related to debugging */ 121 struct per_regs per_user; /* User specified PER registers */ 122 struct per_event per_event; /* Cause of the last PER trap */ 123 unsigned long per_flags; /* Flags to control debug behavior */ 124 unsigned int system_call; /* system call number in signal */ 125 unsigned long last_break; /* last breaking-event-address. */ 126 /* pfault_wait is used to block the process on a pfault event */ 127 unsigned long pfault_wait; 128 struct list_head list; 129 /* cpu runtime instrumentation */ 130 struct runtime_instr_cb *ri_cb; 131 struct gs_cb *gs_cb; /* Current guarded storage cb */ 132 struct gs_cb *gs_bc_cb; /* Broadcast guarded storage cb */ 133 struct pgm_tdb trap_tdb; /* Transaction abort diagnose block */ 134 /* 135 * Warning: 'fpu' is dynamically-sized. It *MUST* be at 136 * the end. 137 */ 138 struct fpu fpu; /* FP and VX register save area */ 139 }; 140 141 /* Flag to disable transactions. */ 142 #define PER_FLAG_NO_TE 1UL 143 /* Flag to enable random transaction aborts. */ 144 #define PER_FLAG_TE_ABORT_RAND 2UL 145 /* Flag to specify random transaction abort mode: 146 * - abort each transaction at a random instruction before TEND if set. 147 * - abort random transactions at a random instruction if cleared. 148 */ 149 #define PER_FLAG_TE_ABORT_RAND_TEND 4UL 150 151 typedef struct thread_struct thread_struct; 152 153 #define ARCH_MIN_TASKALIGN 8 154 155 #define INIT_THREAD { \ 156 .ksp = sizeof(init_stack) + (unsigned long) &init_stack, \ 157 .fpu.regs = (void *) init_task.thread.fpu.fprs, \ 158 .last_break = 1, \ 159 } 160 161 /* 162 * Do necessary setup to start up a new thread. 163 */ 164 #define start_thread(regs, new_psw, new_stackp) do { \ 165 regs->psw.mask = PSW_USER_BITS | PSW_MASK_EA | PSW_MASK_BA; \ 166 regs->psw.addr = new_psw; \ 167 regs->gprs[15] = new_stackp; \ 168 execve_tail(); \ 169 } while (0) 170 171 #define start_thread31(regs, new_psw, new_stackp) do { \ 172 regs->psw.mask = PSW_USER_BITS | PSW_MASK_BA; \ 173 regs->psw.addr = new_psw; \ 174 regs->gprs[15] = new_stackp; \ 175 execve_tail(); \ 176 } while (0) 177 178 /* Forward declaration, a strange C thing */ 179 struct task_struct; 180 struct mm_struct; 181 struct seq_file; 182 struct pt_regs; 183 184 void show_registers(struct pt_regs *regs); 185 void show_cacheinfo(struct seq_file *m); 186 187 /* Free all resources held by a thread. */ 188 static inline void release_thread(struct task_struct *tsk) { } 189 190 /* Free guarded storage control block */ 191 void guarded_storage_release(struct task_struct *tsk); 192 void gs_load_bc_cb(struct pt_regs *regs); 193 194 unsigned long __get_wchan(struct task_struct *p); 195 #define task_pt_regs(tsk) ((struct pt_regs *) \ 196 (task_stack_page(tsk) + THREAD_SIZE) - 1) 197 #define KSTK_EIP(tsk) (task_pt_regs(tsk)->psw.addr) 198 #define KSTK_ESP(tsk) (task_pt_regs(tsk)->gprs[15]) 199 200 /* Has task runtime instrumentation enabled ? */ 201 #define is_ri_task(tsk) (!!(tsk)->thread.ri_cb) 202 203 static __always_inline unsigned long current_stack_pointer(void) 204 { 205 unsigned long sp; 206 207 asm volatile("la %0,0(15)" : "=a" (sp)); 208 return sp; 209 } 210 211 static __always_inline unsigned short stap(void) 212 { 213 unsigned short cpu_address; 214 215 asm volatile("stap %0" : "=Q" (cpu_address)); 216 return cpu_address; 217 } 218 219 #define cpu_relax() barrier() 220 221 #define ECAG_CACHE_ATTRIBUTE 0 222 #define ECAG_CPU_ATTRIBUTE 1 223 224 static inline unsigned long __ecag(unsigned int asi, unsigned char parm) 225 { 226 unsigned long val; 227 228 asm volatile("ecag %0,0,0(%1)" : "=d" (val) : "a" (asi << 8 | parm)); 229 return val; 230 } 231 232 static inline void psw_set_key(unsigned int key) 233 { 234 asm volatile("spka 0(%0)" : : "d" (key)); 235 } 236 237 /* 238 * Set PSW to specified value. 239 */ 240 static inline void __load_psw(psw_t psw) 241 { 242 asm volatile("lpswe %0" : : "Q" (psw) : "cc"); 243 } 244 245 /* 246 * Set PSW mask to specified value, while leaving the 247 * PSW addr pointing to the next instruction. 248 */ 249 static __always_inline void __load_psw_mask(unsigned long mask) 250 { 251 unsigned long addr; 252 psw_t psw; 253 254 psw.mask = mask; 255 256 asm volatile( 257 " larl %0,1f\n" 258 " stg %0,%1\n" 259 " lpswe %2\n" 260 "1:" 261 : "=&d" (addr), "=Q" (psw.addr) : "Q" (psw) : "memory", "cc"); 262 } 263 264 /* 265 * Extract current PSW mask 266 */ 267 static inline unsigned long __extract_psw(void) 268 { 269 unsigned int reg1, reg2; 270 271 asm volatile("epsw %0,%1" : "=d" (reg1), "=a" (reg2)); 272 return (((unsigned long) reg1) << 32) | ((unsigned long) reg2); 273 } 274 275 static inline void local_mcck_enable(void) 276 { 277 __load_psw_mask(__extract_psw() | PSW_MASK_MCHECK); 278 } 279 280 static inline void local_mcck_disable(void) 281 { 282 __load_psw_mask(__extract_psw() & ~PSW_MASK_MCHECK); 283 } 284 285 /* 286 * Rewind PSW instruction address by specified number of bytes. 287 */ 288 static inline unsigned long __rewind_psw(psw_t psw, unsigned long ilc) 289 { 290 unsigned long mask; 291 292 mask = (psw.mask & PSW_MASK_EA) ? -1UL : 293 (psw.mask & PSW_MASK_BA) ? (1UL << 31) - 1 : 294 (1UL << 24) - 1; 295 return (psw.addr - ilc) & mask; 296 } 297 298 /* 299 * Function to drop a processor into disabled wait state 300 */ 301 static __always_inline void __noreturn disabled_wait(void) 302 { 303 psw_t psw; 304 305 psw.mask = PSW_MASK_BASE | PSW_MASK_WAIT | PSW_MASK_BA | PSW_MASK_EA; 306 psw.addr = _THIS_IP_; 307 __load_psw(psw); 308 while (1); 309 } 310 311 /* 312 * Basic Program Check Handler. 313 */ 314 extern void s390_base_pgm_handler(void); 315 extern void (*s390_base_pgm_handler_fn)(struct pt_regs *regs); 316 317 #define ARCH_LOW_ADDRESS_LIMIT 0x7fffffffUL 318 319 extern int memcpy_real(void *, unsigned long, size_t); 320 extern void memcpy_absolute(void *, void *, size_t); 321 322 #define put_abs_lowcore(member, x) do { \ 323 unsigned long __abs_address = offsetof(struct lowcore, member); \ 324 __typeof__(((struct lowcore *)0)->member) __tmp = (x); \ 325 \ 326 memcpy_absolute(__va(__abs_address), &__tmp, sizeof(__tmp)); \ 327 } while (0) 328 329 #define get_abs_lowcore(x, member) do { \ 330 unsigned long __abs_address = offsetof(struct lowcore, member); \ 331 __typeof__(((struct lowcore *)0)->member) *__ptr = &(x); \ 332 \ 333 memcpy_absolute(__ptr, __va(__abs_address), sizeof(*__ptr)); \ 334 } while (0) 335 336 extern int s390_isolate_bp(void); 337 extern int s390_isolate_bp_guest(void); 338 339 static __always_inline bool regs_irqs_disabled(struct pt_regs *regs) 340 { 341 return arch_irqs_disabled_flags(regs->psw.mask); 342 } 343 344 #endif /* __ASSEMBLY__ */ 345 346 #endif /* __ASM_S390_PROCESSOR_H */ 347