1 /* 2 * S390 version 3 * Copyright IBM Corp. 1999 4 * Author(s): Hartmut Penner (hp@de.ibm.com), 5 * Martin Schwidefsky (schwidefsky@de.ibm.com) 6 * 7 * Derived from "include/asm-i386/processor.h" 8 * Copyright (C) 1994, Linus Torvalds 9 */ 10 11 #ifndef __ASM_S390_PROCESSOR_H 12 #define __ASM_S390_PROCESSOR_H 13 14 #include <linux/const.h> 15 16 #define CIF_MCCK_PENDING 0 /* machine check handling is pending */ 17 #define CIF_ASCE 1 /* user asce needs fixup / uaccess */ 18 #define CIF_NOHZ_DELAY 2 /* delay HZ disable for a tick */ 19 #define CIF_FPU 3 /* restore FPU registers */ 20 #define CIF_IGNORE_IRQ 4 /* ignore interrupt (for udelay) */ 21 #define CIF_ENABLED_WAIT 5 /* in enabled wait state */ 22 23 #define _CIF_MCCK_PENDING _BITUL(CIF_MCCK_PENDING) 24 #define _CIF_ASCE _BITUL(CIF_ASCE) 25 #define _CIF_NOHZ_DELAY _BITUL(CIF_NOHZ_DELAY) 26 #define _CIF_FPU _BITUL(CIF_FPU) 27 #define _CIF_IGNORE_IRQ _BITUL(CIF_IGNORE_IRQ) 28 #define _CIF_ENABLED_WAIT _BITUL(CIF_ENABLED_WAIT) 29 30 #ifndef __ASSEMBLY__ 31 32 #include <linux/linkage.h> 33 #include <linux/irqflags.h> 34 #include <asm/cpu.h> 35 #include <asm/page.h> 36 #include <asm/ptrace.h> 37 #include <asm/setup.h> 38 #include <asm/runtime_instr.h> 39 #include <asm/fpu/types.h> 40 #include <asm/fpu/internal.h> 41 42 static inline void set_cpu_flag(int flag) 43 { 44 S390_lowcore.cpu_flags |= (1UL << flag); 45 } 46 47 static inline void clear_cpu_flag(int flag) 48 { 49 S390_lowcore.cpu_flags &= ~(1UL << flag); 50 } 51 52 static inline int test_cpu_flag(int flag) 53 { 54 return !!(S390_lowcore.cpu_flags & (1UL << flag)); 55 } 56 57 /* 58 * Test CIF flag of another CPU. The caller needs to ensure that 59 * CPU hotplug can not happen, e.g. by disabling preemption. 60 */ 61 static inline int test_cpu_flag_of(int flag, int cpu) 62 { 63 struct lowcore *lc = lowcore_ptr[cpu]; 64 return !!(lc->cpu_flags & (1UL << flag)); 65 } 66 67 #define arch_needs_cpu() test_cpu_flag(CIF_NOHZ_DELAY) 68 69 /* 70 * Default implementation of macro that returns current 71 * instruction pointer ("program counter"). 72 */ 73 #define current_text_addr() ({ void *pc; asm("basr %0,0" : "=a" (pc)); pc; }) 74 75 static inline void get_cpu_id(struct cpuid *ptr) 76 { 77 asm volatile("stidp %0" : "=Q" (*ptr)); 78 } 79 80 extern void s390_adjust_jiffies(void); 81 extern const struct seq_operations cpuinfo_op; 82 extern int sysctl_ieee_emulation_warnings; 83 extern void execve_tail(void); 84 85 /* 86 * User space process size: 2GB for 31 bit, 4TB or 8PT for 64 bit. 87 */ 88 89 #define TASK_SIZE_OF(tsk) ((tsk)->mm->context.asce_limit) 90 #define TASK_UNMAPPED_BASE (test_thread_flag(TIF_31BIT) ? \ 91 (1UL << 30) : (1UL << 41)) 92 #define TASK_SIZE TASK_SIZE_OF(current) 93 #define TASK_MAX_SIZE (1UL << 53) 94 95 #define STACK_TOP (1UL << (test_thread_flag(TIF_31BIT) ? 31:42)) 96 #define STACK_TOP_MAX (1UL << 42) 97 98 #define HAVE_ARCH_PICK_MMAP_LAYOUT 99 100 typedef struct { 101 __u32 ar4; 102 } mm_segment_t; 103 104 /* 105 * Thread structure 106 */ 107 struct thread_struct { 108 struct fpu fpu; /* FP and VX register save area */ 109 unsigned int acrs[NUM_ACRS]; 110 unsigned long ksp; /* kernel stack pointer */ 111 mm_segment_t mm_segment; 112 unsigned long gmap_addr; /* address of last gmap fault. */ 113 unsigned int gmap_pfault; /* signal of a pending guest pfault */ 114 struct per_regs per_user; /* User specified PER registers */ 115 struct per_event per_event; /* Cause of the last PER trap */ 116 unsigned long per_flags; /* Flags to control debug behavior */ 117 /* pfault_wait is used to block the process on a pfault event */ 118 unsigned long pfault_wait; 119 struct list_head list; 120 /* cpu runtime instrumentation */ 121 struct runtime_instr_cb *ri_cb; 122 unsigned char trap_tdb[256]; /* Transaction abort diagnose block */ 123 }; 124 125 /* Flag to disable transactions. */ 126 #define PER_FLAG_NO_TE 1UL 127 /* Flag to enable random transaction aborts. */ 128 #define PER_FLAG_TE_ABORT_RAND 2UL 129 /* Flag to specify random transaction abort mode: 130 * - abort each transaction at a random instruction before TEND if set. 131 * - abort random transactions at a random instruction if cleared. 132 */ 133 #define PER_FLAG_TE_ABORT_RAND_TEND 4UL 134 135 typedef struct thread_struct thread_struct; 136 137 /* 138 * Stack layout of a C stack frame. 139 */ 140 #ifndef __PACK_STACK 141 struct stack_frame { 142 unsigned long back_chain; 143 unsigned long empty1[5]; 144 unsigned long gprs[10]; 145 unsigned int empty2[8]; 146 }; 147 #else 148 struct stack_frame { 149 unsigned long empty1[5]; 150 unsigned int empty2[8]; 151 unsigned long gprs[10]; 152 unsigned long back_chain; 153 }; 154 #endif 155 156 #define ARCH_MIN_TASKALIGN 8 157 158 extern __vector128 init_task_fpu_regs[__NUM_VXRS]; 159 #define INIT_THREAD { \ 160 .ksp = sizeof(init_stack) + (unsigned long) &init_stack, \ 161 .fpu.regs = (void *)&init_task_fpu_regs, \ 162 } 163 164 /* 165 * Do necessary setup to start up a new thread. 166 */ 167 #define start_thread(regs, new_psw, new_stackp) do { \ 168 regs->psw.mask = PSW_USER_BITS | PSW_MASK_EA | PSW_MASK_BA; \ 169 regs->psw.addr = new_psw | PSW_ADDR_AMODE; \ 170 regs->gprs[15] = new_stackp; \ 171 execve_tail(); \ 172 } while (0) 173 174 #define start_thread31(regs, new_psw, new_stackp) do { \ 175 regs->psw.mask = PSW_USER_BITS | PSW_MASK_BA; \ 176 regs->psw.addr = new_psw | PSW_ADDR_AMODE; \ 177 regs->gprs[15] = new_stackp; \ 178 crst_table_downgrade(current->mm, 1UL << 31); \ 179 execve_tail(); \ 180 } while (0) 181 182 /* Forward declaration, a strange C thing */ 183 struct task_struct; 184 struct mm_struct; 185 struct seq_file; 186 187 void show_cacheinfo(struct seq_file *m); 188 189 /* Free all resources held by a thread. */ 190 extern void release_thread(struct task_struct *); 191 192 /* 193 * Return saved PC of a blocked thread. 194 */ 195 extern unsigned long thread_saved_pc(struct task_struct *t); 196 197 unsigned long get_wchan(struct task_struct *p); 198 #define task_pt_regs(tsk) ((struct pt_regs *) \ 199 (task_stack_page(tsk) + THREAD_SIZE) - 1) 200 #define KSTK_EIP(tsk) (task_pt_regs(tsk)->psw.addr) 201 #define KSTK_ESP(tsk) (task_pt_regs(tsk)->gprs[15]) 202 203 /* Has task runtime instrumentation enabled ? */ 204 #define is_ri_task(tsk) (!!(tsk)->thread.ri_cb) 205 206 static inline unsigned short stap(void) 207 { 208 unsigned short cpu_address; 209 210 asm volatile("stap %0" : "=m" (cpu_address)); 211 return cpu_address; 212 } 213 214 /* 215 * Give up the time slice of the virtual PU. 216 */ 217 void cpu_relax(void); 218 219 #define cpu_relax_lowlatency() barrier() 220 221 static inline void psw_set_key(unsigned int key) 222 { 223 asm volatile("spka 0(%0)" : : "d" (key)); 224 } 225 226 /* 227 * Set PSW to specified value. 228 */ 229 static inline void __load_psw(psw_t psw) 230 { 231 asm volatile("lpswe %0" : : "Q" (psw) : "cc"); 232 } 233 234 /* 235 * Set PSW mask to specified value, while leaving the 236 * PSW addr pointing to the next instruction. 237 */ 238 static inline void __load_psw_mask(unsigned long mask) 239 { 240 unsigned long addr; 241 psw_t psw; 242 243 psw.mask = mask; 244 245 asm volatile( 246 " larl %0,1f\n" 247 " stg %0,%O1+8(%R1)\n" 248 " lpswe %1\n" 249 "1:" 250 : "=&d" (addr), "=Q" (psw) : "Q" (psw) : "memory", "cc"); 251 } 252 253 /* 254 * Extract current PSW mask 255 */ 256 static inline unsigned long __extract_psw(void) 257 { 258 unsigned int reg1, reg2; 259 260 asm volatile("epsw %0,%1" : "=d" (reg1), "=a" (reg2)); 261 return (((unsigned long) reg1) << 32) | ((unsigned long) reg2); 262 } 263 264 static inline void local_mcck_enable(void) 265 { 266 __load_psw_mask(__extract_psw() | PSW_MASK_MCHECK); 267 } 268 269 static inline void local_mcck_disable(void) 270 { 271 __load_psw_mask(__extract_psw() & ~PSW_MASK_MCHECK); 272 } 273 274 /* 275 * Rewind PSW instruction address by specified number of bytes. 276 */ 277 static inline unsigned long __rewind_psw(psw_t psw, unsigned long ilc) 278 { 279 unsigned long mask; 280 281 mask = (psw.mask & PSW_MASK_EA) ? -1UL : 282 (psw.mask & PSW_MASK_BA) ? (1UL << 31) - 1 : 283 (1UL << 24) - 1; 284 return (psw.addr - ilc) & mask; 285 } 286 287 /* 288 * Function to stop a processor until the next interrupt occurs 289 */ 290 void enabled_wait(void); 291 292 /* 293 * Function to drop a processor into disabled wait state 294 */ 295 static inline void __noreturn disabled_wait(unsigned long code) 296 { 297 psw_t psw; 298 299 psw.mask = PSW_MASK_BASE | PSW_MASK_WAIT | PSW_MASK_BA | PSW_MASK_EA; 300 psw.addr = code; 301 __load_psw(psw); 302 while (1); 303 } 304 305 /* 306 * Basic Machine Check/Program Check Handler. 307 */ 308 309 extern void s390_base_mcck_handler(void); 310 extern void s390_base_pgm_handler(void); 311 extern void s390_base_ext_handler(void); 312 313 extern void (*s390_base_mcck_handler_fn)(void); 314 extern void (*s390_base_pgm_handler_fn)(void); 315 extern void (*s390_base_ext_handler_fn)(void); 316 317 #define ARCH_LOW_ADDRESS_LIMIT 0x7fffffffUL 318 319 extern int memcpy_real(void *, void *, size_t); 320 extern void memcpy_absolute(void *, void *, size_t); 321 322 #define mem_assign_absolute(dest, val) { \ 323 __typeof__(dest) __tmp = (val); \ 324 \ 325 BUILD_BUG_ON(sizeof(__tmp) != sizeof(val)); \ 326 memcpy_absolute(&(dest), &__tmp, sizeof(__tmp)); \ 327 } 328 329 #endif /* __ASSEMBLY__ */ 330 331 #endif /* __ASM_S390_PROCESSOR_H */ 332