xref: /openbmc/linux/arch/s390/include/asm/processor.h (revision 9cfc5c90)
1 /*
2  *  S390 version
3  *    Copyright IBM Corp. 1999
4  *    Author(s): Hartmut Penner (hp@de.ibm.com),
5  *               Martin Schwidefsky (schwidefsky@de.ibm.com)
6  *
7  *  Derived from "include/asm-i386/processor.h"
8  *    Copyright (C) 1994, Linus Torvalds
9  */
10 
11 #ifndef __ASM_S390_PROCESSOR_H
12 #define __ASM_S390_PROCESSOR_H
13 
14 #include <linux/const.h>
15 
16 #define CIF_MCCK_PENDING	0	/* machine check handling is pending */
17 #define CIF_ASCE		1	/* user asce needs fixup / uaccess */
18 #define CIF_NOHZ_DELAY		2	/* delay HZ disable for a tick */
19 #define CIF_FPU			3	/* restore FPU registers */
20 #define CIF_IGNORE_IRQ		4	/* ignore interrupt (for udelay) */
21 
22 #define _CIF_MCCK_PENDING	_BITUL(CIF_MCCK_PENDING)
23 #define _CIF_ASCE		_BITUL(CIF_ASCE)
24 #define _CIF_NOHZ_DELAY		_BITUL(CIF_NOHZ_DELAY)
25 #define _CIF_FPU		_BITUL(CIF_FPU)
26 #define _CIF_IGNORE_IRQ		_BITUL(CIF_IGNORE_IRQ)
27 
28 #ifndef __ASSEMBLY__
29 
30 #include <linux/linkage.h>
31 #include <linux/irqflags.h>
32 #include <asm/cpu.h>
33 #include <asm/page.h>
34 #include <asm/ptrace.h>
35 #include <asm/setup.h>
36 #include <asm/runtime_instr.h>
37 #include <asm/fpu/types.h>
38 #include <asm/fpu/internal.h>
39 
40 static inline void set_cpu_flag(int flag)
41 {
42 	S390_lowcore.cpu_flags |= (1UL << flag);
43 }
44 
45 static inline void clear_cpu_flag(int flag)
46 {
47 	S390_lowcore.cpu_flags &= ~(1UL << flag);
48 }
49 
50 static inline int test_cpu_flag(int flag)
51 {
52 	return !!(S390_lowcore.cpu_flags & (1UL << flag));
53 }
54 
55 #define arch_needs_cpu() test_cpu_flag(CIF_NOHZ_DELAY)
56 
57 /*
58  * Default implementation of macro that returns current
59  * instruction pointer ("program counter").
60  */
61 #define current_text_addr() ({ void *pc; asm("basr %0,0" : "=a" (pc)); pc; })
62 
63 static inline void get_cpu_id(struct cpuid *ptr)
64 {
65 	asm volatile("stidp %0" : "=Q" (*ptr));
66 }
67 
68 extern void s390_adjust_jiffies(void);
69 extern const struct seq_operations cpuinfo_op;
70 extern int sysctl_ieee_emulation_warnings;
71 extern void execve_tail(void);
72 
73 /*
74  * User space process size: 2GB for 31 bit, 4TB or 8PT for 64 bit.
75  */
76 
77 #define TASK_SIZE_OF(tsk)	((tsk)->mm->context.asce_limit)
78 #define TASK_UNMAPPED_BASE	(test_thread_flag(TIF_31BIT) ? \
79 					(1UL << 30) : (1UL << 41))
80 #define TASK_SIZE		TASK_SIZE_OF(current)
81 #define TASK_MAX_SIZE		(1UL << 53)
82 
83 #define STACK_TOP		(1UL << (test_thread_flag(TIF_31BIT) ? 31:42))
84 #define STACK_TOP_MAX		(1UL << 42)
85 
86 #define HAVE_ARCH_PICK_MMAP_LAYOUT
87 
88 typedef struct {
89         __u32 ar4;
90 } mm_segment_t;
91 
92 /*
93  * Thread structure
94  */
95 struct thread_struct {
96 	struct fpu fpu;			/* FP and VX register save area */
97 	unsigned int  acrs[NUM_ACRS];
98         unsigned long ksp;              /* kernel stack pointer             */
99 	mm_segment_t mm_segment;
100 	unsigned long gmap_addr;	/* address of last gmap fault. */
101 	unsigned int gmap_pfault;	/* signal of a pending guest pfault */
102 	struct per_regs per_user;	/* User specified PER registers */
103 	struct per_event per_event;	/* Cause of the last PER trap */
104 	unsigned long per_flags;	/* Flags to control debug behavior */
105         /* pfault_wait is used to block the process on a pfault event */
106 	unsigned long pfault_wait;
107 	struct list_head list;
108 	/* cpu runtime instrumentation */
109 	struct runtime_instr_cb *ri_cb;
110 	unsigned char trap_tdb[256];	/* Transaction abort diagnose block */
111 };
112 
113 /* Flag to disable transactions. */
114 #define PER_FLAG_NO_TE			1UL
115 /* Flag to enable random transaction aborts. */
116 #define PER_FLAG_TE_ABORT_RAND		2UL
117 /* Flag to specify random transaction abort mode:
118  * - abort each transaction at a random instruction before TEND if set.
119  * - abort random transactions at a random instruction if cleared.
120  */
121 #define PER_FLAG_TE_ABORT_RAND_TEND	4UL
122 
123 typedef struct thread_struct thread_struct;
124 
125 /*
126  * Stack layout of a C stack frame.
127  */
128 #ifndef __PACK_STACK
129 struct stack_frame {
130 	unsigned long back_chain;
131 	unsigned long empty1[5];
132 	unsigned long gprs[10];
133 	unsigned int  empty2[8];
134 };
135 #else
136 struct stack_frame {
137 	unsigned long empty1[5];
138 	unsigned int  empty2[8];
139 	unsigned long gprs[10];
140 	unsigned long back_chain;
141 };
142 #endif
143 
144 #define ARCH_MIN_TASKALIGN	8
145 
146 extern __vector128 init_task_fpu_regs[__NUM_VXRS];
147 #define INIT_THREAD {							\
148 	.ksp = sizeof(init_stack) + (unsigned long) &init_stack,	\
149 	.fpu.regs = (void *)&init_task_fpu_regs,			\
150 }
151 
152 /*
153  * Do necessary setup to start up a new thread.
154  */
155 #define start_thread(regs, new_psw, new_stackp) do {			\
156 	regs->psw.mask	= PSW_USER_BITS | PSW_MASK_EA | PSW_MASK_BA;	\
157 	regs->psw.addr	= new_psw | PSW_ADDR_AMODE;			\
158 	regs->gprs[15]	= new_stackp;					\
159 	execve_tail();							\
160 } while (0)
161 
162 #define start_thread31(regs, new_psw, new_stackp) do {			\
163 	regs->psw.mask	= PSW_USER_BITS | PSW_MASK_BA;			\
164 	regs->psw.addr	= new_psw | PSW_ADDR_AMODE;			\
165 	regs->gprs[15]	= new_stackp;					\
166 	crst_table_downgrade(current->mm, 1UL << 31);			\
167 	execve_tail();							\
168 } while (0)
169 
170 /* Forward declaration, a strange C thing */
171 struct task_struct;
172 struct mm_struct;
173 struct seq_file;
174 
175 void show_cacheinfo(struct seq_file *m);
176 
177 /* Free all resources held by a thread. */
178 extern void release_thread(struct task_struct *);
179 
180 /*
181  * Return saved PC of a blocked thread.
182  */
183 extern unsigned long thread_saved_pc(struct task_struct *t);
184 
185 unsigned long get_wchan(struct task_struct *p);
186 #define task_pt_regs(tsk) ((struct pt_regs *) \
187         (task_stack_page(tsk) + THREAD_SIZE) - 1)
188 #define KSTK_EIP(tsk)	(task_pt_regs(tsk)->psw.addr)
189 #define KSTK_ESP(tsk)	(task_pt_regs(tsk)->gprs[15])
190 
191 /* Has task runtime instrumentation enabled ? */
192 #define is_ri_task(tsk) (!!(tsk)->thread.ri_cb)
193 
194 static inline unsigned short stap(void)
195 {
196 	unsigned short cpu_address;
197 
198 	asm volatile("stap %0" : "=m" (cpu_address));
199 	return cpu_address;
200 }
201 
202 /*
203  * Give up the time slice of the virtual PU.
204  */
205 void cpu_relax(void);
206 
207 #define cpu_relax_lowlatency()  barrier()
208 
209 static inline void psw_set_key(unsigned int key)
210 {
211 	asm volatile("spka 0(%0)" : : "d" (key));
212 }
213 
214 /*
215  * Set PSW to specified value.
216  */
217 static inline void __load_psw(psw_t psw)
218 {
219 	asm volatile("lpswe %0" : : "Q" (psw) : "cc");
220 }
221 
222 /*
223  * Set PSW mask to specified value, while leaving the
224  * PSW addr pointing to the next instruction.
225  */
226 static inline void __load_psw_mask(unsigned long mask)
227 {
228 	unsigned long addr;
229 	psw_t psw;
230 
231 	psw.mask = mask;
232 
233 	asm volatile(
234 		"	larl	%0,1f\n"
235 		"	stg	%0,%O1+8(%R1)\n"
236 		"	lpswe	%1\n"
237 		"1:"
238 		: "=&d" (addr), "=Q" (psw) : "Q" (psw) : "memory", "cc");
239 }
240 
241 /*
242  * Extract current PSW mask
243  */
244 static inline unsigned long __extract_psw(void)
245 {
246 	unsigned int reg1, reg2;
247 
248 	asm volatile("epsw %0,%1" : "=d" (reg1), "=a" (reg2));
249 	return (((unsigned long) reg1) << 32) | ((unsigned long) reg2);
250 }
251 
252 static inline void local_mcck_enable(void)
253 {
254 	__load_psw_mask(__extract_psw() | PSW_MASK_MCHECK);
255 }
256 
257 static inline void local_mcck_disable(void)
258 {
259 	__load_psw_mask(__extract_psw() & ~PSW_MASK_MCHECK);
260 }
261 
262 /*
263  * Rewind PSW instruction address by specified number of bytes.
264  */
265 static inline unsigned long __rewind_psw(psw_t psw, unsigned long ilc)
266 {
267 	unsigned long mask;
268 
269 	mask = (psw.mask & PSW_MASK_EA) ? -1UL :
270 	       (psw.mask & PSW_MASK_BA) ? (1UL << 31) - 1 :
271 					  (1UL << 24) - 1;
272 	return (psw.addr - ilc) & mask;
273 }
274 
275 /*
276  * Function to stop a processor until the next interrupt occurs
277  */
278 void enabled_wait(void);
279 
280 /*
281  * Function to drop a processor into disabled wait state
282  */
283 static inline void __noreturn disabled_wait(unsigned long code)
284 {
285 	psw_t psw;
286 
287 	psw.mask = PSW_MASK_BASE | PSW_MASK_WAIT | PSW_MASK_BA | PSW_MASK_EA;
288 	psw.addr = code;
289 	__load_psw(psw);
290 	while (1);
291 }
292 
293 /*
294  * Basic Machine Check/Program Check Handler.
295  */
296 
297 extern void s390_base_mcck_handler(void);
298 extern void s390_base_pgm_handler(void);
299 extern void s390_base_ext_handler(void);
300 
301 extern void (*s390_base_mcck_handler_fn)(void);
302 extern void (*s390_base_pgm_handler_fn)(void);
303 extern void (*s390_base_ext_handler_fn)(void);
304 
305 #define ARCH_LOW_ADDRESS_LIMIT	0x7fffffffUL
306 
307 extern int memcpy_real(void *, void *, size_t);
308 extern void memcpy_absolute(void *, void *, size_t);
309 
310 #define mem_assign_absolute(dest, val) {			\
311 	__typeof__(dest) __tmp = (val);				\
312 								\
313 	BUILD_BUG_ON(sizeof(__tmp) != sizeof(val));		\
314 	memcpy_absolute(&(dest), &__tmp, sizeof(__tmp));	\
315 }
316 
317 #endif /* __ASSEMBLY__ */
318 
319 #endif /* __ASM_S390_PROCESSOR_H */
320