1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * S390 version 4 * Copyright IBM Corp. 1999 5 * Author(s): Hartmut Penner (hp@de.ibm.com), 6 * Martin Schwidefsky (schwidefsky@de.ibm.com) 7 * 8 * Derived from "include/asm-i386/processor.h" 9 * Copyright (C) 1994, Linus Torvalds 10 */ 11 12 #ifndef __ASM_S390_PROCESSOR_H 13 #define __ASM_S390_PROCESSOR_H 14 15 #include <linux/bits.h> 16 17 #define CIF_NOHZ_DELAY 2 /* delay HZ disable for a tick */ 18 #define CIF_FPU 3 /* restore FPU registers */ 19 #define CIF_ENABLED_WAIT 5 /* in enabled wait state */ 20 #define CIF_MCCK_GUEST 6 /* machine check happening in guest */ 21 #define CIF_DEDICATED_CPU 7 /* this CPU is dedicated */ 22 23 #define _CIF_NOHZ_DELAY BIT(CIF_NOHZ_DELAY) 24 #define _CIF_FPU BIT(CIF_FPU) 25 #define _CIF_ENABLED_WAIT BIT(CIF_ENABLED_WAIT) 26 #define _CIF_MCCK_GUEST BIT(CIF_MCCK_GUEST) 27 #define _CIF_DEDICATED_CPU BIT(CIF_DEDICATED_CPU) 28 29 #define RESTART_FLAG_CTLREGS _AC(1 << 0, U) 30 31 #ifndef __ASSEMBLY__ 32 33 #include <linux/cpumask.h> 34 #include <linux/linkage.h> 35 #include <linux/irqflags.h> 36 #include <asm/cpu.h> 37 #include <asm/page.h> 38 #include <asm/ptrace.h> 39 #include <asm/setup.h> 40 #include <asm/runtime_instr.h> 41 #include <asm/fpu/types.h> 42 #include <asm/fpu/internal.h> 43 #include <asm/irqflags.h> 44 45 typedef long (*sys_call_ptr_t)(struct pt_regs *regs); 46 47 static __always_inline void set_cpu_flag(int flag) 48 { 49 S390_lowcore.cpu_flags |= (1UL << flag); 50 } 51 52 static __always_inline void clear_cpu_flag(int flag) 53 { 54 S390_lowcore.cpu_flags &= ~(1UL << flag); 55 } 56 57 static __always_inline bool test_cpu_flag(int flag) 58 { 59 return S390_lowcore.cpu_flags & (1UL << flag); 60 } 61 62 static __always_inline bool test_and_set_cpu_flag(int flag) 63 { 64 if (test_cpu_flag(flag)) 65 return true; 66 set_cpu_flag(flag); 67 return false; 68 } 69 70 static __always_inline bool test_and_clear_cpu_flag(int flag) 71 { 72 if (!test_cpu_flag(flag)) 73 return false; 74 clear_cpu_flag(flag); 75 return true; 76 } 77 78 /* 79 * Test CIF flag of another CPU. The caller needs to ensure that 80 * CPU hotplug can not happen, e.g. by disabling preemption. 81 */ 82 static __always_inline bool test_cpu_flag_of(int flag, int cpu) 83 { 84 struct lowcore *lc = lowcore_ptr[cpu]; 85 86 return lc->cpu_flags & (1UL << flag); 87 } 88 89 #define arch_needs_cpu() test_cpu_flag(CIF_NOHZ_DELAY) 90 91 static inline void get_cpu_id(struct cpuid *ptr) 92 { 93 asm volatile("stidp %0" : "=Q" (*ptr)); 94 } 95 96 void s390_adjust_jiffies(void); 97 void s390_update_cpu_mhz(void); 98 void cpu_detect_mhz_feature(void); 99 100 extern const struct seq_operations cpuinfo_op; 101 extern void execve_tail(void); 102 unsigned long vdso_size(void); 103 104 /* 105 * User space process size: 2GB for 31 bit, 4TB or 8PT for 64 bit. 106 */ 107 108 #define TASK_SIZE (test_thread_flag(TIF_31BIT) ? \ 109 _REGION3_SIZE : TASK_SIZE_MAX) 110 #define TASK_UNMAPPED_BASE (test_thread_flag(TIF_31BIT) ? \ 111 (_REGION3_SIZE >> 1) : (_REGION2_SIZE >> 1)) 112 #define TASK_SIZE_MAX (-PAGE_SIZE) 113 114 #define VDSO_BASE (STACK_TOP + PAGE_SIZE) 115 #define VDSO_LIMIT (test_thread_flag(TIF_31BIT) ? _REGION3_SIZE : _REGION2_SIZE) 116 #define STACK_TOP (VDSO_LIMIT - vdso_size() - PAGE_SIZE) 117 #define STACK_TOP_MAX (_REGION2_SIZE - vdso_size() - PAGE_SIZE) 118 119 #define HAVE_ARCH_PICK_MMAP_LAYOUT 120 121 #define __stackleak_poison __stackleak_poison 122 static __always_inline void __stackleak_poison(unsigned long erase_low, 123 unsigned long erase_high, 124 unsigned long poison) 125 { 126 unsigned long tmp, count; 127 128 count = erase_high - erase_low; 129 if (!count) 130 return; 131 asm volatile( 132 " cghi %[count],8\n" 133 " je 2f\n" 134 " aghi %[count],-(8+1)\n" 135 " srlg %[tmp],%[count],8\n" 136 " ltgr %[tmp],%[tmp]\n" 137 " jz 1f\n" 138 "0: stg %[poison],0(%[addr])\n" 139 " mvc 8(256-8,%[addr]),0(%[addr])\n" 140 " la %[addr],256(%[addr])\n" 141 " brctg %[tmp],0b\n" 142 "1: stg %[poison],0(%[addr])\n" 143 " larl %[tmp],3f\n" 144 " ex %[count],0(%[tmp])\n" 145 " j 4f\n" 146 "2: stg %[poison],0(%[addr])\n" 147 " j 4f\n" 148 "3: mvc 8(1,%[addr]),0(%[addr])\n" 149 "4:\n" 150 : [addr] "+&a" (erase_low), [count] "+&d" (count), [tmp] "=&a" (tmp) 151 : [poison] "d" (poison) 152 : "memory", "cc" 153 ); 154 } 155 156 /* 157 * Thread structure 158 */ 159 struct thread_struct { 160 unsigned int acrs[NUM_ACRS]; 161 unsigned long ksp; /* kernel stack pointer */ 162 unsigned long user_timer; /* task cputime in user space */ 163 unsigned long guest_timer; /* task cputime in kvm guest */ 164 unsigned long system_timer; /* task cputime in kernel space */ 165 unsigned long hardirq_timer; /* task cputime in hardirq context */ 166 unsigned long softirq_timer; /* task cputime in softirq context */ 167 const sys_call_ptr_t *sys_call_table; /* system call table address */ 168 unsigned long gmap_addr; /* address of last gmap fault. */ 169 unsigned int gmap_write_flag; /* gmap fault write indication */ 170 unsigned int gmap_int_code; /* int code of last gmap fault */ 171 unsigned int gmap_pfault; /* signal of a pending guest pfault */ 172 173 /* Per-thread information related to debugging */ 174 struct per_regs per_user; /* User specified PER registers */ 175 struct per_event per_event; /* Cause of the last PER trap */ 176 unsigned long per_flags; /* Flags to control debug behavior */ 177 unsigned int system_call; /* system call number in signal */ 178 unsigned long last_break; /* last breaking-event-address. */ 179 /* pfault_wait is used to block the process on a pfault event */ 180 unsigned long pfault_wait; 181 struct list_head list; 182 /* cpu runtime instrumentation */ 183 struct runtime_instr_cb *ri_cb; 184 struct gs_cb *gs_cb; /* Current guarded storage cb */ 185 struct gs_cb *gs_bc_cb; /* Broadcast guarded storage cb */ 186 struct pgm_tdb trap_tdb; /* Transaction abort diagnose block */ 187 /* 188 * Warning: 'fpu' is dynamically-sized. It *MUST* be at 189 * the end. 190 */ 191 struct fpu fpu; /* FP and VX register save area */ 192 }; 193 194 /* Flag to disable transactions. */ 195 #define PER_FLAG_NO_TE 1UL 196 /* Flag to enable random transaction aborts. */ 197 #define PER_FLAG_TE_ABORT_RAND 2UL 198 /* Flag to specify random transaction abort mode: 199 * - abort each transaction at a random instruction before TEND if set. 200 * - abort random transactions at a random instruction if cleared. 201 */ 202 #define PER_FLAG_TE_ABORT_RAND_TEND 4UL 203 204 typedef struct thread_struct thread_struct; 205 206 #define ARCH_MIN_TASKALIGN 8 207 208 #define INIT_THREAD { \ 209 .ksp = sizeof(init_stack) + (unsigned long) &init_stack, \ 210 .fpu.regs = (void *) init_task.thread.fpu.fprs, \ 211 .last_break = 1, \ 212 } 213 214 /* 215 * Do necessary setup to start up a new thread. 216 */ 217 #define start_thread(regs, new_psw, new_stackp) do { \ 218 regs->psw.mask = PSW_USER_BITS | PSW_MASK_EA | PSW_MASK_BA; \ 219 regs->psw.addr = new_psw; \ 220 regs->gprs[15] = new_stackp; \ 221 execve_tail(); \ 222 } while (0) 223 224 #define start_thread31(regs, new_psw, new_stackp) do { \ 225 regs->psw.mask = PSW_USER_BITS | PSW_MASK_BA; \ 226 regs->psw.addr = new_psw; \ 227 regs->gprs[15] = new_stackp; \ 228 execve_tail(); \ 229 } while (0) 230 231 /* Forward declaration, a strange C thing */ 232 struct task_struct; 233 struct mm_struct; 234 struct seq_file; 235 struct pt_regs; 236 237 void show_registers(struct pt_regs *regs); 238 void show_cacheinfo(struct seq_file *m); 239 240 /* Free guarded storage control block */ 241 void guarded_storage_release(struct task_struct *tsk); 242 void gs_load_bc_cb(struct pt_regs *regs); 243 244 unsigned long __get_wchan(struct task_struct *p); 245 #define task_pt_regs(tsk) ((struct pt_regs *) \ 246 (task_stack_page(tsk) + THREAD_SIZE) - 1) 247 #define KSTK_EIP(tsk) (task_pt_regs(tsk)->psw.addr) 248 #define KSTK_ESP(tsk) (task_pt_regs(tsk)->gprs[15]) 249 250 /* Has task runtime instrumentation enabled ? */ 251 #define is_ri_task(tsk) (!!(tsk)->thread.ri_cb) 252 253 /* avoid using global register due to gcc bug in versions < 8.4 */ 254 #define current_stack_pointer (__current_stack_pointer()) 255 256 static __always_inline unsigned long __current_stack_pointer(void) 257 { 258 unsigned long sp; 259 260 asm volatile("lgr %0,15" : "=d" (sp)); 261 return sp; 262 } 263 264 static __always_inline bool on_thread_stack(void) 265 { 266 unsigned long ksp = S390_lowcore.kernel_stack; 267 268 return !((ksp ^ current_stack_pointer) & ~(THREAD_SIZE - 1)); 269 } 270 271 static __always_inline unsigned short stap(void) 272 { 273 unsigned short cpu_address; 274 275 asm volatile("stap %0" : "=Q" (cpu_address)); 276 return cpu_address; 277 } 278 279 #define cpu_relax() barrier() 280 281 #define ECAG_CACHE_ATTRIBUTE 0 282 #define ECAG_CPU_ATTRIBUTE 1 283 284 static inline unsigned long __ecag(unsigned int asi, unsigned char parm) 285 { 286 unsigned long val; 287 288 asm volatile("ecag %0,0,0(%1)" : "=d" (val) : "a" (asi << 8 | parm)); 289 return val; 290 } 291 292 static inline void psw_set_key(unsigned int key) 293 { 294 asm volatile("spka 0(%0)" : : "d" (key)); 295 } 296 297 /* 298 * Set PSW to specified value. 299 */ 300 static inline void __load_psw(psw_t psw) 301 { 302 asm volatile("lpswe %0" : : "Q" (psw) : "cc"); 303 } 304 305 /* 306 * Set PSW mask to specified value, while leaving the 307 * PSW addr pointing to the next instruction. 308 */ 309 static __always_inline void __load_psw_mask(unsigned long mask) 310 { 311 psw_t psw __uninitialized; 312 unsigned long addr; 313 314 psw.mask = mask; 315 316 asm volatile( 317 " larl %0,1f\n" 318 " stg %0,%1\n" 319 " lpswe %2\n" 320 "1:" 321 : "=&d" (addr), "=Q" (psw.addr) : "Q" (psw) : "memory", "cc"); 322 } 323 324 /* 325 * Extract current PSW mask 326 */ 327 static inline unsigned long __extract_psw(void) 328 { 329 unsigned int reg1, reg2; 330 331 asm volatile("epsw %0,%1" : "=d" (reg1), "=a" (reg2)); 332 return (((unsigned long) reg1) << 32) | ((unsigned long) reg2); 333 } 334 335 static inline void local_mcck_enable(void) 336 { 337 __load_psw_mask(__extract_psw() | PSW_MASK_MCHECK); 338 } 339 340 static inline void local_mcck_disable(void) 341 { 342 __load_psw_mask(__extract_psw() & ~PSW_MASK_MCHECK); 343 } 344 345 /* 346 * Rewind PSW instruction address by specified number of bytes. 347 */ 348 static inline unsigned long __rewind_psw(psw_t psw, unsigned long ilc) 349 { 350 unsigned long mask; 351 352 mask = (psw.mask & PSW_MASK_EA) ? -1UL : 353 (psw.mask & PSW_MASK_BA) ? (1UL << 31) - 1 : 354 (1UL << 24) - 1; 355 return (psw.addr - ilc) & mask; 356 } 357 358 /* 359 * Function to drop a processor into disabled wait state 360 */ 361 static __always_inline void __noreturn disabled_wait(void) 362 { 363 psw_t psw; 364 365 psw.mask = PSW_MASK_BASE | PSW_MASK_WAIT | PSW_MASK_BA | PSW_MASK_EA; 366 psw.addr = _THIS_IP_; 367 __load_psw(psw); 368 while (1); 369 } 370 371 #define ARCH_LOW_ADDRESS_LIMIT 0x7fffffffUL 372 373 static __always_inline bool regs_irqs_disabled(struct pt_regs *regs) 374 { 375 return arch_irqs_disabled_flags(regs->psw.mask); 376 } 377 378 #endif /* __ASSEMBLY__ */ 379 380 #endif /* __ASM_S390_PROCESSOR_H */ 381